54HC373

54HC373 SS

Document overview

• PDF pages: 7

Technical content

Page 1

Rev 1.0

8-bit transparent D-Type Latch with 3-State Outputs in bare die form

Description

The 54HC373 consists of eight D-type transparent latches fabricated using a 2.5µm 5V CMOS process to combine high speed performance LSTTL performance with CMOS low power consumption. Each latch is equipped with separate D-Type inputs and 3-State outputs for bus oriented applications. Data output changes asynchronously and data may be latched even when the outputs are not enabled. Device inputs accept standard CMOS outputs or LSTTL outputs using pull-up resistors. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Ordering Information

The following part suffixes apply:

 No suffix - MIL-STD-883 /2010B Visual Inspection

 “H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

 “K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

 Default – Die in Waffle Pack (100 per tray capacity)

 Sawn Wafer on Tape – On request

 Unsawn Wafer – On request

 Die Thickness <> 350µm(14 Mils) – On request

 Assembled into Ceramic Package – On request

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10/03/21

Features:

 Output Drive Capability: 15 LSTTL Loads

 Low Input Current: 1µA

 Outputs directly interface CMOS, NMOS and TTL

 Operating Voltage Range: 2V to 6V

 CMOS High Noise Immunity

 Function compatible with 54LS373

 Full Military Temperature Range.

Die Dimensions in µm (mils)

1460 (57)

Mechanical Specification

Page 2

Rev 1.0

Pad Layout and Functions

10/03/21

1460µm (57.48 mils)

Logic Diagram

Truth Table

Pad 10 = GND, Pad 20 = VCC

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Page 3

Rev 1.0

Absolute Maximum Ratings1

10/03/21

1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.

Recommended Operating Conditions3 (Voltages referenced to GND)

1. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

DC Electrical Characteristics (Voltages Referenced to GND)

1. -55˚C ≤ TJ ≤ +125˚C

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Page 4

Rev 1.0

10/03/21

DC Electrical Characteristics Continued (Voltages referenced to GND)

AC Electrical Characteristics5

5 Not production tested in die form, characterized by chip design

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Page 5

Rev 1.0

10/03/21

AC Electrical Characteristics continued5

2f + ICC VCC.

1. Used to determine the no-load dynamic power consumption: PD = CPD VCC

Timing Requirements6

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Page 6

Switching Waveforms

Figure 1 – Propagation Delay & Output Transition Time

Figure 3 – Propagation Delay - Output Enable to Q

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Rev 1.0

10/03/21

Figure 2 – Propagation Delay – Latch Enable to Q

Figure 4 – Timing Requirements

Page 7

Rev 1.0

07/02/19

Test Circuits

TEST POINT

\* Includes all probe and jig capacitance

Figure 5

TEST POINT

CONNECT TO VCC WHEN

TESTING tPLZ,& tPZL.

CONNECT TO GND WHEN

TESTING tPHZ,& tPZH

\* Includes all probe and jig capacitance

Figure 6

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