54HC244 Datasheet PDF & Specifications

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74HC244 SS

Document overview

PDF pages: 6

Technical content

Page 1

Rev 1.1

Octal 3-State Non-Inverting Buffer / Line Driver / Line Receiver in bare die form

Description

The 74HC244 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The device can be used as two 4-bit buffers or one 8-bit buffer and features non-inverting inputs with two output enables, each controlling four of the 3-state outputs. The device is specifically designed to improve performance and density in clock drivers, 3-state memory address drivers and bus orientated transmitters and receivers. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

For High Reliability versions of this product please see

54HC244

Supply Formats:

Default – Die in Waffle Pack (100 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

Page 1 of 6

01/05/18

Features:

Output Drive Capability: 15 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

Function compatible with 74LS244.

Die Dimensions in µm (mils)

1900 (75)

Mechanical Specification

Die Size (Unsawn)	1900 x 2050 75 x 81	µm mils
Minimum Bond Pad Size	100 x 100 3.94 x 3.94	µm mils
Die Thickness	350 (±20) 13.78 (±0.79)	µm mils
Top Metal Composition	Al 1%Si 1.1µm
Back Metal Composition	N/A – Bare Si

Page 2

Rev 1.1

01/05/18

Pad Layout and Functions

	2 1 20 19 18 3 17 4 16 5 DIE ID 15 6 14 7 13 8 9 10 11 12
0,0

PAD FUNCTION
1	ENABLE A
2	A1
3	YB4
4	A2
5	YB3
6	A3
7	YB2
8	A4
9	YB1
10	GND
11 B1
12	YA4
13	B2
14	YA3
15	B3
16	YA2
17	B4
18	YA1
19	ENABLE B
20	V CC
CONNECT CHIP BACK TO V OR FLOAT CC

1900µm (74.80 mils)

Logic Diagram

Truth Table

INPUTS		OUTPUTS
ENABLE A ENABLE B	A, B	YA, YB
L L H	L H X	L H Z
H = High level (steady state) L = Low level (steady state) X = Don’t care Z = High impedance

Page 2 of 6

Page 3

Rev 1.1

01/05/18

Pad Descriptions

ADDRESS INPUTS A1, A2, A3, A4, B1, B2, B3, B4

(Pads 2, 4, 6, 8, 11, 13, 15, 17) Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled.

CONTROL INPUTS

Enable A, Enable B (Pads 1, 19) Output enables (active–low). When a low level is applied to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state.

OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

(Pads 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output– enable pins, these outputs are either non-inverting outputs or high– impedance outputs.

Absolute Maximum Ratings1

PARAMETER	SYMBOL	VALUE	UNIT
DC Supply Voltage (Referenced to GND)	V CC	-0.5 to +7.0	V
DC Input Voltage (Referenced to GND)	V IN	-1.5 to V +1.5 CC	V
DC Output Voltage (Referenced to GND)	V OUT	-0.5 to V +0.5 CC	V
DC Input C urrent, per pin	I IN	±20	mA
DC Output Current, per pin	I OUT	±35	mA
DC V or GND Current, per pin CC	I CC	±75	mA
Power Dissipation in Still Air2	P D	750	mW
Storage Temperature Range	T STG	-65 to 150	°C

Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.

Recommended Operating Conditions3 (Voltages referenced to GND)

PARAMETER		SYMBOL	MIN	MAX
DC Supply Voltage		V CC	2	6
DC Input or Output Voltage		V ,V IN OUT	0	V CC
Operating Temperature Range		T A	0	+85
Input Rise and Fall Time	V = 2.0V CC	t, t r f	0	1000
	V = 4.5V CC		0	500
	V = 6.0V CC		0	400

UNITS

V V °C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Page 3 of 6

Page 4

Rev 1.1

01/05/18

DC Electrical Characteristics (Voltages Referenced to GND)

PARAMETER	SYMBOL	V CC	CONDITIONS	LIMITS			UNITS
PARAMETER	SYMBOL	V CC	CONDITIONS	25°C	85°C	FULL RANGE4	UNITS
Minimum High-Level Input Voltage	V IH	2.0V	V = V -0.1V OUT CC │I │≤ 20µA OUT	1.5	1.5	1.5	V
		3.0V		2.1	2.1	2.1
		4.5V		3.15	3.15	3.15
		6.0V		4.2	4.2	4.2
Maximum Low-Level Input Voltage	V IL	2.0V	V = 0.1V OUT │I │≤ 20µA OUT	0.5	0.5	0.5	V
		3.0V		0.9	0.9	0.9
		4.5V		1.35	1.35	1.35
		6.0V		1.8	1.8	1.8
Minimum High-Level Output Voltage	V OH	2.0V	V = V IN IH │I │≤ 20µA OUT	1.9	1.9	1.9	V
		4.5V		4.4	4.4	4.4
		6.0V		5.9	5.9	5.9
		3.0V	V = V IN IH │I │≤ 2.4mA OUT	2.48	2.34	2.34	V
		4.5V	V = V IN IH │I │≤ 6.0mA OUT	3.98	3.84	3.84
		6.0V	V = V IN IH │I │≤ 7.8mA OUT	5.48	5.34	5.34
Maximum Low-Level Output Voltage	V OL	2.0V	V = V IN IL │I │≤ 20µA OUT	0.1	0.1	0.1	V
		4.5V		0.1	0.1	0.1
		6.0V		0.1	0.1	0.1
		3.0V	V = V IN IL │I │≤ 2.4mA OUT	0.26	0.33	0.33	V
		4.5V	V = V IN IL │I │≤ 6.0mA OUT	0.26	0.33	0.33
		6.0V	V = V IN IL │I │≤ 7.8mA OUT	0.26	0.33	0.33
Maximum Input Leakage Current	I IN	6.0V	V = V or GND IN CC	±0.1	±1.0	±1.0	µA
Maximum 3-State leakage current	I OZ	6.0V	V = V or 0 OUT CC V = V or V IN IL IH	±0.5	±5.0	±5.0	µA
Maximum Quiescent Supply Leakage Current	I CC	6.0V	V = V or GND IN CC I = 0µA OUT	4	40	40	µA

0˚C ≤ TJ ≤ +85˚C

Page 4 of 6

Page 5

Rev 1.1

AC Electrical Characteristics5

01/05/18

PARA METER	SYMBOL	V CC	CONDITIONS	LIMITS			UNITS
PARA METER	SYMBOL	V CC	CONDITIONS	25°C	85°C	FULL RANGE4	UNITS
Maximum Propagation Delay, A to YA or B to YB (Figure 1, 3)	t t PLH, PHL	2.0V	C = 50pF, L t = t = 6ns r f	96	115	115	ns
		3.0V		50	60	60
		4.5V		18	23	23
		6.0V		15	20	20
Maximum Propagation Delay, Output Enable to YA or YB (Fig ure 2,4)	t t PLZ, PHZ	2.0V	C = 50pF, L t = t = 6ns r f	110	140	140	ns
		3.0V		60	70	70
		4.5V		22	28	28
		6.0V		19	24	24
Maximum Propagation Delay, Output Enable to Y A or YB (Figure 2,4)	t t PZL, PZH	2.0V	C = 50pF, L t = t = 6ns r f	110	140	140	ns
		3.0		60	70	70
		4.5V		22	28	28
		6.0V		19	24	24
Maximum Output Rise and F all Time (Figure 1, 3)	t t TLH, THL	2.0V	C = 50pF, L t = t = 6ns r f	60	75	75	ns
		3.0V		23	27	27
		4.5V		12	15	15
		6.0V		10	13	13
Maximum Input Cap acitance	C IN	-	-	10	10	10	pF
Maximum Three-State Output Capacitance (Output in High- Impedance State)	C OUT	-	-	15	15	15	pF
Power Dissipation Capacitance (Per Buffer)5	C PD	-	T = 25°C, A V = 5.0V CC	TYPICAL			pF
Power Dissipation Capacitance (Per Buffer)5	C PD	-	T = 25°C, A V = 5.0V CC	34			pF

Not production tested in die form, characterized by chip design and tested in package LAT.

2f + ICC VCC.

Used to determine the no-load dynamic power consumption: PD = CPD VCC

Page 5 of 6

Page 6

Rev 1.1

01/05/18

Switching Waveforms

Figure 1 – Propagation Delay Input A or B to Output YA or YB

Test Circuits

TEST POINT

Figure 2 – Propagation Delay Output Enable to Output YA or YB

TEST POINT

CONNECT TO VCC WHEN TESTING tPLZ,& tPZL. CONNECT TO GND WHEN TESTING tPHZ,& tPZH

\* Includes all probe and jig capacitance

Figure 3

Figure 4

Page 6 of 6

Overview

54HC244 is listed in the Logic IC category. Available datasheets include documents from Motorola, Inc, Silicon Supplies, STMicroelectronics. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

High Speed CMOS Logic

Description

High Speed CMOS Logic

Source title 54HC244 Datasheet(PDF) - Silicon Supplies

54HC244

Manufacturer specification

Read the Silicon Supplies document online.

74HC244 SS

Document overview

Technical content

Page 1

Octal 3-State Non-Inverting Buffer / Line Driver / Line Receiver in bare die form

Description

Ordering Information

Supply Formats:

Features:

Die Dimensions in µm (mils)

Mechanical Specification

Page 2

Pad Layout and Functions

Logic Diagram

Truth Table

Page 3

Pad Descriptions

ADDRESS INPUTS A1, A2, A3, A4, B1, B2, B3, B4

CONTROL INPUTS

OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

Absolute Maximum Ratings1

Recommended Operating Conditions3 (Voltages referenced to GND)

UNITS

Page 4

DC Electrical Characteristics (Voltages Referenced to GND)

Page 5

AC Electrical Characteristics5

Page 6

Switching Waveforms

Test Circuits

Silicon Supplies 54HC244 overview.

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