54ACT32_V01 SS

Document overview

  • Manufacturer or author: Provided By digicamel.com
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Technical content

www.siliconsupplies.com Die Size (Unsawn) 1200 x 1200 47 x 47 µm mils Minimum Bond Pad Size 120 x 120 4.72 x 4.72 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Advanced CMOS TTL Input – 54ACT32 Quad 2-Input OR Gate with LSTTL compatible inputs in bare die form Rev 1.1 08/11/2022  Inputs directly accept TTL  Outputs directly inter face CMOS, NMOS and TTL  Outputs Source/Sink 24 mA  Low Input Current: 1µA  Functionally compatible with bipolar 54F32  Lower power alternative to bipolar logic  Full Military Temperature Range Features:

Ordering Information

The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request The 54ACT32 quad 2-input OR gate is produced on a 1.5µm 5V CMOS process and provides four independent 2-input OR gates with standard push-pull outputs. The device gates perform the Boolean function Y = A ● B or Y = A + B. Device inputs directly accept LSTTL or CMOS. All inputs are protected against ESD and excess voltage transients. This device is designed specifically to interface both Bipolar Logic and High Speed CMOS systems.

Description

Die Dimensions in µm (mils) 1200 (47) 1200 (47) A ll data sheet.com

www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT32 Rev 1.1 08/11/2022 COORDINATES (µm) PAD FUNCTION X Y 1 1A 100 350 2 1B 150 100 3 1Y 480 100 4 2A 660 100 5 2B 990 100 6 2Y 990 350

7 GND 990 540

14 VCC 100 540

CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions 1200µm (47.24 mils) 1200µm (47.24 mils) Function Table INPUTS OUTPUT A B Y L L L L H H H L H H H H H = High level (steady state) L = Low level (steady state) Pad 15,15 = VCC Pad 7,8 = GND Y = Ᾱ 0,0 Logic Diagram 2 3 4 5 12 11 10 DIE ID A ll data sheet.com

www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT32 Rev 1.1 08/11/2022 Recommended Operating Conditions3 (Voltages Referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±50 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Output current - High IOH - -24 mA Output current - Low IOL - 24 mA VCC = 4.5V 0 10 Input Rise or Fall rate (VIN from 0.8V to 2V) VCC = 5.5V Δt/ΔV 0 8 ns/V LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 4.5V 2 2 2 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V 2 2 2 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V IOUT = -50µA 5.4 5.4 5.4 V 4.5V 3.86 3.76 3.70 Minimum High-Level Output Voltage VOH 5.5V VIN = VIL or VIH IOH = -24mA 4.86 4.76 4.70 V A ll data sheet.com

Advanced CMOS TTL Input – 54ACT32 Rev 1.1 08/11/2022 LIMITS PARAMETER LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS tPLH 5.0V 9 10 12.1 Maximum Propagation Delay, Input A or B to Output Y (Figure 1) tPHL 5.0V CL = 50pF 9 10 12.1 ns SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 4.5V 0.1 0.1 0.1 5.5V IOUT = 50µA 0.1 0.1 0.1 V 4.5V 0.36 0.44 0.50 Maximum Low-Level Output Voltage VOL VIN = VIL or VIH IOL = 24mA 5.5V 0.36 0.44 0.50 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Additional Maximum ICC / Input ΔICCT 5.5V VIN = VCC -2.1V 1 1.5 1.6 mA IOLD 5.5V VOLD = 1.65V Max - 75 50 Minimum Dynamic Output Current6 IOHD 5.5V VOHD = 3.85V Min - -75 -50 mA Maximum Quiescent Supply Leakage Current ICC 5.5V VIN = VCC or GND IOUT = 0µA 4 40 80 µA Capacitance7 7. Not production tested in die form, characterized by chip design and tested in package. PARAMETER SYMBOL VCC CONDITIONS TYPICAL UNITS Maximum Input Capacitance CIN 5.0V TJ = 25°C 4.5 pF Power Dissipation Capacitance CPD 5.0V TJ = 25°C, CL = 50pF 20 pF Page 4 of 5 www.siliconsupplies.com A ll data sheet.com

www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT32 Rev 1.1 08/11/2022 Switching Waveform Figure 1 – Propagation Delay Test Circuit DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT * Includes all probe and jig capacitance TEST POINT A ll data sheet.com