54ACT11_V01 SS

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Technical content

Advanced CMOS TTL Input – 54ACT11 Triple 3-Input AND gate with LSTTL compatible inputs in bare die form Rev 1.0 11/03/19 Description Features:  Inputs directly accept TTL / NMOS  Outputs directly inter face CMOS, NMOS and TTL  Outputs Sink/Source 24mA Die Size (Unsawn) 1130 x 1070 45 x 42 µm mils Minimum Bond Pad Size 108 x 108 4.25 x 4.25 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si  Low input current: 1µA  High noise immunity  Functionally compatible with bipolar 54LS/ALS11.  Full military temperature Range

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The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request The 54ACT11 is fabricated using an advanced CMOS process combining LSTTL speed with CMOS low power consumption while delivering high output drive. The device contains x3 independent gates each performing Boolean function Y = A • B • C or Y = A + B + C in positive logic. The device directly accepts LSTTL or NMOS inputs and suits use as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. All inputs are protected against ESD and excess voltage transients. Die Dimensions in µm (mils) 1130 (45) 1070 (42) Page 1 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

Advanced CMOS TTL Input – 54ACT11 Rev 1.0 11/03/19 Pad Layout and Functions 1130µm (44.49 mils) COORDINATES (µm) PAD FUNCTION X Y 1 1A 0.350 0.845 2 1B 0.115 0.845 3 2A 0.115 0.570 4 2B 0.115 0.390 5 2C 0.115 0.115 6 2Y 0.320 0.115 7 GND 0.510 0.115 8 3Y 0.705 0.115 9 3C 0.910 0.115 10 3B 0.910 0.390 11 3A 0.910 0.600 12 1Y 0.910 0.790 13 1C 0.740 0.845 14 VCC 0.520 0.845 CONNECT CHIP BACK TO VCC OR FLOAT 1070µm (42.13 mils) DIE ID 5 6 7 8 9 13 14 1 0,0 Logic Diagram Truth Table INPUTS OUTPUT A B C Y H L X X H X L X H X X L H L L L H = High level (steady state) L = Low level (steady state) X = Either Low or High level Y = ABC Page 2 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT11 Rev 1.0 13/05/21 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 4.5V 0 10 Input Rise or Fall rate3 (except Schmitt Inputs) tr, tf VCC = 5.5V 0 8 ns/V Output Current – High IOH - -24 mA Output Current – Low IOL - 24 mA Recommended Operating Conditions2 (Voltages Referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±50 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Storage Temperature Range TSTG -65 to 150 °C 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 3. VIN from 0.8V to 2.0V LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 4.5V 2 2 2 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V 2 2 2 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V IOUT = -50µA 5.4 5.4 5.4 V 4.5V 3.86 3.76 3.70 Minimum High-Level Output Voltage VOH 5.5V VIN = VIL or VIH IOH = -24mA 4.86 4.76 4.70 V PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT11 Rev 1.0 13/05/21 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 4.5V 0.1 0.1 0.1 5.5V IOUT = 50µA 0.1 0.1 0.1 V 4.5V 0.36 0.44 0.50 Maximum Low-Level Output Voltage VOL 5.5V VIN = VIL or VIH IOL = 24mA 0.36 0.44 0.50 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Additional Maximum ICC / Input ΔICCT 5.5V VIN = VCC -2.1V 1 1.5 1.6 mA IOLD 5.5V VOLD = 1.65V Max - 75 50 Minimum Dynamic Output Current6 IOHD 5.5V VOHD = 3.85V Min - -75 -50 mA Maximum Quiescent Supply Leakage Current ICC 5.5V VIN = VCC or GND IOUT = 0µA 4 40 80 µA LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Propagation Delay Input A,B,C to Output Y tPLH 5V ±0.5 CL = 50pF, input tr = tf =3.0ns 9.5 10.5 10.5 ns Propagation Delay Input A,B,C to Output Y tPHL 5V ±0.5 CL = 50pF, input tr = tf =3.0ns 9.5 10.5 10.5 ns Capacitance7 (VCC = 5V, Tj = 25°C) PARAMETER 7. Not production tested in die form, characterized by chip design and tested in package. SYMBOL V CC CONDITIONS LIMITS UNITS Input Capacitance CIN 5V VIN = VCC or GND 4.5 pF TYPICAL Power Dissipation Capacitance CPD 5V CL = 50pF, f = 1 MHz 20 pF PART OBSOLETE - DISCONTINUED