4571

4571 RENESAS

Document overview

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Technical content

Rev.1.02 May 25, 2007 Page 1 of 124 REJ03B0179-0102

DESCRIPTION

The 4571 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with three 8-bit timers (each timer has one or two reload registers), interrupts, and voltage drop detection circuit. The various microcomputers in the 4571 Group include variations of the built-in memory size as shown in the table below.

FEATURES

(at 6 MHz oscillation frequency, in through-mode) (It depends on oscillation frequency and operation mode)

• T i m e r s and carrier wave output auto-control function carrier wave generation circuit
• V oltage drop detection circuit
• Watchdog timer
• Power-on reset circuit
• Clock generating circuit (ceramic resonator) APPLICATION Remote control transmitter Note 1.Shipped in blank Table 1 Support Product Part number ROM size ( × 10 bits) RAM size ( × 4 bits) Package ROM type M34571G4FP (Note 1) 4096 words 128 words PRSP0024GA-A QzROM M34571G4-XXXFP 4096 words 128 words PRSP0024GA-A QzROM M34571G6FP (Note 1) 6144 words 128 words PRSP0024GA-A QzROM M34571G6-XXXFP 6144 words 128 words PRSP0024GA-A QzROM M34571GDFP (Note 1) 16384 words 128 words PRSP0024GA-A QzROM M34571GD-XXXFP 16384 words 128 words PRSP0024GA-A QzROM

4571 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0179-0102 Rev.1.02 May 25, 2007

Rev.1.02 May 25, 2007 Page 2 of 124 REJ03B0179-0102 Fig 1. Pin configuration (PRSP0024GA-A type) Outline: PRSP0024GA-A (24P2Q-A) Pin configuration (top view) 12P11 P12 11P10 P13 10P03 P20/INT0 9P02 P21/INT1 8P01 P30 7P00 P31 D0RESET K 5 XOUT 4 XIN 3 VSS 2 D4/CNTR0 1VDD C/CNTR1 M34571GxFP M34571Gx-XXXFP

Rev.1.02 May 25, 2007 Page 3 of 124 REJ03B0179-0102 Fig 2. Functional block diagram (PRSP0024GA-A type) RAM 128 words × 4 bits ROM 4096, 6144, 16384 words × 10 bits Memory I/O Port Internal peripheral functions Timer Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (8 bits) 4500 series CPU core Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) Watchdog timer (16 bits) Port P0 Port P1 Port P2 Port D System clock generating circuit XIN-XOUT(ceramic) Voltage drop detection circuit Port P3 Port C Port K Power-on reset circuit

Rev.1.02 May 25, 2007 Page 4 of 124 REJ03B0179-0102 Table 2 Performance overview Parameter Function Number of basic instructions M34571G4/G6 126 M34571GD 128 Minimum instruction execution time 0.5 µs (Oscillation frequency 6 MHz: through mode) Memory sizes ROM M34571G4 4096 words × 10 bits M34571G6 6144 words × 10 bits M34571GD 16384 words × 10 bits RAM 128 words × 4 bits I/O port D 0–D4 I/O (Input is examined by skip decision) Five independent I/O ports; The output structure of ports D0–D3 is switched by software. Port D4 is also used as CNTR0, respectively. P00−P03 I/O 4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. P10−P13 I/O 4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. P20, P21 I/O 2-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software. Ports P20 and P21 are also used as INT0 and INT1, respectively. P30, P31 I/O 2-bit I/O port ; the output structure is switched by software. C Output 1-bit output port (CMOS output only); port C is also used as CNTR1 pin. K Input 1-bit input port ; a key-on wakeup function can be switched by software. CNTR0 Timer I/O 1-bit I/O port ; CNTR0 pin is also used as port D CNTR1 Timer output 1-bit output port ; CNTR1 pin is also used as port C. INT0, INT1 Interrupt input 1-bit input port ; INT0 and INT1 are also used as ports P2 0 and P21, respectively. Timer Timer 1 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. Timer 2 8-bit timer with a reload register. Timer 3 8-bit timer with two reload regist ers and carrier wave generation function. Watchdog timer 16-bit timer, fixed di viding frequency (timer for monitor) Power-on reset circuit Built-in Voltage drop detection circuit Reset occurrence Typ. 1.65 V (Ta=25 °C) Reset release Typ. 1.75 V (Ta=25 °C) Interrupt occurrence Typ. 1.85 V (Ta=25 °C) Interrupt Source 6 sources (two for external, three for timers, voltage drop detection circuit) Nesting 1 level Subroutine nesting 8 levels Device structure CMOS sillicon gate Operating temperature range -20 to 85 °C Power source voltage 1.8 to 5.5 V (It depends on oscillation frequency and operation mode) Power dissipation (Typ. value) At active mode 0.3 mA (Ta = 25 °C, V DD = 3.0 V, f(XIN)=4 MHz, f(STCK)=f(XIN)/8) At RAM back-up 0.1 µA (Ta = 25 °C, output transistor is cut-off state)

Rev.1.02 May 25, 2007 Page 5 of 124 REJ03B0179-0102 Note 1.Pins except above have just single function. Note 2.The input of D4 can be used even when CNTR0 (output) is selected. The input/output of D4 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and D4 since the input threshold value of CNTR0 pin is different from that of port D4. Note 3.“H” output function of port C can be used even when the CNTR1 (output) is used. Note 4.The input/output of P20 can be used even when INT0 is used. Be careful when using inputs of both INT0 and P20 since the input threshold value of INT0 pin is different from that of port P20. Note 5.The input/output of P21 can be used even when INT1 is used. Be careful when using inputs of both INT1 and P21 since the input threshold value of INT1 pin is different from that of port P21. Table 3 Pin description Pin Name Input/Output Function VDD Power source − Connected to a plus power supply. VSS Power source − Connected to a 0 V power supply. RESET Reset I/O I/O An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, or the built-in power-on reset causes the system to be reset, the RESET pin outputs “L” level. XIN Main clock input Input I/O pins of the main clock gener ating circuit. Connect a ceramic resonator between pins XIN and XOUT. A feedback resistor is built-in between them.XOUT Main clock output Output D0−D4 I/O port D (Input is examined by skip decision.) I/O Each pin of port D has an independent 1-bit wide I/O function. The output structure of ports D 0–D3 can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D4 is also used as CNTR0 pin. P00−P03 I/O port P0 I/O Port P0 serves as a 4-bit I/O port. The output structure is N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. P10−P13 I/O port P1 I/O Port P1 serves as a 4-bit I/O port. The output structure is N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 0, P21 I/O port P2 I/O Port P2 serves as a 2-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P20 and P21 are also used as INT0 pin and INT1 pin, respectively. P30, P31 I/O port P3 I/O Port P3 serves as a 2-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1”. C Output port C Output Port C serves as a 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1. K Input port K Input Port K serves as a 1-bit input port. It has the key-on wakeup function which can be switched by software. When port K is used for the input of key matrix, connect a pull-up resistor to it externally. CNTR0, CNTR1 Timer I/O I/O CNTR0 pin has the function to input t he clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to output the PWM signal generated by timer 3. CNTR0 pin and CNTR1 pin are also used as Ports D 4 and C, respectively. INT0, INT1 Interrupt input Input INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports P20 and P21, respectively. Table 4 Pin description Pin Multifunction Pin Multifunction Pin Multifunction Pin Multifunction C CNTR1 P2 0 INT0 CNTR1 C INT0 P2 0 D4 CNTR0 P2 1 INT1 CNTR0 D 4 INT1 P2 1

Rev.1.02 May 25, 2007 Page 6 of 124 REJ03B0179-0102 DEFINITION OF CLOCK AND CYCLE

• Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external input
• System clock The system clock is the basic clock for controlling this product. The system clock is selected by the register MR.
• Instruction clock The instruction clock is a signa l derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle.
• Machine cycle The machine cycle is the standard cycle required to execute the instruction. Note 1.The frequency divided by 8 is selected after system is released from reset. Table 5 Port function Port Pin Input Output Output structure I/O unit Control instructions Control registers Remark Port D D 0−D3 I/O (5) N-channel open-drain/ CMOS 1 bit SD, RD SZD, CLD FR1 Programmable output structure selection function D 4/CNTR0 N-channel open-drain Port P0 P0 0 P01 P02 P03 I/O (4) N-channel open-drain 4 bits OP0A IAP0 PU0 Programmable pull-up and key-on wakeup function Port P1 P1 0 P11 P12 P13 I/O (4) N-channel open-drain 4 bits OP1A IAP1 PU1 Programmable pull-up and key-on wakeup function Port P2 P2 0/INT0 P21/INT1 I/O (2) N-channel open-drain 2 bits OP2A IAP2 PU2 K2, I1, I2, L1 Programmable pull-up and key-on wakeup function Port P3 P3 0 P31 I/O (2) N-channel open-drain/ CMOS 2 bits OP3A IAP3 FR0 Programmable output structure selection function Port C C/CNTR1 Output (1) CMOS 1 bit RCP SCP W1, W3, W5 − Port K K Input (1) - 1 bit IAK K2 Programmable key-on wakeup function Table 6 Table Selection of system clock Register MR System clock Operation modeMR3 MR2 1 1 f(STCK) = f(X IN)/8 Frequency divided by 8 mode 1 0 f(STCK) = f(X IN)/4 Frequency divided by 4 mode 0 1 f(STCK) = f(X IN)/2 Frequency divided by 2 mode 0 0 f(STCK) = f(X IN) Frequency through mode

Rev.1.02 May 25, 2007 Page 7 of 124 REJ03B0179-0102 CONNECTIONS OF UNUSED PINS Note 1.If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed when the output latch is 1, the supply voltage may be increased in the instruction execution cycle by the through current. Note 2.Do not select the CNTR0 input as the timer 1 count source. (W11 W10≠11) Note 3.Set the input of INT0 pin or INT1 pin to be disabled. (I13=0, I23=0) Note 4.Set the output of the CNTR1 pin to be invalid. (W33=0) (Note when connecting to VSS or VDD) Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Table 7 Port function Pin Connection Usage condition Output structure Pull-up transistor Key-on wakeup Value of output latch Others D0−D3 P30, P31 Open. N-channel open-drain −− 0/1 (Note 1) CMOS −− 0/1 − Connect to VSS. N-channel open-drain −− 0/1 − CMOS −− 0 − Connect to VDD. N-channel open-drain −− 1 − CMOS −− 1 − D4/CNTR0 Open. N-channel open-drain −− 0/1 (Notes 1, 2) Connect to VSS. N-channel open-drain −− 0/1 (Note 2) Connect to VDD. N-channel open-drain −− 1 (Note 2) P00−P03, P10−P13 Open. N-channel open-drain OFF Invalid 0/1 (Note 1) ON Invalid 1 − Connect to VSS. N-channel open-drain OFF Invalid 0/1 − Connect to VDD. N-channel open-drain ON/OFF Valid/Invalid 1 − P20/INT0 P21/INT1 Open. N-channel open-drain OFF Invalid 0/1 (Notes 1, 3) ON Invalid 1 (Note 3) Connect to VSS. N-channel open-drain OFF Invalid 0/1 (Note 3) Connect to VDD. N-channel open-drain ON/OFF Valid/Invalid 1 (Note 3) C/CNTR1 Open. CMOS −− 0/1 − Connect to VSS.C M O S −− 0 (Note 4) K Connect to V SS. −− Invalid −− Connect to VDD. −− Valid/Invalid −−

Rev.1.02 May 25, 2007 Page 8 of 124 REJ03B0179-0102 Fig 3. Port block diagram (1) Register Y Decoder Skip decision SZD instruction SD instruction RD instruction CLD instruction FR1i(Note 3) (Note 1) (Note 1) D0-D3 (Note 2)S R Q Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. i represents bits 0 to 3. 4. A falling edge of port input is detected. (Note 1) (Note 1) D4/CNTR0 (Note 2) Clock input for timer 1 event count W52

1 W10

S R Q W50 W23 Timer 1 underflow signal Timer 2 underflow signal Edge detection circuitKey-on wakeup input IAP0 instruction OP0A instruction (Note 1) (Note 1) P00-P03 (Note 2)D T Q K0i PU0i Ai Register A Ai (Note 3) (Note 3) (Note 4) (Note 3) Pull-up transistor

Rev.1.02 May 25, 2007 Page 9 of 124 REJ03B0179-0102 Fig 4. Port block diagram (2) Edge detection circuitKey-on wakeup input IAP1 instruction OP1A instruction (Note 1) (Note 1) P10-P13(Note 2)D T Q K1i PU1i Ai Register A Ai (Note 3) (Note 3) (Note 4) (Note 3) Pull-up transistor IAP2 instruction OP2A instruction (Note 1) (Note 1) PU20 P20/INT0(Note 2)D T Q External 0 interrupt External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input (Notes 5, 6) Register A Edge detection circuitKey-on wakeup input K20(Note 4) IAP2 instruction OP2A instruction (Note 1) (Note 1) PU21 P21/INT1(Note 2)D T Q External 1 interrupt External 1 interrupt Key-on wakeup input Register A Edge detection circuitKey-on wakeup input K21(Note4) Pull-up transistor Pull-up transistor (Notes 5, 6) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. i represents bits 0 to 3. 4. Falling edge of port input is detected. 5. As for details, refer to the external interrupt structure. 6. The threshold value of port input is different from that of external interrupt input.

Rev.1.02 May 25, 2007 Page 10 of 124 REJ03B0179-0102 Fig 5. Port block diagram (3) IAP3 instruction OP3A instruction (Note 1) (Note 1) P30, P31(Note 2)D T Q Aj Register A Aj (Note 3) FR0j(Note 3) (Note 1) (Note1) C/CNTR1(Note 2) D T Q SCP instruction RCP instruction S R R Q PWMOD Timer 1 underflow signal W51 W12 Carrier wave output auto-control signal PWMOUT (Note 1) K(Note 2) Edge detection circuitKey-on wakeup input K22(Note 4) Register A IAK instruction Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be V DD or less. 3. j represents bits 0 or 1. 4. Falling edge of port input is detected.

Rev.1.02 May 25, 2007 Page 11 of 124 REJ03B0179-0102 Fig 6. Port block diagram (4) Key-on wakeup input SNZI0 instruction (Note 1) L11 1Edge detection circuit Level detection circuit P20/INT0 I13 I12 Falling Rising L10 I11 One-sided edge detection circuit Both edges detection circuit Skip EXF0 External 0 interrupt Timer 1 count start synchronization circuit input (Note 2) (Note 3) Note 1: This symbol represents a parasitic diode on the port. 2: When IX2= 0(X=0 or 1) is 0, “L” level is detected. When IX2 is 1, “H” level is detected. 3: When IX2 is 0, falling edge is detected. When IX2 is 1, rising edge is detected. (Note 1) Key-on wakeup input SNZI1 instruction (Note 1) L13 1Edge detection circuit Level detection circuit P21/INT1 I23 I22 Falling Rising L12 I21 One-sided edge detection circuit Both edges detection circuit Skip EXF1 External 1 interrupt (Note 2) (Note 3) (Note 1)

Rev.1.02 May 25, 2007 Page 12 of 124 REJ03B0179-0102 (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison , AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 7). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 8). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register us ed for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 9). Register E is undefined after syst em is released from reset and returned from the RAM back-up. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 10). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “0”. When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”. Register D is undefined after syst em is released from reset and returned from the RAM back-up. Accordingly, set the initial value. Fig 7. AMC instruction execution example Fig 8. RAR instruction execution example Fig 9. Registers A, B and register E Fig 10. TABP p instruction execution example (CY) <Result> (M(DP)) (A) Addition ALU <Carry> <Clear> RC instruction <Set> SC instruction CY A3 A2 A1 A0 <Rotation> RAR instruction A0 CY A3 A2 A1 A3 A2 A1 A0 Register ATAB instruction E3 E2 E1 E0E7 E6 E5 E4 B3 B2 B1 B0 Register B TEAB instruction Register E A3 A2 A1 A0 Register ATBA instruction B3 B2 B1 B0 Register B TABE instruction A3 A2 A1 A0DR2 DR1 DR0 PCL Register A (4) Low-order 4bits Register D (3) High-order 2 bits Register B (4) Middle-order 4 bits ROM Immediate field value p The contents of register D The contents of register A Specifying address TABP p instruction * Flag UPTF = 1; High-order 2 bits of reference data is transferred to the low-order 2 bits of register D. “0” is stored to the high-order 1 bit of register D. Flag UPTF = 0; Data is not transferred to register D. p3 p2 p1 p0p6 p5 p4 PCH 840

Rev.1.02 May 25, 2007 Page 13 of 124 REJ03B0179-0102 (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 11 shows the stack registers (SKs) structure. Figure 12 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (S DP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interr upt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip deci sion for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig 11. Stack registers (SKs) structure Fig 12. Example of operation at subroutine call Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK 0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Program counter (PC) SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing BM instruction Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 (SP) 0 (SK0) 0001 16 (PC) SUB1 (PC) (SK 0) (SP) 7 Main program Address

000016 NOP

000116 BM SUB1

000216 NOP

SUB1: NOP

• ·· RT Subroutine Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.

Rev.1.02 May 25, 2007 Page 14 of 124 REJ03B0179-0102 (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call inst ructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PC L (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 13). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y . Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 14). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD , or SZD instruction (Figure 15).

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig 13. Program counter (PC) structure Fig 14. Data pointer (DP) structure Fig 15. SD instruction execution example a3 a2 a1 a0a6 a5 a4 PCH Specifying page Program counter p3 p2 p1 p0p6 p5 p4 PCL Specifying address Register Y (4) Data pointer (DP) X2 X1 X0 Y3Z1 Z0 X3 Y2 Y1 Y0 Register X (4) Register Z (2) Specifying RAM digit Specifying RAM file Specifying RAM file group Specifying bit position 0 0 0 1 Register Y (4) Set D3 D2 D1 D0 Port D output latch

Rev.1.02 May 25, 2007 Page 15 of 124 REJ03B0179-0102 PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 16 shows the ROM map of M34571G6. Note 1.Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 0080 16 to 00FF 16) is reserved for interrupt addresses (Figure 17). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and th e instruction at the interrupt address is executed. When usin g an interrupt service routine, write the instruction generating th e branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F 16) is the special page for subroutine calls. Subroutines writ ten in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of al l addresses can be used as data areas with the TABP p instruction. ROM Code Protect Address When selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp., reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit wr ite at ROM writing with a serial programmer. As for the QzROM product shippe d after writing, whether the ROM code protect is used or not can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering. Fig 16. ROM map of M34571GD Fig 17. Page 1 (addresses 0080 16 to 00FF16) structure Table 8 ROM size and pages Part number ROM (PROM) size (× 10 bits) Pages M34571G4 4096 words 32 (0 to 31) M34571G6 6144 words 48 (0 to 47) M34571GD 16384 words 128 (0 to 127) Interrupt address page Subroutine special page 000016 007F16 008016 00FF16 010016 017F16 018016 3FFF16 Page 127 Page 0 Page 1 Page 2 Page 3 9 876543210 00FF16 008C16 008A16 008816 008616 008416 008216 008016 9876543210 008E16 Voltage drop detection circuit interrupt address Timer 2 interrupt address Timer 1 interrupt address External 0 interrupt address External 1 interrupt address Timer 3 interrupt address

Rev.1.02 May 25, 2007 Page 16 of 124 REJ03B0179-0102 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y . Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). Table 9 shows the RAM size. Figure 18 shows the RAM map.

• Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Fig 18. RAM map Table 9 RAM size and pages Part number RAM size M34571G4 128 words × 4 bits (512 bits)M34571G6 M34571GD Register Z Register Y Register X 0 1 2 3 ... 6 7 RAM 128 words × 4 bits (512 bits) 128 words × 4 bits (512 bits) M34571G4 M34571G6 M34571GD Z=0 X=0 to 7 Y=0 to 15

Rev.1.02 May 25, 2007 Page 17 of 124 REJ03B0179-0102 The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the foll owing 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”) Table 10 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (IN TE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 11 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 12 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag except the voltage dr op detection circuit interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. The voltage drop detection circu it interrupt request flag cannot be cleared to “0” at the state that the activated condition is satisfied. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one inte rrupt request flag is set when the interrupt disable state is released, the interru pt priority level is as follows shown in Table 10. Table 10 Interrupt sources Priority level Interrupt source Interrupt addressInterrupt name Activated condition

1 Voltage drop

2 External 0

3 External 1

4 Timer 1 interrupt Timer 1

5 Timer 2 interrupt Timer 2

6 Timer 3 interrupt Timer 3

Table 11 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name Interrupt request flag Skip instruction Interrupt enable bit Voltage drop detection circuit interrupt VDF SNZVD V2 3 External 0 interrupt EXF0 SNZ0 V1 0 External 1 interrupt EXF1 SNZ1 V1 1 Timer 1 interrupt T1F SNZT1 V1 2 Timer 2 interrupt T2F SNZT2 V1 3 Timer 3 interrupt T3F SNZT3 V2 0 Table 12 Interrupt en able bit function Interrupt enable bit Occurrence of interrupt Skip instruction

1 Enabled Invalid

0 Disabled Valid

Rev.1.02 May 25, 2007 Page 18 of 124 REJ03B0179-0102 (4) Internal state during an interrupt The internal state of the microcom puter during an interrupt is as follows (Figure 20).

• Program counter (PC) An interrupt address is set in program c ounter. The address to be executed when returnin g to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0” (the voltage drop detection circuit interrupt request flag is excluded)
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt o ccurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing th e EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interr upts are enabled after returning the main routine. (Refer to Figure 19) Fig 19. Program example of interrupt processing Fig 20. Internal state when interrupt occurs Fig 21. Interrupt system diagram Main routine Interrupt occurs Interrupt is enabled Interrupt service routine EI RTI : Interrupt enabled state : Interrupt disabled state Each interrupt address
• Program counter (PC) The address of main routine to be executed when returning
• Stack register (SK) 0 (Interrupt disabled)
• Interrupt enable flag (INTE) 0 (excluding voltage drop detection interrupt request flag)
• Interrupt request flag (only the flag for the current interrupt source) Stored in the interrupt stack register (SDP) automatically
• Data pointer, carry flag, registers A and B, skip flag EXF0 Request flag (state retained) V10 Enable bit Enable flag Address 0 in page 1INT0 pin interrupt waveform input Timer 2 underflow T1F V12 Address 4 in page 1 Timer 1 underflow T2F V13 Address 6 in page 1 T3F V20 Address 8 in page 1 Activated condition INTE Timer 3 underflow EXF1 V11 Address 2 in page 1 INT1 pin interrupt waveform input VDF V23 Address E in page 1 when supply voltage goes lower than specified value

Rev.1.02 May 25, 2007 Page 19 of 124 REJ03B0179-0102 (6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Se t the contents of this register through register A with the TV1A instruction. The TA V1 instruction can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2 The voltage drop detection circuit interrupt enable bit and timer 3 interrupt enable bit are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TA V2 instruction can be used to transfer the contents of register V2 to register A. Note 1.“R” represents read enabled, and “W” represents write enabled. Table 13 Interrupt control registers Interrupt control register V1 at reset : 0000 2 at RAM back-up : 00002 R/W TAV1/TV1A V13 Timer 2 interrupt enable bit 0 Interrupt disabled (SNZT2 instruction is valid)

1 Interrupt enabled (SNZT2 instruction is invalid)

V12 Timer 1 interrupt enable bit 0 Interrupt disabled (SNZT1 instruction is valid)

1 Interrupt enabled (SNZT1 instruction is invalid)

V11 External 1 interrupt enable bit 0 Interrupt disabled (SNZ1 instruction is valid)

1 Interrupt enabled (SNZ1 instruction is invalid)

V10 External 0 interrupt enable bit 0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid)

Interrupt control register V2 at reset : 0000 2 at RAM back-up : 00002 R/W TAV2/TV2A V23 Voltage drop detector interrupt enable bit 0 Interrupt disabled (SNZVD instruction is valid)

1 Interrupt enabled (SNZVD instruction is invalid)

V22 Not used 0 This bit has no function, but read/write is enabled.1 V21 Not used 0 This bit has no function, but read/write is enabled.1 V20 Timer 3 interrupt enable bit 0 Interrupt disabled (SNZT3 instruction is valid)

1 Interrupt enabled (SNZT3 instruction is invalid)

Rev.1.02 May 25, 2007 Page 20 of 124 REJ03B0179-0102 (7) Interrupt sequence Interrupts only occur when th e respective INTE flag, interrupt enable bits (V1 0−V13, V20, V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 22). Fig 22. Interrupt sequence T3T2T1 1 machine cycle System clock (STCK) Interrupt enable flag (INTE) INT0 INT1 T1F T2F T3F The program starts from the interrupt address. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) EXF0 EXF1 External 0, External 1 interruptTimer 1 Timer 2 Timer 3 interrupt VDF Voltage drop detection circuit interrupt When an interrupt request flag is set after its interrupt is enabled EI instruction execution cycle Interrupt enabled state Interrupt disabled state Retaining level of system clock for 4 periods or more is necessary. Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. T3T2T1 T3T2T1 T3T2T1 T2T1

Rev.1.02 May 25, 2007 Page 21 of 124 REJ03B0179-0102 The 4571 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Fig 23. External interrupt circuit structure Table 14 External interrupt activated conditions Name Input pin Activated condition Valid waveform selection bit External 0 interrupt P2 0/INT0 When the next waveform is input to P2 0/INT0 pin

• Falling waveform (“H” → “L”)
• Both rising and falling waveforms I11 I12 External 1 interrupt P2 1/INT1 When the next waveform is input to P2 1/INT1 pin
• Falling waveform (“H” → “L”)
• Both rising and falling waveforms I21 I22 Key-on wakeup input SNZI0 instruction (Note 1) L11 1Edge detection circuit Level detection circuit P20/INT0 I13 I12 Falling Rising L10 I11 One-sided edge detection circuit Both edges detection circuit Skip EXF0 External 0 interrupt Timer 1 count start synchronization circuit input (Note 2) (Note 3) Note 1: This symbol represents a parasitic diode on the port. 2: When IX2= 0(X=0 or 1) is 0, “L” level is detected. When IX2 is 1, “H” level is detected. 3: When IX2 is 0, falling edge is detected. When IX2 is 1, rising edge is detected. (Note 1) Key-on wakeup input SNZI1 instruction (Note 1) L13 1Edge detection circuit Level detection circuit P21/INT1 I23 I22 Falling Rising L12 I21 One-sided edge detection circuit Both edges detection circuit Skip EXF1 External 1 interrupt (Note 2) (Note 3) (Note 1)

Rev.1.02 May 25, 2007 Page 22 of 124 REJ03B0179-0102 (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P20/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 22). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt contro l register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P2 0/INT0 pin. The valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. (1) Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I1. (3) Clear the EXF0 flag to “0” with the SNZ0 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. (5) Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the P2 0/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P21/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 22). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt contro l register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.
• External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P2 1/INT1 pin. The valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. (1) Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I2. (3) Clear the EXF1 flag to “0” with the SNZ1 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. (5) Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid waveform is input to the P2 1/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

Rev.1.02 May 25, 2007 Page 23 of 124 REJ03B0179-0102 (3) External interrupt control registers (1) Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. (2) Interrupt cont rol register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set. Table 15 External interrupt control register Interrupt control register I1 at reset : 0000 2 at RAM back-up : state retained R/W TAI1/TI1A I13 INT0 pin input control bit (Note 2) 0 INT0 pin input disabled

1 INT0 pin input enabled

Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)

0 Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level

1 Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

instruction)/“H” level I11 INT0 pin edge detection circuit control bit 0 One-sided edge detected

1 Both edges detected

timer 1 control enable bit

0 Timer 1 disabled

1 Timer 1 enabled

Interrupt control register I2 at reset : 0000 2 at RAM back-up : state retained R/W TAI2/TI2A I23 INT1 pin input control bit (Note 3) 0 INT0 pin input disabled Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)

0 Falling waveform (“L” level of INT0 pin is recognized with the SNZI1

instruction)/“L” level

1 Rising waveform (“H” level of INT0 pin is recognized with the SNZI1

instruction)/“H” level I21 INT1 pin edge detection circuit control bit 0 One-sided edge detected I20 Not used 0 This bit has no function, but read/write is enabled.1

Rev.1.02 May 25, 2007 Page 24 of 124 REJ03B0179-0102 (4) Notes on interrupts (1) Bit 3 of register I1 When the input of the P2 0/INT0 pin is controlled with the bit 3 of register I1 in so ftware, be careful about the following notes.

• Depending on the input state of the P20/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 24) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 24). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 24). Fig 24. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the INT0 pin input is disabled (register I1 3 = “0”), set the key-on wakeup of INT0 pin to be invalid (register L1 0 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 25). Fig 25. External 0 interrupt program example-2 (3) Bit 2 of register I1 When the interrupt valid waveform of the P2 0/INT0 pin is changed with the bit 2 of regist er I1 in software, be careful about the following notes.
• Depending on the input state of the P20/INT0 pin, the external 1 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 26) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 26). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 26). Fig 26. External 0 interrupt program example-3
• •• LA 4 ; ( ×××02) LA 8 ; (1 ×××2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here. LA 0 ; ( ×××02) DI EPOF POF ; RAM back-up
• •• ×: these bits are not used here. LA 4 ; ( ×××02) LA 12 ; (1 ×××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here.

Rev.1.02 May 25, 2007 Page 25 of 124 REJ03B0179-0102 (4) Bit 3 of register I2 When the input of the P2 1/INT1 pin is controlled with the bit 3 of register I2 in so ftware, be careful about the following notes.

• Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 27) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 27). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instru ction (refer to (3) in Figure 27). Fig 27. External 1 interrupt program example-1 (5) Bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the INT1 pin input is disabled (register I2 3 = “0”), set the key-on wakeup of INT1 pin to be invalid (register L2 0 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 28) Fig 28. External 1 interrupt program example-2 (6) Bit 2 of register I2 When the interrupt valid waveform of the P2 1/INT1 pin is changed with the bit 2 of regist er I2 in software, be careful about the following notes.
• Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 29) and then, change the bit 2 of register I2 is changed. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 29). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instru ction (refer to (3) in Figure 29). Fig 29. External 1 interrupt program example-3
• •• LA 4 ; ( ××0×2) LA 8 ; (1 ×××2) TI1A ; Control of INT1 pin input is changed SNZ0 ; The SNZ1 instruction is executed (EXF1 flag cleared)
• •• ×: these bits are not used here. LA 0 ; ( ×0××2) DI EPOF POF ; RAM back-up ×: these bits are not used here.
• •• LA 4 ; ( ××0×2) LA 12 ; (1 ×××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ1 instruction is executed (EXF1 flag cleared)
• •• ×: these bits are not used here.

Rev.1.02 May 25, 2007 Page 26 of 124 REJ03B0179-0102 The 4571 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be se t. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig 30. Auto-reload function n+1 count Reload n+1 count An interrupt occurs or a skip instruction is executed. 1st underflow Reload 2nd underflow FF16 Time n 0016 “1” “0” n : Counter initial value The contents of counter Timer interrupt request flag Count starts

Rev.1.02 May 25, 2007 Page 27 of 124 REJ03B0179-0102 The 4571 Group timer consists of the following circuits.

• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Watchdog timer: 16-bit fixed frequency timer (Timers 1, 2 and 3 have the interrupt function, respectively) Prescaler, timer 1, timer 2 and timer 3 can be controlled with the timer control registers PA, W1, W2, W3 and W5. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Table 16 Function related timers Circuit Structure Count source Frequency dividing ratio Use of output signal Control register Prescaler 8-bit programmable binary down counter
• Instruction clock (INSTCK)
• Instruction clock divided by 4 (INSTCK/4) 1 to 256 • Timer 1 count source
• Timer 2 count source
• Timer 3 count source PA Timer 1 8-bit programmable binary down counter (link to INT0 input) (carrier wave output auto- control function)
• PWM signal (PWMOUT)
• Prescaler output (ORCLK)
• CNTR0 input (CNTR0IN)
• System clock (STCK) 1 to 256 • Timer 2 count source
• CNTR0 output
• Carrier wave output auto- control
• Timer 1 interrupt Timer 2 8-bit programmable binary down counter
• PWM signal (PWMOUT)
• Timer 1 underflow (T1UDF)
• Prescaler output (ORCLK)
• System clock (STCK) 1 to 256 • CNTR0 output
• Timer 2 interrupt Timer 3 8-bit programmable binary down counter (with carrier wave generation function) IN input
• Prescaler output divided by 2 (ORCLK/2) 1 to 256 • Timer 1 count source
• Timer 2 count source
• CNTR1 output
• Timer 3 interrupt Watchdog timer 16-bit fixed dividing frequency
• Instruction clock (INSTCK) 65536 • System reset (counting twice)
• Decision of flag WDF1

Rev.1.02 May 25, 2007 Page 28 of 124 REJ03B0179-0102 Fig 31. Timers structure (1) Data is set automatically from each reload register when timer underflows (auto-reload function). XIN ORCLK W50 D4/CNTR0 Port D4 output W52 W23 T1UDF T2UDF P20/INT0 I12 I11 One-sided edge detection circuit INTSNCI13 W21,W 20 PWMOUT ORCLK T1UDF W22 Timer 2 (8) Reload register R2 (8) Register B (TAB2) (T2AB) Register A (T2AB)(T2AB) (TAB2) T2F Timer 2 interrupt T2UDF STCK W11,W 10 PWMOUT ORCLK CNTR0IN W12 W53 (Note 1) S R QINT0SNC I10 W13 T1UDF Timer 1 (8) Reload register R1 (8) Register B (TAB1) (T1AB) Register A (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt T1UDF STCK PA1 MR3,MR2Division circuit Divided by 8 Divided by 4 Divided by 2 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) Prescaler (8)PA0 Reload register RPS (8) Register B (TABPS) (TPSAB) Register A (TPSAB)(TPSAB) (TABPS) PWMOUT: PWM signal (output from timer 3) CNTR0IN (TR1AB) Both edges detection circuit Note 1: Timer 1 count start synchronous circuit is synchronized with the valid edge of INT pin selected by bits 1 (I11) and 2 (I12) of register I1.

Rev.1.02 May 25, 2007 Page 29 of 124 REJ03B0179-0102 Fig 32. Timers structure (2) Watchdog reset signal reset signal (Note 3) D T Q R DWDT instruction WRST instruction Reset signal (Note 4) (Note 2) WRST instruction Watchdog timer (16) S R Q WDF1 S R Q WEF C/CNTR1 Port C output PWMOUT PWMOD W12 W51 Q R D T T1UDF W30 XIN W31 Timer 3 (8) Reload Register R3L (8) Register B (TAB3) (T3AB) Register A (T3AB)(T3AB) (TAB3) (T3R3L) Reload control circuit (Note 1)Reload Register R3H (8) (T3HAB) Register B Register A W33 Timer 3 interrupt 1/2ORCLK TQ R W32 “H” interval expansion T3F PWMOD T2UDF: Timer 2 underflow signal ORCLK: Prescaler output Note 1: When the CNTR1 output function is valid (W33=“1”), the value is auto-reloaded alternately from reload register R3L and R3H every timer 3 underflow. When the CNTR1 function is invalid (W33=“0”), the value is auto-reloaded from reload register R3L only. 2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”. 3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 4: The WEF flag is set to “1” at system reset or RAM back-up mode. Data is set automatically from each reload register when timer underflows (auto-reload function).

Rev.1.02 May 25, 2007 Page 30 of 124 REJ03B0179-0102 Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is selected (W53 =“1”). Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”). Table 17 Timer control registers Timer control register PA at reset : 00 2 at RAM back-up : 002 W TPAA PA1 Prescaler count source selection bit 0 Instruction clock (INSTCK)

1 Instruction clock divided by 4 (INSTCK/4)

PA0 Prescaler control bit 0 Stop (state initialized) 1O p e r a t i n g Timer control register W1 at reset : 0000 2 at RAM back-up : state retained R/W TAW1/TW1A W13 Timer 1 count auto-stop circuit selection bit (Note 2)

0 Timer 1 count auto-stop circuit not selected

1 Timer 1 count auto-stop circuit selected

W12 Timer 1 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 1 count source selection bits W11 W10 Count source W11 0 0 PWM signal (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 System clock (STCK)W1 1 1 CNTR0 input Timer control register W2 at reset : 0000 2 at RAM back-up : state retained R/W TAW2/TW2A W23 CNTR0 pin function selection bit 0 Timer 1 underflow signal divided by 2 output

1 Timer 2 underflow signal divided by 2 output

W22 Timer 2 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 2 count source selection bits W21 W20 Count source W21 0 0 PWM signal (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 System clock (STCK)W2 1 1 Timer 1 underflow signal (T1UDF) Timer control register W3 at reset : 0000 2 at RAM back-up : 00002 R/W TAW3/TW3A W33 CNTR1 pin output control bit 0 CNTR1 pin output invalid

1 CNTR1 pin output valid

“H” interval expansion function control bit

0 PWM signal “H” interval expansion function invalid

1 PWM signal “H” interval expansion function valid

W31 Timer 3 control bit 0 Stop (state retained) 1O p e r a t i n g W30 Timer 3 count source selection bit 0X IN input

1 Prescaler output (ORCLK)/2

Timer control register W5 at reset : 0000 2 at RAM back-up : state retained R/W TAW5/TW5A W53 Timer 1 count start synchronous circuit selection bit (Note 3)

0 Count start synchronous circuit not selected

1 Count start synchronous circuit selected

W52 CNTR0 pin input count edge selection bit 0 Falling edge

1 Rising edge

CNTR 1 pin output auto-control circuit selection bit

0 Output auto-control circuit not selected

1 Output auto-control circuit selected

W50 D4/CNTR0 pin function selection bit 0D 4 (I/O) / CNTR0 (input) 1D 4 (input) /CNTR0 (I/O)

Rev.1.02 May 25, 2007 Page 31 of 124 REJ03B0179-0102 (1) Timer control registers

• Timer control register PA Register PA controls the count operation and count source of prescaler. Set the contents of this register through register A with the TPAA instruction.
• Timer control register W1 Register W1 controls the coun t operation and count source of timer 1, and timer 1 count auto-stop circuit. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
• Timer control register W2 Register W2 controls the coun t operation and count source of timer 2, and CNTR0 pin out put signal function. Set the contents of this register th rough register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W3 Register W3 controls timer 3 count source, timer 3 count operation, CNTR1 pin output and PWM signal “H” interval expansion function. Set the conten ts of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the cont ents of register W3 to register
• Timer control register W5 Register W5 controls the input count edge of CNTR0 pin, the timer 1 count start synchrono us circuit, CNTR1 pin output auto-control circuit and the D 4/CNTR1 pin function. Set the contents of this register th rough register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler can be selected the instruction clock (INSTCK) or the instruction clock (INSTCK)/4. Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload regi ster RPS, and count continues (auto-reload function). The output signal (ORCLK) of pres caler can be used for timer 1 and 2 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with a timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register R1 with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instru ction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; (1) set data in timer 1 (2) set count source by bits 0 and 1 of register W1, and (3) set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). After timer 1 control by INT0 pin is enabled by setting the bit 0 of register I1 to “1”, INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 3 of register W5 to “1”. Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” The timer 1 underflow signal divided by 2 can be output from the CNTR0 pin by setting the bit 0 of register W5 to “1” and bit 3 of register W2 to “0”. (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary dow n counter with timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register R2 with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; (1) set data in timer 2 (2) set count source by bits 0 and 1 of register W2, and (3) set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). The timer 2 underflow signal divided by 2 can be output from the CNTR0 pin by setting the bit 0 of register W5 to “1” and bit 3 of register W2 to “1”.

Rev.1.02 May 25, 2007 Page 32 of 124 REJ03B0179-0102 (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary dow n counter with two timer 3 reload registers (R3L, R3H). Data can be set simultaneously in timer 3 and the reload register R3L with the T3AB instruction. Data can be set in the reload register R3H with the T3HAB instruction. The contents of reload regi ster R3L set with the T3AB instruction can be set to timer 3 again with the T3R3L instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the T3 HAB instruction to set data to reload register R3H while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; (1) set data in timer 3 (2) set count source by bit 0 of register W3, and (3) set the bit 1 of register W3 to “1.” When a value set in reload register R3L is n and a value set in reload register R3H is m, timer 3 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). <Bit 3 of register W3 = “0” (CNTR1 pin output invalid)> Once count is started, when time r 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3 L, and count continues (auto- reload function). <Bit 3 of register W3 = “1” (CNTR1 pin output valid)> Timer 3 generates the PWM signal of the “L” interval set as reload register R3L, and the “H” interval set as reload register R3H. The PWM (PWMOD) signal generated by timer 3 is output from CNTR1 pin. When bit 2 of register W3 is set to “1” at this time, timer 3 extends the interval set to reload register R3H for a half period of count source. When a value set in reload register R3H is n, timer 3 divides the count source signal by m + 1.5 (m = 1 to 255). When this function is used, set “1” or more to reload register R3H. When bit 1 of register W5 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/ invalid each timer 1 underflow. However, when timer 3 is stopped, this function is canceled. Even when bit 1 of a register W3 is cleared to “0” in the “H” interval of PWM signal, timer 3 does not stop until it next timer 3 underflow. When bit 1 of register W3 is cleared to “0” in order to stop timer 3 while the PWM output is used, avoid a timing when timer 3 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. (6) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT0 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function can be selected after timer 1 control by INT0 pin is enabled by setting the bit 0 of register I1 to “1” and its functi on is selected by setting the bit 3 of register W5 to “1”. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to timer by inputting valid waveform to INT0 pin. The valid waveform of INT0 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start s ynchronous circuit is cleared by clearing the bit I1 0 to “0” or system reset. However, when the count auto-st op circuit is selected, the count start synchronous circuit is clea red (auto-stop) at the timer 1 underflow. (7) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop circuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. (8) Timer input/output pin (D 4/CNTR0) CNTR0 pin is used to input the timer 1 count source and output the timer 1 or timer 2 underflow signal/2. The D4/CNTR0 pin function can be se lected by bit 0 of register W5. The output signal can be selected by bit 0 of register W2. When the CNTR0 input is sel ected for timer 1 count source, timer 1 counts the fa lling or rising waveform of CNTR0 input. The count edge is selected by bit 2 of register W5. (9) PWM signal output f unction (C/CNT R1, timer 1, timer 2) The C/CNTR1 pin is also used to output the PWM signal generated by timer 3. When the bit 3 of register W3 is set to “1”, the PWM signal can be output from the C/CNTR1 pin. In this time, set the output latch of port C to “1.” (10)Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cl eared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction.

Rev.1.02 May 25, 2007 Page 33 of 124 REJ03B0179-0102 (11) Precautions

• Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. Stop prescaler counting to change its count source.
• Timer count source Stop timer 1, 2 or 3 counting to change its count source.
• Reading the count value Stop timer 1, 2 or 3 counting and then execute the TAB1, TAB2 or TAB3 instruction to read its data.
• Writing to the timer Stop timer 1, 2 or 3 counting and then execute the T1AB, T2AB, T3AB or T3R3L instruction to write data to timer.
• Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R3H while the timer 3 is operating, execute th e T3HAB instruction except a timing of the timer 3 underflow.
• PWM signal If the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When “H” interval expansion f unction of the PWM signal is used, set “1” or more to reload register R3H. Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin.
• Prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 33 after prescaler and timer operations start (1) in Figure 33. Time to first underflow (3) in Figu re 33 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 33 by the timing to start the timer and count source operations after count starts. When selecting CNTR0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of CNTR0 input selected by software. Fig 33. Timer count start timing and count time when operation starts Count source (3) (4) (1) Timer start (2) Count source (When falling edge of CNTR0 input is selected) Timer 1 value Timer 1 underflow signal 32 1 0 3 2 1 0 3 2

Rev.1.02 May 25, 2007 Page 34 of 124 REJ03B0179-0102 Fig 34. Timer 3 operation example Timer 3 count source Timer 3 start Timer 3 count value (Reload register) Timer 3 underflow signal PWM signal 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 00160316 (R3L) (R3L) (R3L) (R3L) (R3L) PWM1 signal “L” fixed - CNTR1 pin output invalid (W33=0) Timer 3 count source Timer 3 start Timer 3 count value (Reload register) Timer 3 underflow signal PWM signal 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 01160316 (R3L) (R3H) (R3L) (R3H) (R3L) (R3H) PWM period 7 clock PWM period 7 clock * : “0316” is set to reload register R3L and “0216” is set to reload register R3H. 4 clock 3 clock 4 clock 3 clock 4 clock Timer 3 count source Timer 3 start Timer 3 count value (Reload register) Timer 3 underflow signal PWM signal 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 02160316 (R3L) (R3H) (R3L) (R3H) (R3L) (R3H) PWM period 7.5 clock PWM period 7.5 clock 4 clock 3.5 clock 4 clock 3.5 clock 4 clock Note: When the PWM signal “H” interval expansion function is valid, set “1” or more to reload register R3H. - CNTR1 pin output valid (W33=1), PWM signal “H” interval expansion function invalid (W32=0) - CNTR1 pin output valid (W33=1), PWM signal “H” interval expansion function valid (W32=1) (Note)

Rev.1.02 May 25, 2007 Page 35 of 124 REJ03B0179-0102 Fig 35. CNTR1 output auto-control function by timer 1 Timer 1 start CNTR1 output start Timer 1 underflow signal PWM signal

• CNTR1 output auto-control circuit operation example 1 (W33 = “1”, W51 = “1”) CNTR1 output * When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows.
• CNTR1 output auto-control circuit operation example 2 (W33 = “1”, W51 = “1”) Timer 1 start CNTR1 output start Timer 1 underflow signal PWM signal Register W51 Timer 1 stop CNTR1 output stop CNTR1 output (1) When the CNTR1 output auto-control function is not selected while the CNTR1 output is invalid, CNTR1 output invalid state is retained. (2) When the CNTR1 output auto-control function is not selected while the CNTR1 output is valid, CNTR1 output valid state is retained. (3) When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid. (1) (2) (3)

Rev.1.02 May 25, 2007 Page 36 of 124 REJ03B0179-0102 Fig 36. Timer count start/stop timing (R3H) Timer 3 underflow signal Machine cycle Timer 3 count start timing (R3L = “0216”, R3H = “0216”, W33 = “1”) Register W31 Mi Mi + 1 Mi + 2 Mi + 3 0216001601160216001601160216 (R3L)(R3L) Timer 3 count start timing PWM signal Timer 3 count value (reload register) Timer 3 count source (XIN input) (R3H) Mi Mi + 1 Mi + 2 Mi + 3 001601160216001601160216 0216 Timer 3 count stop timing (R3L)(R3H) (Note 1) TW3A instruction execution (W31←1) TW3A instruction execution (W31←0) Timer 3 underflow signal Machine cycle Register W31 PWM signal Timer 3 count value (reload register) Timer 3 count source (XIN input) Timer 3 count stop timing (R3L = “0216”, R3H = “0216”, W33 = “1”) Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR1 pin output is valid (W33=“1”), a hazard may occur in the PWM signal waveform. 2: When timer count is stopped during “H” interval of the PWM signal, timer is stopped after the end of the “H” output interval.

Rev.1.02 May 25, 2007 Page 37 of 124 REJ03B0179-0102 Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the inst ruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction a nd the WRST instruction are executed continuously, the WEF fl ag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is initialized to “1” at system reset or RAM back- up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. Fig 37. Watchdog timer function (1) Reset released 65534 count (Note) (4) (2)(2) (3) WRST instruction executed (skip executed) (5) System reset FFFF16 000016 Value of 16-bit timer (WDT) WDF1 flag WDF2 flag RESET pin output (1) After system is released from reset (= after program is started), timer WDT starts count down. (2) When timer WDT underflow occurs, WDF1 flag is set to “1”. (3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0”, the next instruction is skipped. (4) When timer WDT underflow occurs while WDF1 flag is “1”, WDF2 flag is set to “1” and the watchdog reset signal is output. (5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock.

Rev.1.02 May 25, 2007 Page 38 of 124 REJ03B0179-0102 When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 38). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with th e WRST instruction just before the microcomputer enters the RA M back-up state. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction (refer to Figure 39). Fig 38. Program example to start/stop watchdog timer Fig 39. Program example when using the watchdog timer WRST ; WDF1 flag cleared

• •• DI DWDT ; Watchdog timer fu nction enabled/disabled WRST ; WEF and WDF1 flags cleared
• •• WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ; RAM back-up mode Oscillation stop

Rev.1.02 May 25, 2007 Page 39 of 124 REJ03B0179-0102 System reset is performed by the followings:

• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. (1) RESET pin input System reset is performed ce rtainly by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Fig 40. Structure of reset pin and its peripherals Fig 41. RESET pin input waveform and reset release timing Power-on reset circuit Watchdog reset signal WEF SRST instruction Internal reset signal (Note 1) RESET pin (Note 2) Pull-up transistor Voltage drop detection circuit (Note 1) Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 0.3VDD 0.85VDD (Note 1) Program starts (address 0 in page 0) Reset input 1 machine cycle or more RESET f(RING) Notes 1: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: It depends on the internal state at reset. XIN input is counted 5400 to 5424 times (Note 2).

Rev.1.02 May 25, 2007 Page 40 of 124 REJ03B0179-0102 (2) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, “L” level is output to RESET pin and system reset is performed. Fig 42. Power-on reset operation Note 1.Output latch is set to “1.” Note 2.The output structure is N-channel open-drain. Note 3.Pull-up transistor is turned OFF. 100µso r l e s s VDD (Note 1) Power-on reset circuit output Internal reset signal Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Reset released Reset state Power-on Table 18 Port state at reset Name Function State D0−D3 D0−D3 High-impedance (Notes 1, 2) D4/CNTR0 D 4 High-impedance (Note 1) P00−P03 P00−P03 High-impedance (Notes 1, 3) P10−P13 P10−P13 High-impedance (Notes 1, 3) P20/INT0, P21/INT1 P2 0, P21 High-impedance (Notes 1, 3) P30, P31 P30, P31 High-impedance (Notes 1, 2) C/CNTR1 C/CNTR1 (V SS) K K High-impedance

Rev.1.02 May 25, 2007 Page 41 of 124 REJ03B0179-0102 (4) Internal state at reset Figure 43 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figu re 43 are undefined, so set the initial value to them. Fig 43. Internal state at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0• Program counter (PC) Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE)
• Power down flag (P)
• External 0 interrupt request flag (EXF0)
• External 1 interrupt request flag (EXF1)
• Interrupt control register V1
• Interrupt control register V2
• Interrupt control register I1
• Interrupt control register I2
• Timer 1 interrupt request flag (T1F)
• Timer 2 interrupt request flag (T2F)
• Timer 3 interrupt request flag (T3F)
• Watchdog timer flags (WDF1, WDF2)
• Watchdog timer enable flag (WEF)
• Timer control register PA
• Timer control register W1
• Timer control register W2
• Timer control register W3
• Timer control register W5
• Clock control register MR 0 (Interrupt disabled) 0 (Interrupt disabled)0 0 0 0 (Interrupt disabled)0 0 0 00 0 0 0 (Prescaler stopped) 0 (Timer 1 stopped)0 0 0 0 (Timer 2 stopped)0 0 0 00 0 0 00 0 0 11 1 1
• Key-on wakeup control register K0
• Key-on wakeup control register K1
• Key-on wakeup control register K2
• Key-on wakeup control register L1
• Pull-up control register PU0
• Pull-up control register PU1
• Pull-up control register PU2
• Port output structure control register FR0
• Port output structure control register FR1
• Carry flag (CY)
• Register A
• Register B
• Register D
• Register E
• Register X
• Register Y
• Register Z
• Stack pointer (SP) 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 ×× × ×× × × 11 1 “X” represents undefined. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 00 0 ×× × × 00 0 0 (Timer 3 stopped)

Rev.1.02 May 25, 2007 Page 42 of 124 REJ03B0179-0102 VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detectio n circuit is used to set the voltage drop detection circuit inte rrupt request flag (VDF) or to perform system reset. The voltage drop detection circuit stops at RAM back-up mode. Fig 44. Voltage drop detection reset circuit WEF VRST-/VRST+ VINT Interrupt occurrence Reset occurrence VDF Voltage drop detection circuit interrupt S R Q Q Oscillation stop signalKey-on wakeup signal EPOF instruction POF instruction Power-on reset circuit Watchdog reset signal SRST instruction Internal reset signal (Note 1) RESET pin (Note 2) Pull-up transistor Voltage drop detection circuit (Note 1) Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less.

Rev.1.02 May 25, 2007 Page 43 of 124 REJ03B0179-0102 (1) Voltage drop detection circuit interrupt request flag (VDF) V oltage drop detection circuit interrupt request flag (VDF) is set to “1” when the supply voltage goes the defined value (V INT) or less. Moreover, voltage drop dete ction circuit interrupt request flag (VDF) is cleared to “0” wh en the supply voltage goes the defined value (V INT) or more. The state of the interrupt request flag can be examined with the skip instruction (SNZVD). Use the interrupt control register V2 to select an interrupt or a skip instruction. Unlike other interrupt request flags, even when the interrupt occurs or the skip in struction is executed, the voltage drop detection circuit interrupt request flag is not cleared to “0”. (2) Voltage drop detection circuit reset System reset is performed when the supply voltage goes the defined value (V RST-) or less (“L” level is not output to RESET pin.). However, unlike the normal system reset, the oscillation circuit is stopped. When the supply voltage goes the defined value (VRST-) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released. Fig 45. Voltage drop detection circuit operation waveform Fig 46. V DD and VRST- (3) Note on voltage drop detection circuit The voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a mic rocomputer falls below to the minimum value of recommended operating conditions and rises again, depending on the capacity value of the bypass capacitor added to the power supply pi n, the following case may cause program failure (Figure 46); supply voltage does not fall below to VRST-, and its voltage rises again with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that. VDD Voltage drop detection circuit interrupt request flag (VDF) VRST+(reset release voltage) VRST-(reset occurrence voltage) Voltage drop detection circuit reset signal Notes 1: Microcomputer starts operation after input clock is counted 5400 to 5424 times. 2: “L” level is not output from RESET pin. The oscillation circuit is stopped. 3: After microcomputer starts operation, the detection of the interrupt occurrence voltage is performed. (Note 1)(Note 2) (Note 3) VINT (interrupt occurrence voltage) VDD VRST+ VRST- VDD VRST+ VRST- Recommended operating condition min.value Normal operation Reset No reset Program failure may occur. Recommended operating condition min.value

Rev.1.02 May 25, 2007 Page 44 of 124 REJ03B0179-0102 The 4571 Group has the RAM back-up mode. When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 19 shows the function and states retained at RAM back-up. Figure 47 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal rese t state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF instruction and POF instruction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when;

• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed, or
• reset by the voltage drop detection circuit is performed. In this case, the P flag is “0.” Note 1.“O” represents that the function can be retained, and “ ×” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. Note 2.The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. Note 3.The state of the timer is undefined. Note 4.Initialize the watchdog timer flag WDF1 with the WRST instruction, and then set the system to be in the RAM back-up mode. Note 5.The voltage drop detection circuit is invalid. Note 6.C/CNTR pin outputs “L” level. Other ports retain their output levels. Table 19 Functions and states retained at RAM back-up Function RAM back-up Program counter (PC), stack pointer (SP) (Table 2), carry flag (CY), registers A, B × Contents of RAM O Interrupt control registers V1, V2 × Interrupt control registers I1, I2 O Clock control register MR Timer 1, Timer 2, Timer 3 function (Note 3) Watchdog timer function × (Note 4) Timer control registers PA, W3 × Timer control registers W1, W2, W5 O Voltage drop detection circuit (Note 5) Port level (Note 6) Key-on wakeup control registers K0 to K2, L1 O Pull-up control registers PU0 to PU2 O Port output structure control registers FR0, FR1 O External interrupt request flags (EXF0, EXF1) Timer interrupt request flags (T1F, T2F, T3F) (Note 3) Voltage drop detection circuit interrupt request flag (VDF) Interrupt enable flag (INTE) × Watchdog timer flags (WDF1, WDF2) × (Note 4) Watchdog timer enable flag (WEF) × (Note 4)

Rev.1.02 May 25, 2007 Page 45 of 124 REJ03B0179-0102 (4) Return signal An external wakeup signal is used to return from the RAM back- up mode because the oscillation is stopped. Table 20 shows the return condition for each return source. (5) Control registers

• Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the T AK0 instruction can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition, the T AK1 instruction can be used to transfer the contents of register K1 to register A.
• Key-on wakeup control register K2 Register K2 controls the ports K and P2 key-on wakeup function. Set the contents of th is register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A.
• Key-on wakeup control register L1 Register L1 controls the selection of the selection of the INT0 pin return condition and INT0 pin key-on wakeup function and the selection of the INT1 pin return condition and INT1 pin key-on wakeup function. Set the contents of this register through register A with the TL1A instruction. In addition, the TAL1 instruction can be used to transfer the contents of register L1 to register A.
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of th is register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of th is register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A.
• Pull-up control register PU2 Register PU2 controls the ON/ OFF of the ports P2 pull-up transistor. Set the contents of th is register through register A with the TPU2A instruction. In addition, the TAPU2 instruction can be used to transfer the contents of register PU2 to register A.
• Interrupt control register I1 Register I1 controls the valid waveform/level of the INT0 pin and the input control of INT0 pin. Set the contents of this register through register A wi th the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 20 Return source and return condition Return source Return condition Remarks External wakeup signal Port P00−P03 Port P10−P13 Port P20, P21 Port K Return by an external falling edge (“H” → “L”) input. The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to “H” level before going into the RAM back-up state. INT pin Return by an external “H” level or “L” level input, or falling edge (“H” → “L”) or rising edge (“L” → “H”). When the return level is input, the EXF0 flag is not set. The key-on wakeup function can be selected by one port unit. Select the return level (“L” level or “H” level) with the register I1 and return condition (level or edge) with the register L1 according to the external state before going into the RAM back-up state.

Rev.1.02 May 25, 2007 Page 46 of 124 REJ03B0179-0102 Fig 47. State transition Fig 48. Set source and clear source of the P flag Fig 49. Start condition identified example using the SNZP instruction Notes 1: Microcomputer starts its operation after counting f( XIN) 5400 to 5424 times from system is released from reset. 2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 3: The operation mode also returns to the initial state (internal frequency divided by 4 mode) (register MR initialized). State A Operating state f(XIN) : operating POF instruction execution (Note 2) Key-on wakeup (Notes 1, 3) Reset (Note 1) State D RAM back-up mode f(XIN) : Stop QS+ R EPOF instruction POF instruction Internal reset signal Power down flag (P) - Set source ... - Clear source ... Reset EPOF instruction + POF instruction P = “1” Yes No Warm start SNZP instruction Cold start Software start

Rev.1.02 May 25, 2007 Page 47 of 124 REJ03B0179-0102 Note 1.“R” represents read enabled, and “W” represents write enabled. Table 21 Key-on wakeup control registers Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W TAK0/TK0A K03 Port P03 key-on wakeup control bit

0 Key-on wakeup not used

1 Key-on wakeup used

Key-on wakeup control register K1 at reset : 0000 2 at RAM back-up : state retained R/W TAK1/TK1A K13 Port P13 key-on wakeup control bit Key-on wakeup control register K2 at reset : 0000 2 at RAM back-up : state retained R/W TAK2/TK2A K23 Not used 0 This bit has no function, but read/write is enabled.1 K22 Port K key-on wakeup control bit Key-on wakeup control register L1 at reset : 0000 2 at RAM back-up : state retained R/W TAL1/TL1A L13 INT1 pin return condition selection bit

0 Return by level

1 Return by edge

return condition selection bit

Rev.1.02 May 25, 2007 Page 48 of 124 REJ03B0179-0102 Note 1.“R” represents read enabled, and “W” represents write enabled. Table 22 Pull-up control registers Pull-up control register PU0 at reset : 0000 2 at RAM back-up : state retained R/W TAPU0/TPU0A PU03 Port P03 pull-up transistor control bit

0 Pull-up transistor OFF

1 Pull-up transistor ON

Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 at reset : 0000 2 at RAM back-up : state retained R/W TAPU1/TPU1A PU13 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU2 at reset : 0000 2 at RAM back-up : state retained R/W TAPU2/TPU2A PU23 Not used 0 This bit has no function, but read/write is enabled.1 PU22 Not used 0 This bit has no function, but read/write is enabled.1 PU21 Port P21 pull-up transistor control bit Port P20 pull-up transistor control bit

Rev.1.02 May 25, 2007 Page 49 of 124 REJ03B0179-0102 The clock control circuit consists of the following circuits.

• Ceramic oscillation circuit
• Frequency divider
• Internal clock generating circuit The system clock and the instruct ion clock are generated as the source clock for operation by these circuits. Figure 50 shows the structure of the clock control circuit. Fig 50. Clock control circuit structure XIN MR3, MR2Division circuit divided by 8 divided by 4 divided by 2 Internal clock generation circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) Ceramic oscillation circuit Voltage drop detection circuit (reset occurs) S R Q EPOF instruction + POF instruction Key-on wakeup signal RESET Oscillation stop signal

Rev.1.02 May 25, 2007 Page 50 of 124 REJ03B0179-0102 (1) Ceramic resonator When the ceramic resonator is used as the main clock (f(X IN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT (Figure 51). (2) External clock When the external signal cloc k is used for the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 52). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (3) Clock control register MR Register MR controls the select ion of operation mode. Set the contents of this register th rough register A with the TMRA instruction. In addition, the TA MR instruction can be used to transfer the contents of register MR to register A. Fig 51. Ceramic resonator external circuit Fig 52. External clock input circuit Note 1.“R” represents read enabled, and “W” represents write enabled. XIN XOUT CIN COUT Rd Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. 4571 XIN XOUT 4571 External oscillation circuit VDD VSS Table 23 Return source and return condition Clock control register MR at reset : 1111 2 at RAM back-up : 11112 R/W TAMR/TMRA MR3 Operation mode selection bits MR3 MR2 Operation mode 0 0 Through mode (frequency not divided) 0 1 Frequency divided by 2 mode MR 2 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode MR 1 Not used 0 This bit has no function, but read/write is enabled.1 MR0 Not used 0 This bit has no function, but read/write is enabled.1

Rev.1.02 May 25, 2007 Page 51 of 124 REJ03B0179-0102 In the QzROM writing mode , the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is applicable for this microcomputer. Table 24 lists the pin descript ion (QzROM writing mode) and Figure 53 shows the pin connections. Refer to Figure 54 for examples of a connection with a serial pro- grammer. Contact the manufacturer of y our serial programmer for serial pro-grammer. Refer to the user’s manual of your serial programmer for details on how to use it. Table 24 Pin description (QzROM writing mode) Pin Name I/O Function VDD Power source − • Power supply voltage pin. VSS GND − • GND pin. KV PP input − • QzROM programmable power source pin. P01 SDA input/output I/O • QzROM serial data I/O pin. P00 SCLK input Input • QzROM serial clock input pin. P10 PGM input Input • QzROM read/program pulse input pin. RESET Reset input Input • Reset input pin.

• Input “L” level signal. XIN Clock input − • Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open.XOUT Clock output − P02, P03, P11−P13, P20/INT0, P21/INT1, P30, P31, D0−D3, D4/CNTR0, C/CNTR1 I/O port I/O • Input “H” or “L” le vel signal or leave the pin open.

Rev.1.02 May 25, 2007 Page 52 of 124 REJ03B0179-0102 Fig 53. Pin connection diagram 12P11 P12 11P10 P13 10P03 P20/INT0 9P02 P21/INT1 8P01 P30 7P00 P31 D0RESET K 5 XOUT 4 XIN 3 VSS 2 D4/CNTR0 1VDD C/CNTR1 M34571GxFP M34571Gx-XXXFP Note: Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. VDD VSS (Note) VPP SCLK SDA PGM RESET : QzROM pin

Rev.1.02 May 25, 2007 Page 53 of 124 REJ03B0179-0102 Fig 54. When using programmer of Suisei Electronics System Co., LTD, connection example T_VDD T_VPP T_RXD T_SCLK T_PGM/OE/MD T_RESET GND RESET circuit Either connect an oscillation circuit or connect XIN pin to VSS and leave the XOUT pin open. VDD K P01 (SDA) P00 (SCLK) P10 (PGM) RESET Vss XIN XOUT Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. T_BUSY T_TXD 1 kΩ N.C.

Rev.1.02 May 25, 2007 Page 54 of 124 REJ03B0179-0102 DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specification form, refer to th e “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer.

Rev.1.02 May 25, 2007 Page 55 of 124 REJ03B0179-0102 (1) Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire. Port K is also used as V PP pin. Accordingly, when using this pin, connect this pin to VSS or VDD. Do not leave this pin open. When port is used for key matrix, connect it to V DD through a pull-up resistor. (2) Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits) (4) Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits) (5) Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. (6) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. (7) Multifunction
• The input of D 4 can be used even when CNTR0 (output) is selected. The input/output of D 4 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and D4 since the input threshold value of CNTR0 pin is different from that of port D4.
• “H” output function of port C can be used even when the CNTR1 (output) is used.
• The input/output of P2 0 can be used even when INT0 is used. Be careful when using inputs of both INT0 and P2 0 since the input threshold value of INT0 pin is different from that of port P20.
• The input/output of P2 1 can be used even when INT1 is used. Be careful when using inputs of both INT1 and P2 1 since the input threshold value of INT1 pin is different from that of port (8) Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (9) POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF inst ruction and the POF instruction continuously.

Rev.1.02 May 25, 2007 Page 56 of 124 REJ03B0179-0102 (10)P20/INT0 pin (1) Bit 3 of register I1 When the input of the P2 0/INT0 pin is controlled with the bit 3 of register I1 in so ftware, be careful about the following notes.

• Depending on the input state of the P20/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 55) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 55). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 55). Fig 55. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes.
• When the INT0 pin input is disabled (register I1 3 = “0”), set the key-on wakeup of INT0 pin to be invalid (register L1 0 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 56). Fig 56. External 0 interrupt program example-2 (3) Bit 2 of register I1 When the interrupt valid waveform of the P2 0/INT0 pin is changed with the bit 2 of regist er I1 in software, be careful about the following notes.
• Depending on the input state of the P20/INT0 pin, the external 1 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to (1) in Figure 57) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to (2) in Figure 57). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instru ction (refer to (3) in Figure 57). Fig 57. External 0 interrupt program example-3
• •• LA 4 ; ( ×××02) LA 8 ; (1 ×××2) TI1A ; Control of INT0 pin input is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here. LA 0 ; ( ×××02) DI EPOF POF ; RAM back-up
• •• ×: these bits are not used here. LA 4 ; ( ×××02) LA 12 ; (1 ×××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed (EXF0 flag cleared)
• •• ×: these bits are not used here.

Rev.1.02 May 25, 2007 Page 57 of 124 REJ03B0179-0102 (11)P21/INT1 pin (1) Bit 3 of register I2 When the input of the P2 1/INT1 pin is controlled with the bit 3 of register I2 in so ftware, be careful about the following notes.

• Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 58) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 58). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instru ction (refer to (3) in Figure 58). Fig 58. External 1 interrupt program example-1 (2) Bit 3 of register I2 When the bit 3 of register I2 is cleared to “0”, the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes.
• When the INT1 pin input is disabled (register I2 3 = “0”), set the key-on wakeup of INT1 pin to be invalid (register L2 0 = “0”) before system enters to the RAM back-up mode. (refer to (1) in Figure 59) Fig 59. External 1 interrupt program example-2 (3) Bit 2 of register I2 When the interrupt valid waveform of the P2 1/INT1 pin is changed with the bit 2 of regist er I2 in software, be careful about the following notes.
• Depending on the input state of the P21/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to (1) in Figure 60) and then, change the bit 2 of register I2 is changed. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one instruction (refer to (2) in Figure 60). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instru ction (refer to (3) in Figure 60). Fig 60. External 1 interrupt program example-3
• •• LA 4 ; ( ××0×2) LA 8 ; (1 ×××2) TI1A ; Control of INT1 pin input is changed SNZ0 ; The SNZ1 instruction is executed (EXF1 flag cleared)
• •• ×: these bits are not used here. LA 0 ; ( ×0××2) DI EPOF POF ; RAM back-up
• •• ×: these bits are not used here. LA 4 ; ( ××0×2) LA 12 ; (1 ×××2) TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ1 instruction is executed (EXF1 flag cleared)
• •• ×: these bits are not used here.

Rev.1.02 May 25, 2007 Page 58 of 124 REJ03B0179-0102 (12)Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. (13)Timer count source Stop timer 1, 2 or 3 counting to change its count source. (14)Reading the count value Stop timer 1, 2 or 3 counting a nd then execute the TAB1, TAB2 or TAB3 instruction to read its data. (15)Writing to the timer Stop timer 1, 2 or 3 counting and then execute the T1AB, T2AB, T3AB or T3R3L instruction to write data to timer. (16)Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR 1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R3H while the timer 3 is operating, execute the T3HAB instruction except a timing of the timer 3 underflow. (17)PWM signal If the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When “H” interval expansion function of the PWM signal is used, set “1” or more to reload register R3H. Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin. (18)Prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 61 after prescaler and tim er operations start (1) in Figure 61. Time to first underflow (3) in Figu re 61 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 61 by the timing to start the timer and count source operations after count starts. When selecting CNTR0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of CNTR0 input selected by software. Fig 61. Timer count start timing and count time when operation starts (19)Watchdog timer

• The watchdog timer function is valid after system is released from reset. When not usi ng the watchdog timer function, execute the DWDT instructio n and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode.
• When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. (20)External clock Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (21)QzROM (1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritte n because of overvoltage. Take care especially at turning on the power. (2) As for the product shippe d in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. (22)Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than “00 16” and “FF 16” can not be accepted. Count source (3) (4) (1) Timer start (2) Count source (When falling edge of CNTR0 input is selected) Timer 1 value Timer 1 underflow signal 32 1 0 3 2 1 0 3 2

Rev.1.02 May 25, 2007 Page 59 of 124 REJ03B0179-0102 Countermeasures against noise are described below. The following counte rmeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1. Shortest wiring length (1) Wiring for RESET pin Make the length of wiring whic h is connected to the RESET pin as short as possible. Especially , connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring. <Reason> In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse wi dth than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig 62. Wiring for the RESET pin (2) Wiring for cloc k input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Fig 63. Wiring for clock I/O pins (3) Port K Wiring Do not leave port K open. Always connect it to the V DD pin or VSS pin using the thickest wire at the shortest distance. When port K is used for key matrix, connect it to the V DD pin through a pull-up resistor. In that case too, place a pull-up resistor close to port K and connect it to port K or the V DD pin using the thickest wire at the shortest distance as above. <Reason> Port K is also used as th e power source input pin (V PP pin) for the built-in QzROM. When programming to the QzROM, the impedance of port K is low so that the electric writing current will flow into the QzROM. This allows noise to en ter easily. If noise enters from port K, abnormal instruction co des or data are read from the QzROM, which may cause a program runaway. Fig 64. Wiring for port K RESETReset circuit Noise VSSVSS N.G. Reset circuit VSS RESET VSS O.K. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. VDD VSS K Shortest distance (Note) (Note) Note: This indicates pin. VDD VSS K Shortest distance (Note) (Note) VDD VSS K Shortest distance Shortest distance A pull-up resistor (Note) (Note)

Rev.1.02 May 25, 2007 Page 60 of 124 REJ03B0179-0102

1. Connection of bypass capacitor across V SS line and VDD line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VDD line as follows:

• Connect a bypass capacitor across the VSS pin and the VDD pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. Fig 65. Bypass capacitor across the V SS line and the VDD line 3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Be sides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. <Reason> Signals which is input in an an alog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Fig 66. Analog signal line and a resistor and a capacitor VSS VDD VSS VDD N.G. O.K. Thermistor Analog input pin (Note) N.G. O.K. VSS Note : The resistor is used for dividing resistance with a thermistor. Microcomputer Noise

Rev.1.02 May 25, 2007 Page 61 of 124 REJ03B0179-0102

1. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcom puter, there are signal lines for controlling motors, LEDs, and ther mal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a conn ecting pattern of an oscillator away from signal lines where pote ntial levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such line s cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Fig 67. Wiring for a large current signal line Fig 68. Wiring to a signal line where potential levels change frequently (3) Oscillator protection using V SS pattern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides, separate this V SS pattern from other VSS patterns. Fig 69. Vss pattern on the underside of an oscillator 5. Setup fo r I/O ports Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to pull-up control registers at fixed periods. 6. Providing of watchdog timer function by software If a microcomputer runs away becau se of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In th e following example, to reset a microcomputer to nor mal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that in terrupt processing is repeated multiple times in a single main routine processing. XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross N.G. Oscillator wiring pattern example An example of VSS patterns on the underside of a printed circuit board Separate the VSS line for oscillation from other VSS lines XIN XOUT VSS

Rev.1.02 May 25, 2007 Page 62 of 124 REJ03B0179-0102 <The main routine>

• Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and deter-mines to branch to the pr ogram initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: If the SWDT contents are not in itialized to the initial value N but continued to decrement and if they reach 0 or less. Fig 70. Watchdog timer by software N Main routine (SWDT) ← N EI Main processing (SWDT) =N? Interrupt processing routine errors Interrupt processing routine (SWDT) ← (SWDT)−1 Interrupt processing (SWDT) ≤0? RTI Return Main routine errors

Rev.1.02 May 25, 2007 Page 63 of 124 REJ03B0179-0102 Note 1.”R” represents read enabled, and “W” represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set. Interrupt control register V1 at reset : 0000 2 at RAM back-up : 00002 R/W TAV1/TV1A V13 Timer 2 interrupt enable bit 0 Interrupt disabled (SNZT2 instruction is valid) V12 Timer 1 interrupt enable bit 0 Interrupt disabled (SNZT1 instruction is valid) V11 External 1 interrupt enable bit 0 Interrupt disabled (SNZ1 instruction is valid) V10 External 0 interrupt enable bit 0 Interrupt disabled (SNZ0 instruction is valid) Interrupt control register V2 at reset : 0000 2 at RAM back-up : 00002 R/W TAV2/TV2A V23 Voltage drop detector interrupt enable bit 0 Interrupt disabled (SNZVD instruction is valid) V22 Not used 0 This bit has no function, but read/write is enabled.1 V21 Not used 0 This bit has no function, but read/write is enabled.1 V20 Timer 3 interrupt enable bit 0 Interrupt disabled (SNZT3 instruction is valid) Interrupt control register I1 at reset : 0000 2 at RAM back-up : state retained R/W TAI1/TI1A I13 INT0 pin input control bit (Note 2) 0 INT0 pin input disabled Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) instruction)/“L” level instruction)/“H” level I11 INT0 pin edge detection circuit control bit 0 One-sided edge detected timer 1 control enable bit Interrupt control register I2 at reset : 0000 2 at RAM back-up : state retained R/W TAI2/TI2A I23 INT1 pin input control bit (Note 3) 0 INT0 pin input disabled Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) instruction)/“L” level instruction)/“H” level I21 INT1 pin edge detection circuit control bit 0 One-sided edge detected I20 Not used 0 This bit has no function, but read/write is enabled.1

Rev.1.02 May 25, 2007 Page 64 of 124 REJ03B0179-0102 Note 1.“R” represents read enabled, and “W” represents write enabled. Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is selected (W53 =“1”). Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”). Timer control register PA at reset : 00 2 at RAM back-up : 002 W TPAA PA1 Prescaler count source selection bit 0 Instruction clock (INSTCK)

1 Instruction clock di vided by 4 (INSTCK)/4

PA0 Prescaler control bit 0 Stop (state initialized) 1O p e r a t i n g Timer control register W1 at reset : 0000 2 at RAM back-up : state retained R/W TAW1/TW1A W13 Timer 1 count auto-stop circuit selection bit (Note 2) W12 Timer 1 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 1 count source selection bits W11 W10 Count source W11 0 0 PWM output (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 System clock (STCK)W10 1 1 CNTR0 input Timer control register W2 at reset : 0000 2 at RAM back-up : state retained R/W TAW2/TW2A W23 CNTR0 pin function selection bit 0 Timer 1 underflow signal divided by 2 output W22 Timer 2 control bit 0 Stop (state retained) 1O p e r a t i n g Timer 2 count source selection bits W21 W20 Count source W21 0 0 PWM output (PWMOUT) 0 1 Prescaler output (ORCLK) 1 0 System clock (STCK)W20 1 1 Timer 1 underflow signal (T1UDF) Timer control register W3 at reset : 0000 2 at RAM back-up : 00002 R/W TAW3/TW3A W33 CNTR1 pin output control bit 0 CNTR1 pin output invalid “H” interval expansion function control bit

0 PWM signal “H” interval ex pansion function invalid

W31 Timer 3 control bit 0 Stop (state retained) 1O p e r a t i n g W30 Timer 3 count source selection bit 0X IN input

1 Prescaler output/2

Timer control register W5 at reset : 0000 2 at RAM back-up : state retained R/W TAW5/TW5A W53 Timer 1 count start synchronous circuit selection bit (Note 3) W52 CNTR0 pin input count edge selection bit 0 Falling edge CNTR 1 pin output auto-control circuit selection bit W50 D4/CNTR0 pin function selection bit 0D 4 (I/O) / CNTR0 (input) 1D 4 (input) /CNTR0 (I/O)

Rev.1.02 May 25, 2007 Page 65 of 124 REJ03B0179-0102 Note 1.“R” represents read enabled, and “W” represents write enabled. Clock control register MR at reset : 1111 2 at RAM back-up : 11112 R/W TAMR/TMRA Operation mode selection bits MR3 MR2 Operation mode MR3 0 0 Through mode (frequency not divided) 0 1 Frequency divided by 2 mode 1 0 Frequency divided by 4 modeMR2 1 1 Frequency divided by 8 mode MR1 Not used 0 This bit has no function, but read/write is enabled.1 MR0 Not used 0 This bit has no function, but read/write is enabled.1 Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W TAK0/TK0A K03 Port P03 key-on wakeup control bit 0 Key-on wakeup not used K02 Port P02 key-on wakeup control bit 0 Key-on wakeup not used K01 Port P01 key-on wakeup control bit 0 Key-on wakeup not used K00 Port P00 key-on wakeup control bit 0 Key-on wakeup not used Key-on wakeup control register K1 at reset : 0000 2 at RAM back-up : state retained R/W TAK1/TK1A K13 Port P13 key-on wakeup control bit 0 Key-on wakeup not used K12 Port P12 key-on wakeup control bit 0 Key-on wakeup not used K11 Port P11 key-on wakeup control bit 0 Key-on wakeup not used K10 Port P10 key-on wakeup control bit 0 Key-on wakeup not used Key-on wakeup control register K2 at reset : 0000 2 at RAM back-up : state retained R/W TAK2/TK2A K23 Not used 0 This bit has no function, but read/write is enabled.1 K22 Port K key-on wakeup control bit 0 Key-on wakeup not used K21 Port P21 key-on wakeup control bit 0 Key-on wakeup not used K20 Port P20 key-on wakeup control bit 0 Key-on wakeup not used Key-on wakeup control register L1 at reset : 0000 2 at RAM back-up : state retained R/W TAL1/TL1A L13 INT1 pin return condition selection bit 0 Return by level

0 Falling waveform/“L” level

1 Rising waveform/“H” level

return condition selection bit

Rev.1.02 May 25, 2007 Page 66 of 124 REJ03B0179-0102 Note 1. “R” represents read enabled, and “W” represents write enabled. Pull-up control register PU0 at reset : 0000 2 at RAM back-up : state retained R/W TAPU0/TPU0A PU03 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 at reset : 0000 2 at RAM back-up : state retained R/W TAPU1/TPU1A PU13 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU2 at reset : 0000 2 at RAM back-up : state retained R/W TAPU2/TPU2A PU23 Not used 0 This bit has no function, but read/write is enabled.1 PU22 Not used 0 This bit has no function, but read/write is enabled.1 PU21 Port P21 pull-up transistor control bit Port P20 pull-up transistor control bit Port output structure control register FR0 at reset : 0000 2 at RAM back-up : state retained W TFR0A FR03 Not used 0 This bit has no function, but read/write is enabled.1 FR02 Not used 0 This bit has no function, but read/write is enabled.1 FR01 Port P31 output structure selection bit 0 N-channel open-drain output

1 CMOS output

FR00 Port P30 output structure selection bit 0 N-channel open-drain output Port output structure control register FR1 at reset : 0000 2 at RAM back-up : state retained W TFR1A FR13 Port D3 output structure selection bit 0 N-channel open-drain output FR12 Port D2 output structure selection bit 0 N-channel open-drain output FR11 Port D1 output structure selection bit 0 N-channel open-drain output FR10 Port D0 output structure selection bit 0 N-channel open-drain output

Rev.1.02 May 25, 2007 Page 67 of 124 REJ03B0179-0102 Each instruction is described as follows; 1. Index list of instruction function 2. Machine instructions (index by alphabet) 3. Machine instructions (index by function) 4. Instruction code table The symbols shown below are used in the following list of instruction function and the machine instructions. Note 1.The 4571 Group just invalidates the next instruction w hen a skip is performed. The contents of program counter is not in creased by 2. Accordingly, the number of cycles does not change even if skip is no t performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SYMBOL Symbol Contents Symbol Contents A Register A (4 bits) T1F Timer 1 interrupt request flag B Register B (4 bits) T2F Timer 2 interrupt request flag DR Register DR (3 bits) T3F Timer 3 interrupt request flag E Register E (8 bits) WDF1 Watchdog timer flag V1 Interrupt control register V1 (4 bits) WEF Watchdog timer enable flag V2 Interrupt control register V2 (4 bits) INTE Interrupt enable flag I1 Interrupt control register I1 (4 bits) EXF0 External 0 interrupt request flag I2 Interrupt control register I2 (4 bits) EXF1 External 1 interrupt request flag PA Timer control register PA (2 bits) VDF Volt age drop detection circuit interrupt request flag W1 Timer control register W1 (4 bits) P Power down flag W2 Timer control register W2 (4 bits) D Port D (5 bits) W3 Timer control register W3 (4 bits) P0 Port P0 (4 bits) W5 Timer control register W5 (4 bits) P1 Port P1 (4 bits) MR Clock control regist er MR (4 bits) P2 Port P2 (2 bits) K0 Key-on wakeup control register K0 (4 bits) P3 Port P3 (2 bits) K1 Key-on wakeup control register K1 (4 bits) K2 Key-on wakeup control register K2 (4 bits) x Hexadecimal variable L1 Key-on wakeup control register L1 (4 bits) y Hex adecimal variable PU0 Pull-up control register PU0 (4 bits) z Hexadec imal variable PU1 Pull-up control register PU1 (4 bits) p Hexadec imal variable PU2 Pull-up control register PU2 (4 bits) n Hexadecimal constant FR0 Port output structure control regist er FR0 (4 bits) i H exadecimal constant FR1 Port output structure control regist er FR1 (4 bits) j H exadecimal constant X Register X (4 bits) A

3 A2 A1 A0 Binary notation of hexadecimal variable A

(same for others)Y Register Y (4 bits) Z Register Z (2 bits) DP Data pointer (10 bits) (It consists of registers X, Y, and Z) ← Direction of data movement ( ) Contents of registers and memories PC Program counter (14 bits) − Negate, Flag unchanged after executing instruction PCH High-order 7 bits of program counter M (DP) RAM address pointed by the data pointer PCL Low-order 7 bits of program counter a Label indi cating address a6 a5 a4 a3 a2 a1 a0 SK Stack register (14 bits × 8) p, a Label indicating address a 6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0SP Stack pointer (3 bits) CY Carry flag RPS Prescaler reload register (8 bits) C Hex. C + Hex. number x (also same for others) R1L Timer 1 reload register (8 bits) + R2 Timer 2 reload register (8 bits) x R3L Timer 3 reload register (8 bits ) ? Decision of state shown before “?” R3H Timer 3 reload register (8 bits) ← → Data exchange between a register and memory PS Prescaler T1 Timer 1 AND Logical multiplication T2 Timer 2 OR Logical addition T3 Timer 3

Rev.1.02 May 25, 2007 Page 68 of 124 REJ03B0179-0102 M34571G4: p=0 to 31 M34571G6: p=0 to 47 M34571GD: p=0 to 127 INDEX LIST OF INSTRUCTION FUNCTION Group ing Mnemonic Function Page Register to register transfer TEAB (E 7−E4) ← (B) (E3−E0) ← (A) 96, 103 TABE (B) ← (E7−E4) (A) ← (E3−E0) 89, 103 TDA (DR 2−DR0) ← (A2−A0) 95, 103 TAD (A 2−A0) ← (DR2−DR0) (A3) ← 0 90, 103 TAZ (A 1, A0) ← (Z1, Z0) (A3, A2) ← 0 95, 103 TASP (A 2−A0) ← (SP2−SP0) (A3) ← 0 93, 103 RAM addresses LXY x, y (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 77, 103 LZ z (Z) ← z, z = 0 to 3 77, 103 RAM to register transfer TAM j (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 91, 103 XAM j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 102, 103 XAMD j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 102, 103 XAMI j (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 102, 103 TMA j (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 98, 103 Group ing Mnemonic Function Page Arithmetic operation LA n (A) ← n n = 0 to 15 76, 105 TABP p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (UPTF) = 1, (DR2) ← 0 (DR1, DR0) ← (ROM(PC))9, 8 (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 89, 105 AMC (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry 71, 105 A n (A) ← (A) + n n = 0 to 15 71, 105 AND (A) ← (A)AND(M(DP)) 71, 105 OR (A) ← (A)OR(M(DP)) 78, 105 SC (CY) ← 1 82, 105 RC (CY) ← 0 80, 105 SZC (CY) = 0 ? 86, 105 RAR 79, 105 Bit operation SB j (Mj(DP)) ← 1 j = 0 to 3 81, 105 RB j (Mj(DP)) ← 0 j = 0 to 3 79, 105 SZB j (Mj(DP)) = 0 ? j = 0 to 3 86, 105 Comparison operation SEAM (A) = (M(DP)) ? 83, 107 SEA n (A) = n n = 0 to 15 83, 107 Branch operation B a (PC L) ← a6−a0 72, 107 BL p, a (PC H) ← p (PCL) ← a6−a0 72, 107 BLA p (PC H) ← p (PCL) ← (DR2−DR0, A3−A0) 72, 107 CY A3A2A1A0

Rev.1.02 May 25, 2007 Page 69 of 124 REJ03B0179-0102 M34571G4: p=0 to 31 M34571G6: p=0 to 47 M34571GD: p=0 to 127 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group ing Mnemonic Function Page Subroutine operation BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 72, 107 BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 73, 107 BMLA p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) 73, 107 Return operation RTI (PC) ← (SK(SP)) (SP) ← (SP) − 1 81, 107 RT (PC) ← (SK(SP)) (SP) ← (SP) − 1 80, 107 RTS (PC) ← (SK(SP)) (SP) ← (SP) − 1 81, 107 Interrupt operation DI (INTE) ← 0 74, 109 EI (INTE) ← 1 74, 109 SNZ0 V1 0 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : NOP 83, 109 SNZI0 I1 2 = 0 : (INT0) = “L” ? 84, 109 SNZ1 V1 1 = 0 : (EXF1) = 1 ? (EXF1) ← 0 V11 = 1 : NOP 83, 109 SNZI1 I2 2 = 0 : (INT1) = “L” ? 84, 109 TV1A (V1) ← (A) 100, 109 TV2A (V2) ← (A) 100, 109 Group ing Mnemonic Function Page Timer operation TPAA (PA 0) ← (A0) 98, 109 TW1A (W1) ← (A) 100, 109 TW2A (W2) ← (A) 101, 109 TW3A (W3) ← (A) 101, 109 TW5A (W5) ← (A) 101, 109 TABPS (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) 89, 111 TPSAB (RPS 7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) 99, 111 TAB1 (B) ← (T17−T14) (A) ← (T13−T10) 88, 111 T1AB (R1 7−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) 87, 111 TR1AB (R1 7−R14) ← (B) (R13−R10) ← (A) 100, 111 TAB2 (B) ← (T27−T24) (A) ← (T23−T20) 88, 111 T2AB (R2 7−R24) ← (B) (T27−T24) ← (B) (R23−R20) ← (A) (T23−T20) ← (A) 87, 111 TAB3 (B) ← (T37−T34) (A) ← (T33−T30) 89, 111 T3AB (R3L 7−R3L4) ← (B) (T37−T34) ← (B) (R3L3−R3L0) ← (A) (T33−T30) ← (A) 87, 111 T3R3L (T3 7−T30) ← (R3L7−R3L0) 88, 111 T3HAB (R3H 7−R3H4) ← (B) (R3H3−R3H0) ← (A) 87, 111

Rev.1.02 May 25, 2007 Page 70 of 124 REJ03B0179-0102 INDEX LIST OF INSTRUCTION FUNCTION (continued) Group ing Mnemonic Function Page Timer operation SNZT1 V1 2 = 0 : (T1F) = 1 ? (T1F) ← 0 V12 = 1 : SNZT1=NOP 84, 111 SNZT2 V1 3 = 0 : (T2F) = 1 ? (T2F) ← 0 V13 = 1 : SNZT2=NOP 85, 111 SNZT3 V2 0 = 0 : (T3F) = 1 ? (T3F) ← 0 V20 = 1 : SNZT3=NOP 85, 111 Input/Output operation IAP2 (A 1, A0) ← (P21, P20) (A3, A2) ← 0 76, 113 OP2A (P2 1, P20) ← (A1, A0) 78, 113 IAP3 (A 1, A0) ← (P31, P30) (A3, A2) ← 0 76, 113 OP3A (P3 1, P30) ← (A1, A0) 78, 113 CLD (D) ← 1 73, 113 RD (D(Y)) ← 0 (Y) = 0 to 4 80, 113 SD (D(Y)) ← 1 (Y) = 0 to 4 82, 113 SZD (D(Y)) = 0 ? (Y) = 0 to 4 86, 113 IAK (A 0) ← (K) (A3−A1) ← 0 75, 113 TFR0A (FR0) ← (A) 96, 113 TFR1A (FR1) ← (A) 96, 113 TAPU0 (A) ← (PU0) 92, 113 TPU0A (PU0) ← (A) 99, 113 TAPU1 (A) ← (PU1) 92, 113 TPU1A (PU1) ← (A) 99, 113 TAPU2 (A) ← (PU2) 92, 113 TPU2A (PU2) ← (A) 99, 113 Group ing Mnemonic Function Page Input/Output operation Other operation TAMR (A) ← (MR) 92, 115 TMRA (MR) ← (A) 98, 115 NOP (PC) ← (PC)+1 77, 115 POF RAM back-up 79, 115 EPOF POF instruction valid 75, 115 SNZP (P) = 1 ? 84, 115 SNZVD V2 3 = 0 : (VDF) = 1? V23 = 0 : NOP 85, 115 WRST (WDF1) = 1 ? (WDF1) ← 0 102, 115 DWDT Stop of watchdog timer function enabled 74, 115 SRST System reset 85, 115 RUPT (UPTF) ←0 81, 115 SUPT (UPTF) ←1 86, 115 RBK p 6 ← 0 when TABP p instruction is executed 79, 115 SBK p 6 ← 1 when TABP p instruction is executed 82, 115

Rev.1.02 May 25, 2007 Page 71 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 000110nnnn 2 06n 16 11- O v e r f l o w = 0 Opera- tion: (A) ← (A) + n n = 0 to 15 Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. AM (Add accumulator and Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001010 2 00A 16 11- - Opera- tion: (A) ← (A)Å{(M(DP)) Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001011 2 00B 16 11 0 / 1 - Opera- tion: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. AND (logical AND between accumulator and memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011000 2 018 16 11- - Opera- tion: (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in regis- ter A.

Rev.1.02 May 25, 2007 Page 72 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) B a (Branch to address a) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 011 a 6 a5 a4 a3 a2 a1 a0 2 1 8 +a a 16 11- - Opera- tion: (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch within a page : Branches to address a in the identi- cal page. Note: Specify the branch address within the page including this instruction. BL p,a (Branch Long to address a in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00111 p 4 p3 p2 p1 p0 2 0 E +p p 16 2 2 - - 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2 2aa 16 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Opera- tion: (PCH) ← p (PCL) ← a6 to a0 BLA p (Branch Long to address (D)+(A) in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010000 2 010 16 22- - 1p 6 p5 p4 00 p 3 p2 p1 p0 2 2pp 16 Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Opera- tion: (PC H) ← p (PCL) ← (DR2−R0, A3−A0) BM a (Branch and Mark to address a in page 2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 010 a 6 a5 a4 a3 a2 a1 a0 2 1aa 16 11- - Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.

Rev.1.02 May 25, 2007 Page 73 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BML p,a (Branch and Mark Long to address a in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00110 p 4 p3 p2 p1 p0 2 0 c +p p 16 22- - 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2 2aa 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Be careful not to over the stack because the maximum level of subroutine nesting is 8. Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6−a0 BMLA p (Branch and Mark Long to address (D)+(A) in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000110000 2 030 16 22- - 1p 6 p5 p4 00 p 3 p2 p1 p0 2 2pp 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 Be careful not to over the stack because the maximum level of subroutine nesting is 8. Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) CLD (CLear port D) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010001 2 011 16 11- - Opera- tion: (D) ← (1) Grouping: Input/Output operation Description: Sets (1) to port D. CMA (CoMplement of Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011100 2 01C 16 11- - Opera- tion: (A) ←(A) Grouping: Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A.

Rev.1.02 May 25, 2007 Page 74 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DEY (DEcrement register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010111 2 017 16 11- ( Y ) = 1 5 Opera- tion: (Y) ← (Y) −1 Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.DI (Disable Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000100 2 004 16 11- - Opera- tion: (INTE) ← 0 Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by ex ecuting the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010011100 2 29C 16 11- - Opera- tion: Stop of watchdog timer function enabled Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. EI (Enable Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000101 2 005 16 11- - Opera- tion: (INTE) ← 1 Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.

Rev.1.02 May 25, 2007 Page 75 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EPOF (Enable POF instruction) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011011 2 05B 16 11- - Opera- tion: POF instruction valid Grouping: Other operation Description: Makes the immediate after POF instruction valid by exe- cuting the EPOF instruction. IAK (Input Accumulator from port K) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001101111 2 26F 16 11- - Opera- tion: (A0) ← (K) (A3−A1) ← 0 Grouping: Input/Output operation Description: Transfers the input of port K to the least significant bit (A0) of register A. “0” is stored to the high-order 3 bits (A3−A1) of register A. IAP0 (Input Accumulator from port P0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100000 2 260 16 11- - Opera- tion: (A) ← (P0) Grouping: Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100001 2 261 16 11- - Opera- tion: (A) ← (P1) Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.

Rev.1.02 May 25, 2007 Page 76 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP2 (Input Accumulator from port P2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100010 2 262 16 11- - Opera- tion: (A3, A2) ← 0 Grouping: Input/Output operation Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. IAP3 (Input Accumulator from port P3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001100011 2 263 16 11- - Opera- tion: (A3, A2) ← 0 Grouping: Input/Output operation Description: Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. INY (INcrement register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010011 2 013 16 11- ( Y ) = 0 Opera- tion: (Y) ← (Y) + 1 Grouping: RAM addresses Description: Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 000111nnnn 2 07n 16 11- Continuous tion: (A) ← n n = 0 to 15 Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and exe- cuted, only the first LA instruction is executed and other LA instructions coded continuously are skipped.

Rev.1.02 May 25, 2007 Page 77 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) LXY x,y (Load register X and Y with x and y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 11 x 3 x2 x1 x0 y3 y2 y1 y0 2 3xy 16 11- Continuous tion: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition

00010010 Z 1 Z0 2 04 8

+z 16 1 1 - - Opera- tion: (Z) ← z z = 0 to 3 Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z. NOP (No OPeration) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000000 2 000 16 11- - Opera- tion: (PC) ← (PC) + 1 Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged. OP0A (Output port P0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100000 2 220 16 11- - Opera- tion: (P0) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.

Rev.1.02 May 25, 2007 Page 78 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP1A (Output port P1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100001 2 221 16 11- - Opera- tion: (P1) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P1. OP2A (Output port P2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100010 2 222 16 11- - Opera- tion: (P21, P20) ← (A1, A0) Grouping: Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of reg- ister A to port P2. OP3A (Output port P3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000100011 2 223 16 11- - Opera- tion: (P31, P30) ← (A1, A0) Grouping: Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of reg- ister A to port P3. OR (logical OR between accumulator and memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011001 2 019 16 11- - Opera- tion: (A) ← (A) OR (M(DP)) Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register

Rev.1.02 May 25, 2007 Page 79 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) POF (Power OFf) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000010 2 002 16 11- - Opera- tion: RAM back-up Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed just before this instruction, this instruction is equivalent to the NOP instruc- tion. RAR (Rotate Accumulator Right) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011101 2 01D 16 11 0 / 1 - Opera- tion: Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00010011 j j 2 04 C +j 16 1 1 - - Opera- tion: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). RBK (Reset BanK flag)) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001001100 2 040 16 11- - Opera- tion: p6 ← 0 when TABP p instruction is executed. Grouping: Other operation Description: Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Note: This instruction cannot be used for the M34571G4/G6. CY A3A2A1A0

Rev.1.02 May 25, 2007 Page 80 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000110 2 006 16 110 - Opera- tion: (CY) ← 0 Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RCP (Reset Port C) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001100 2 28C 16 11- - Opera- tion: (C) ← 0 Grouping: Input/Output operation Description: Clears (0) to port C. RD (Reset port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010100 2 014 16 11- - Opera- tion: (D(Y)) ← 0 However, (Y) = 0 to 4 Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y. RT (ReTurn from subroutine) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000100 2 044 16 12- - Opera- tion: (PC) ← (SK(SP)) (SP) ← (SP) −1 Grouping: Return operation Description: Returns from subroutine to the routine called the subrou- tine.

Rev.1.02 May 25, 2007 Page 81 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTI (ReTurn from Interrupt) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000110 2 046 16 12- - Opera- tion: (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000101 2 045 16 1 2 - Skip at uncondition Opera- tion: (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subrou- tine, and skips the next instruction at uncondition. RUPT (Reset UPT flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011000 2 058 16 11- - Opera- tion: (UPTF) ←0 Grouping: Other operation Description: Clears (0) to the high-order bit reference enable flag UPTF. Note: Even when the table reference instruction (TABP p) is exe- cuted, the high-order 2 bits of ROM reference data is not transferred to register D. SB j (Set Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00010111 j j 2 05 C +j 16 11- - Opera- tion: (Mj(DP)) ← 1 j = 0 to 3 Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

Rev.1.02 May 25, 2007 Page 82 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SBK (Set BanK flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001000001 2 041 16 11- - Opera- tion: p6 ← 1 when TABP p instruction is executed. Grouping: Other operation Description: Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Note: This instruction cannot be used for the M34571G4/G6. SC (Set Carry flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000111 2 007 16 111 - Opera- tion: (CY) ← 1 Grouping: Arithmetic operation Description: Sets (1) to carry flag CY. SCP (Set Port C) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001101 2 28D 16 11- - Opera- tion: (C) ← 1 Grouping: Input/Output operation Description: Sets (1) to port C. SD (Set port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000010101 2 015 16 11- - Opera- tion: (D(Y)) ← 1 (Y) = 0 to 4 Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y . Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y.

Rev.1.02 May 25, 2007 Page 83 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100101 2 025 16 22- (A) = n n = 0 to 15 000111nnnn 2 07n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. Opera- tion: (A) = n ? n = 0 to 15 SEAM (Skip Equal, Accumulator with Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100110 2 026 16 1 1 - (A) = (M(DP)) Opera- tion: (A) = (M(DP)) ? Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111000 2 038 16 11- V 1 0 = 0 : (EXF0) = 1 Opera- tion: (EXF0) ← 0 V10 = 1 : SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Grouping: Interrupt operation Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. SNZ1 (Skip if Non Zero condition of external interrupt 1 request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111001 2 039 16 11- V 1 1 = 0 : (EXF1) = 1 Opera- tion: (EXF1) ← 0 V11 = 1 : SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1) Grouping: Interrupt operation Description: When V11 = 0 : Clears (0) to the EXF1 flag and skips the next instruction when external 1 interrupt request flag EXF1 is “1”. When the EXF1 flag is “0”, executes the next instruction. When V1 1 = 1 : This instruction is equivalent to the NOP instruction.

Rev.1.02 May 25, 2007 Page 84 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111010 2 03A 16 11- I12 = 0 : (INT0) = “L” Opera- tion: (I12 : bit 2 of the interrupt control register I1) Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L”. Executes the next instruction when the level of INT0 pin is “H”. When I1 2 = 1 : Skips the next instruction when the level of INT0 pin is “H.” Executes the next instruction when the level of INT0 pin is “L”. SNZI1 (Skip if Non Zero condition of external Interrupt 1 input pin) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111011 2 03B 16 11- I22 = 0 : (INT1) = “L” Opera- tion: Grouping: Interrupt operation Description: When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L”. Executes the next instruction when the level of INT1 pin is “H”. When I2 2 = 1 : Skips the next instruction when the level of INT1 pin is “H”. Executes the next instruction when the level of INT1 pin is “L”. SNZP (Skip if Non Zero condition of Power down flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000011 2 003 16 11- ( P ) = 1 Opera- tion: (P) = 1 ? Grouping: Other operation Description: Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”. SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000000 2 280 16 11- V 1 2 = 0 : (T1F) = 1 Opera- tion: (T1F) ← 0 V12 = 1 : SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Grouping: Timer operation Description: When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0,” executes the next instruction. When V1 2 = 1 : This instruction is equivalent to the NOP instruction.

Rev.1.02 May 25, 2007 Page 85 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000001 2 281 16 11- V 1 3 = 0 : (T2F) = 1 Opera- tion: (T2F) ← 0 V13 = 1 : SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Grouping: Timer operation Description: When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V1 3 = 1 : This instruction is equivalent to the NOP instruction. SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010000010 2 282 16 11- V 2 0 = 0 : (T3F) = 1 Opera- tion: (T3F) ← 0 V20 = 1 : SNZT3 = NOP Grouping: Timer operation Description: When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. SNZVD (Skip if Non Zero condition of Voltage Detector interrupt request flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010001010 2 28A 16 11- V 2 3 = 0 : (VDF) = 1 Opera- tion: V23 = 1 : SNZVD = NOP Grouping: Other operation Description: When V23 = 0 : Skips the next instruction when voltage detector interrupt request flag VDF is “1”. After skipping, clears (0) to the VDF flag. The VDF flag is not cleared to “0”. When V2 3 = 1 : This instruction is equivalent to the NOP instruction. SRST (System ReSet) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000000001 2 001 16 11- - Opera- tion: System reset Grouping: Other operation Description: System reset occurs.

Rev.1.02 May 25, 2007 Page 86 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SUPT (Set UPT flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001011001 2 059 16 11- - Opera- tion: (UPTF) ←1 Grouping: Other operation Description: Sets (1) to the high-order bit reference enable flag UPTF. Note: When the table reference inst ruction (TABP p) is executed, the high-order 2 bits of ROM reference data is transferred to the low-order 2 bits of register D. SZB j (Skip if Zero, Bit) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 00001000 j j 2 02 j 16 11- (Mj(DP)) = 0 j = 0 to 3 Opera- tion: (Mj(DP)) = 0 ? j = 0 to 3 Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”. SZC (Skip if Zero, Carry flag) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101111 2 02F 16 11- ( C Y ) = 0 Opera- tion: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0”. After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is “1”. SZD (Skip if Zero, port D specified by register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000100100 2 024 16 2 2 - (D(Y)) = 0 0000101011 2 02B 16 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when the bit is “1”. Note: (Y) = 0 to 4. Do not execute this instruction if values except above are set to register Y. Opera- tion: (D(Y)) = 0 ? (Y) = 0 to 4

Rev.1.02 May 25, 2007 Page 87 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110000 2 230 16 11- - Opera- tion: (T17−T14) ← (B) (R17−R14) ← (B) (T13−T10) ← (A) (R13−R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110001 2 231 16 11- - Opera- tion: (T27−T24) ← (B) (R27−R24) ← (B) (T23−T20) ← (A) (R23−R20) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.T3AB (Transfer data to timer 3 and register R3L from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110010 2 232 16 11- - Opera- tion: (T37−T34) ← (B) (R3L7−R3L4) ← (B) (T33−T30) ← (A) (R3L3−R3L0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3L. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3L. T3HAB (Transfer data to register R3H from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000111101 2 23D 16 11- - Opera- tion: (R3H7−R3H4) ← (B) (R3H3−R3H0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3H. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3H.

Rev.1.02 May 25, 2007 Page 88 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T3R3L (Transfer data to timer 3 from register R3L) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110100 2 234 16 11- - Opera- tion: (T37−T30) ← (R3L7−R3L0) Grouping: Timer operation Description: Transfers the contents of reload register R3L to timer 3. TAB (Transfer data to Accumulator from register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011110 2 01E 16 11- - Opera- tion: (A) ← (B) Grouping: Register to register transfer Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110000 2 270 16 11- - Opera- tion: (B) ← (T17−T14) (A) ← (T13−T10) Grouping: Timer operation Description: Transfers the high-order 4 bits (T17−T14) of timer 1 to reg- ister B. Transfers the low-order 4 bits (T13−T10) of timer 1 to regis- ter A. TAB2 (Transfer data to Accumulator and register B from timer 2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110001 2 271 16 11- - Opera- tion: (B) ← (T27−T24) (A) ← (T23−T20) Grouping: Timer operation Description: Transfers the high-order 4 bits (T27−T24) of timer 2 to reg- ister B. Transfers the low-order 4 bits (T2 3−T20) of timer 2 to regis- ter A.

Rev.1.02 May 25, 2007 Page 89 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB3 (Transfer data to Accumulator and register B from timer 3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110010 2 272 16 11- - Opera- tion: (B) ← (T37−T34) (A) ← (T33−T30) Grouping: Timer operation Description: Transfers the high-order 4 bits (T37−T34) of timer 3 to reg- ister B. Transfers the low-order 4 bits (T3 3−T30) of timer 3 to regis- ter A. TABE (Transfer data to Accumulator and register B from register E) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101010 2 02A 16 11- - Opera- tion: (B) ← (E7−E4) (A) ← (E3−E0) Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7−E4) of register E to reg- ister B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0010 p 5 p4 p3 p2 p1 p0 2 0 8 +p p 16 13- - Opera- tion: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7−4 (A) ← (ROM(PC))3−0 (UPTF) ← 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low- order 2 bits (DR 1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. Note: M34571G4 : p = 0 to 31 M34571G6 : p = 0 to 47 M34571GD : p = 0 to 127 When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABPS (Transfer data to Accumulator and register B from Prescaler) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001110101 2 275 16 11- - Opera- tion: (B) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) Grouping: Timer operation Description: Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A.

Rev.1.02 May 25, 2007 Page 90 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAD (Transfer data to Accumulator from register D) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010001 2 051 16 11- - Opera- tion: (A2−A0) ← (DR2−DR0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAI1 (Transfer data to Accumulator from register I1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010011 2 253 16 11- - Opera- tion: (A) ← (I1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A. TAI2 (Transfer data to Accumulator from register I2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010100 2 254 16 11- - Opera- tion: (A) ← (I2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I2 to register A. TAK0 (Transfer data to Accumulator from register K0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010110 2 256 16 11- - Opera- tion: (A) ← (K0) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A.

Rev.1.02 May 25, 2007 Page 91 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK1 (Transfer data to Accumulator from register K1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011001 2 259 16 11- - Opera- tion: (A) ← (K1) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A. TAK2 (Transfer data to Accumulator from register K2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011010 2 25A 16 11- - Opera- tion: (A) ← (K2) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TAL1 (Transfer data to Accumulator from register L1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001010 2 24A 16 11- - Opera- tion: (A) ← (L1) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register L1 to register A. TAM j (Transfer data to Accumulator from Memory) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101100 j j j j 2 2C j 16 11- - Opera- tion: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.

Rev.1.02 May 25, 2007 Page 92 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010010 2 252 16 11- - Opera- tion: (A) ← (MR) Grouping: Clock operation Description: Transfers the contents of clock control register MR to reg- ister A. TAPU0 (Transfer data to Accumulator from register PU0) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001010111 2 257 16 11- - Opera- tion: (A) ← (PU0) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A. TAPU1 (Transfer data to Accumulator from register PU1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011110 2 25E 16 11- - Opera- tion: (A) ← (PU1) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. TAPU2 (Transfer data to Accumulator from register PU2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001011111 2 25F 16 11- - Opera- tion: (A) ← (PU2) Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU2 to register A.

Rev.1.02 May 25, 2007 Page 93 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TASP (Transfer data to Accumulator from Stack Pointer) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010000 2 050 16 11- - Opera- tion: (A2−A0) ← (SP2−SP0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low- order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010100 2 054 16 11- - Opera- tion: (A) ← (V1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A. TAV2 (Transfer data to Accumulator from register V2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010101 2 055 16 11- - Opera- tion: (A) ← (V2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A. TAW1 (Transfer data to Accumulator from register W1) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001011 2 24B 16 11- - Opera- tion: (A) ← (W1) Grouping: Timer operation Description: Transfers the contents of timer control register W1 to regis- ter A.

Rev.1.02 May 25, 2007 Page 94 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW2 (Transfer data to Accumulator from register W2) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001100 2 24C 16 11- - Opera- tion: (A) ← (W2) Grouping: Timer operation Description: Transfers the contents of timer control register W2 to regis- ter A. TAW3 (Transfer data to Accumulator from register W3) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001101 2 24D 16 11- - Opera- tion: (A) ← (W3) Grouping: Timer operation Description: Transfers the contents of timer control register W3 to regis- ter A. TAW5 (Transfer data to Accumulator from register W5) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1001001111 2 24F 16 11- - Opera- tion: (A) ← (W5) Grouping: Timer operation Description: Transfers the contents of timer control register W5 to regis- ter A. TAX (Transfer data to Accumulator from register X) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010010 2 052 16 11- - Opera- tion: (A) ← (X) Grouping: Register to register transfer Description: Transfers the contents of register X to register A.

Rev.1.02 May 25, 2007 Page 95 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAY (Transfer data to Accumulator from register Y) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011111 2 01F 16 11- - Opera- tion: (A) ← (Y) Grouping: Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0001010011 2 053 16 11- - Opera- tion: (A3, A2) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. TBA (Transfer data to register B from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001110 2 00E 16 11- - Opera- tion: (B) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register B. TDA (Transfer data to register D from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000101001 2 029 16 11- - Opera- tion: (DR2−DR0) ← (A2−A0) Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D.

Rev.1.02 May 25, 2007 Page 96 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000011010 2 01A 16 11- - Opera- tion: (E7−E4) ← (B) (E3−E0) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. TFR0A (Transfer data to register FR0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101000 2 228 16 11- - Opera- tion: (FR0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR0. TFR1A (Transfer data to register FR1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101001 2 229 16 11- - Opera- tion: (FR1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to port output structure control register FR1. TI1A (Transfer data to register I1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010111 2 217 16 11- - Opera- tion: (I1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister I1.

Rev.1.02 May 25, 2007 Page 97 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TI2A (Transfer data to register I2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000011000 2 218 16 11- - Opera- tion: (I2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister I2. TK0A (Transfer data to register K0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000011011 2 21B 16 11- - Opera- tion: (K0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K0. TK1A (Transfer data to register K1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010100 2 214 16 11- - Opera- tion: (K1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K1. TK2A (Transfer data to register K2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010101 2 215 16 11- - Opera- tion: (K2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register K2.

Rev.1.02 May 25, 2007 Page 98 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TL1A (Transfer data to register L1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001010 2 20A 16 11- - Opera- tion: (L1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup con- trol register L1. TMA j (Transfer data to Memory from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101011 j j j j 2 2B j 16 11- - Opera- tion: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TMRA (Transfer data to register MR from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010110 2 216 16 11- - Opera- tion: (MR) ← (A) Grouping: Clock operation Description: Transfers the contents of register A to clock control regis- ter MR. TPAA (Transfer data to register PA from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010101010 2 2AA 16 11- - Opera- tion: (PA0) ← (A0) Grouping: Timer operation Description: Transfers the least significant bit of register A (A0) to timer control register PA.

Rev.1.02 May 25, 2007 Page 99 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPSAB (Transfer data to Prescaler and register RPS from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000110101 2 235 16 11- - Opera- tion: (RPS7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of pres- caler and prescaler reload register RPS.TPU0A (Transfer data to register PU0 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101101 2 22D 16 11- - Opera- tion: (PU0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101110 2 22E 16 11- - Opera- tion: (PU1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU1. TPU2A (Transfer data to register PU2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000101111 2 22F 16 11- - Opera- tion: (PU2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control regis- ter PU2.

Rev.1.02 May 25, 2007 Page 100 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR1AB (Transfer data to register R1 from Accumulator and register B) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000111111 2 23F 16 11- - Opera- tion: (R17−R14) ← (B) (R13−R10) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents of regis- ter A to the low-order 4 bits (R13−R10) of reload register R1. TV1A (Transfer data to register V1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111111 2 03F 16 11- - Opera- tion: (V1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister V1. TV2A (Transfer data to register V2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000111110 2 03E 16 11- - Opera- tion: (V2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control reg- ister V2. TW1A (Transfer data to register W1 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001110 2 20E 16 11- - Opera- tion: (W1) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1.

Rev.1.02 May 25, 2007 Page 101 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW2A (Transfer data to register W2 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000001111 2 20F 16 11- - Opera- tion: (W2) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2. TW3A (Transfer data to register W3 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010000 2 210 16 11- - Opera- tion: (W3) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3. TW5A (Transfer data to register W5 from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1000010010 2 212 16 11- - Opera- tion: (W5) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W5. TYA (Transfer data to register Y from Accumulator) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 0000001100 2 00C 16 11- - Opera- tion: (Y) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register Y.

Rev.1.02 May 25, 2007 Page 102 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) WRST (Watchdog timer ReSeT) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 1010100000 2 2A0 16 11- ( W D F 1 ) = 1 Opera- tion: (WDF1) = 1 ? (WDF1) ← 0 Grouping: Other operation Description: Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. XAM j (eXchange Accumulator and Memory data) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101101 j j j j 2 2D j 16 11- - Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101111 j j j j 2 2F j 16 11- ( Y ) = 1 5 Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) −1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruc- tion code D9 D0 Number of words Number of cycles Flag CY Skip condition 101110 j j j j 2 2E j 16 11- ( Y ) = 0 Opera- tion: (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.

Rev.1.02 May 25, 2007 Page 103 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY TYPES) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Register to register transfer T A B 000001111001E 1 1( A ) ← (B) T B A 000000111000E 1 1( B ) ← (A) T A Y 000001111101F 1 1( A ) ← (Y) T Y A 000000110000C 1 1( Y ) ← (A) T E A B 000001101001A 1 1( E 7−E4) ← (B) (E3−E0) ← (A) T A B E 000010101002A 1 1( B ) ← (E7−E4) (A) ← (E3−E0) T D A 0000101001029 1 1( D R 2−DR0) ← (A2−A0) T A D 0001010001051 1 1( A 2−A0) ← (DR2−DR0) (A3) ← 0 T A Z 0001010011053 1 1( A 1, A0) ← (Z1, Z0) (A3, A2) ← 0 T A X 0001010010052 1 1( A ) ← (X) T A S P 0001010000050 1 1( A 2−A0) ← (SP2−SP0) (A3) ← 0 RAM addresses LXY x, y 1 1 x 3 x2 x1 x0 y3 y2 y1 y0 3xy 1 1( X ) ← x x = 0 to 15 (Y) ← y y = 0 to 15 L Z z 00010010 z 1 z0 048 1 1 (Z) ← z z = 0 to 3 I N Y 0000010011013 1 1( Y ) ← (Y) + 1 D E Y 0000010111017 1 1( Y ) ← (Y) − 1 RAM to register transfer T A M j 101100 j j j j 2Cj 1 1( A ) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 X A M j 101101 j j j j 2Dj 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 X A M D j 101111 j j j j 2F j 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) − 1 X A M I j 101110 j j j j 2Ej 1 1( A ) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 T M A j 101011 j j j j 2Bj 1 1( M ( D P ) ) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 104 of 124 REJ03B0179-0102 −− Transfers the contents of register B to register A. −− Transfers the contents of register A to register B. −− Transfers the contents of register Y to register A. −− Transfers the contents of register A to register Y . −− Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register A to the low-order 4 bits (E3−E0) of register E. −− Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register −− Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D. −− Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. −− Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. −− Transfers the contents of register X to register A. −− Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2−A0) of register A. “0” is stored to the bit 3 (A3) of register A. Continuous − Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. −− Loads the value z in the immediate field to register Z. (Y) = 0 − Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. (Y) = 15 − Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. −− After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. −− After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 − After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. (Y) = 0 − After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. −− After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.

Rev.1.02 May 25, 2007 Page 105 of 124 REJ03B0179-0102 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Arithmetic operation L A n 000111nnnn07n 1 1( A ) ← n n = 0 to 15 TABP p 0010 p 5 p4 p3 p2 p1 p0 08 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) (B) ← (ROM(PC))7-4 (A) ← (ROM(PC))3-0 (UPTF) = 1 (DR1, DR0) ← (ROM(PC))9, 8 (DR2) ← 0 (PC) ← (SK(SP)) (SP) ← (SP) − 1 A M 000000101000A 1 1( A ) ← (A) + (M(DP)) (CY) ← Carry A n 000110nnnn06n 1 1( A ) ← (A) + n n = 0 to 15 A N D 0000011000018 1 1( A ) ← (A) AND (M(DP)) O R 0000011001019 1 1( A ) ← (A) OR (M(DP)) S C 0000000111007 1 1( C Y ) ← 1 R C 0000000110006 1 1( C Y ) ← 0 S Z C 000010111102F 1 1( C Y ) = 0 ? C M A 000001110001C 1 1( A ) ← (A) R A R 000001110101D 1 1 Bit operation S B j 00010111 j j 05C 1 1 (Mj(DP)) ← 1 j = 0 to 3 R B j 00010011 j j 04C 1 1 (Mj(DP)) ← 0 j = 0 to 3 S Z B j 00001000 j j 02 j 1 1( M j ( D P ) ) = 0 ? j = 0 to 3 Para meter Type of instructi ons CY A3A2A1A0

Rev.1.02 May 25, 2007 Page 106 of 124 REJ03B0179-0102 − Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. −− Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. −− Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. − 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Overflow = 0 − Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. −− Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. −− Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. − 1 Sets (1) to carry flag CY . − 0 Clears (0) to carry flag CY. (CY) = 0 − Skips the next instruction when the contents of carry flag CY is “0”. Executes the next instruction when the contents of carry flag CY is “1”. The contents of carry flag CY remains unchanged. −− Stores the one’s complement for register A’s contents in register A. − 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. −− Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). −− Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 − Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0”. Executes the next instruction when the contents of bit j of M(DP) is “1”.

Rev.1.02 May 25, 2007 Page 107 of 124 REJ03B0179-0102 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Comparison operation SEAM 0000100110026 1 1( A ) = ( M ( D P ) ) ? SEA n 0000100101025 2 2( A ) = n n = 0 to 15 000111nnnn07n Branch operation B a 011 a 6 a5 a4 a3 a2 a1 a0 18 a1 1 ( P C L) ← a6−a0 B L p , a 00111 p 4 p3 p2 p1 p0 0E p2 2 ( P C H) ←p (Note 1) (PCL) ← a6−a0 1p 6 p5 a6 a5 a4 a3 a2 a1 a0 2aa B L A p 0000010000 0 10 2 2( P C H) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0) 1p 6 p5 p4 00 p 3 p2 p1 p0 2pp Subroutine operation B M a 010 a 6 a5 a4 a3 a2 a1 a0 1aa 1 1( S P ) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6−a0 B M L p , a 00110 p 4 p3 p2 p1 p0 0C (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← a6−a01p 6 p5 a6 a5 a4 a3 a2 a1 a0 2aa B M L A p 0000110000 030 2 2( S P ) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note 1) (PCL) ← (DR2−DR0, A3−A0)1p 6 p5 p4 00 p 3 p2 p1 p0 2pp Return operation R T I 0001000110046 1 1( P C ) ← (SK(SP)) (SP) ← (SP) − 1 R T 0001000100044 1 2( P C ) ← (SK(SP)) (SP) ← (SP) − 1 R T S 0001000101045 1 2( P C ) ← (SK(SP)) (SP) ← (SP) − 1 Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 108 of 124 REJ03B0179-0102 (A) = (M(DP)) − Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). (A) = n n = 0 to 15 − Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. −− Branch within a page : Branches to address a in the identical page. −− Branch out of a page : Branches to address a in page p. −− Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. −− Call the subroutine in page 2 : Calls the subroutine at address a in page 2. −− Call the subroutine : Calls the subroutine at address a in page p. −− Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. −− Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. −− Returns from subroutine to the routine called the subroutine. No conditional skip − Returns from subroutine to the routine called the subroutine, and skips the next instruction at with no condition.

Rev.1.02 May 25, 2007 Page 109 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Interrupt operation D I 0000000100004 1 1( I N T E ) ← 0 E I 0000000101005 1 1( I N T E ) ← 1 S N Z 0 0 000111000038 1 1V 1 0 = 0 : (EXF0) = 1 ? (EXF0) ← 0 V10 = 1 : SNZ0 = NOP S N Z I 0 000011101003A 1 1I 1 2 = 0 : (INT0) = “L”? S N Z 1 0 000111001039 1 1V 1 1 = 0 : (EXF1) = 1 ? (EXF1) ← 0 V11 = 1 : SNZ1 = NOP S N Z I 1 000011101103B 1 1I 2 2 = 0 : (INT1) = “L” ? T A V 1 0001010100054 1 1( A ) ← (V1) T V 1 A 000011111103F 1 1( V 1 ) ← (A) T A V 2 0001010101055 1 1( A ) ← (V2) T V 2 A 000011111003E 1 1( V 2 ) ← (A) T A I 1 1001010011253 1 1( A ) ← (I1) T I 1 A 1000010111217 1 1( I 1 ) ← (A) T A I 2 1001010100254 1 1( A ) ← (I2) T I 2 A 1000011000218 1 1( I 2 ) ← (A) Timer operation T P A A 10101010102AA 1 1( P A 1, PA0) ← (A1, A0) T A W 1 100100101124B 1 1( A ) ← (W1) T W 1 A 100000111020E 1 1( W 1 ) ← (A) T A W 2 100100110024C 1 1( A ) ← (W2) T W 2 A 100000111120F 1 1( W 2 ) ← (A) T A W 3 100100110124D 1 1( A ) ← (W3) T W 3 A 1000010000210 1 1( W 3 ) ← (A) T A W 5 100100111124F 1 1( A ) ← (W5) T W 5 A 1000010010212 1 1( W 5 ) ← (A) Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 110 of 124 REJ03B0179-0102 −− Clears (0) to interrupt enable flag INTE, and disables the interrupt. −− Sets (1) to interrupt enable flag INTE, and enables the interrupt. V10 = 0 : (EXF0) = 1 − When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction. When V1 0 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) (INT0) = “L” However, I12 = 0 − When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L”. Executes the next instruction when the level of INT0 pin is “H”. (INT0) = “H” However, I12 = 1 When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H”. Executes the next instruction when the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1) V11 = 0 : (EXF1) = 1 − When V11 = 0 : Clears (0) to the EXF1 flag and skips the next instruction when external 1 interrupt request flag EXF1 is “1”. When the EXF1 flag is “0”, executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) I22 = 0 : (INT1) = “L” − When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L”. Executes the next instruction when the level of INT1 pin is “H”. I22 = 1 : (INT1) = “H” When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H”. Executes the next instruction when the level of INT1 pin is “L”. (I22: bit 2 of interrupt control register I2) −− Transfers the contents of interrupt control register V1 to register A. −− Transfers the contents of register A to interrupt control register V1. −− Transfers the contents of interrupt control register V2 to register A. −− Transfers the contents of register A to interrupt control register V2. −− Transfers the contents of interrupt control register I1 to register A. −− Transfers the contents of register A to interrupt control register I1. −− Transfers the contents of interrupt control register I2 to register A. −− Transfers the contents of register A to interrupt control register I2. −− Transfers the contents of register A (A1, A0) to timer control register PA. −− Transfers the contents of timer control register W1 to register A. −− Transfers the contents of register A to timer control register W1. −− Transfers the contents of timer control register W2 to register A. −− Transfers the contents of register A to timer control register W2. −− Transfers the contents of timer control register W3 to register A. −− Transfers the contents of register A to timer control register W3. −− Transfers the contents of timer control register W5 to register A. −− Transfers the contents of register A to timer control register W5.

Rev.1.02 May 25, 2007 Page 111 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Timer operation TABPS 1001110101275 1 1( B ) ← (TPS7−TPS4) (A) ← (TPS3−TPS0) TPSAB 1000110101235 1 1( R P S 7−RPS4) ← (B) (TPS7−TPS4) ← (B) (RPS3−RPS0) ← (A) (TPS3−TPS0) ← (A) T A B 1 1001110000270 1 1( B ) ← (T17−T14) (A) ← (T13−T10) T 1 A B 1000110000230 1 1( R 1 7−R14) ← (B) (T17−T14) ← (B) (R13−R10) ← (A) (T13−T10) ← (A) T R 1 A B 100011111123F 1 1( R 1 7−R14) ← (B) (R13−R10) ← (A) T A B 2 1001110001271 1 1( B ) ← (T27−T24) (A) ← (T23−T20) T 2 A B 1000110001231 1 1( R 2 7−R24) ← (B) (T27−T24) ← (B) (R23−R20) ← (A) (T23−T20) ← (A) T A B 3 1001110010272 1 1( B ) ← (T37−T34) (A) ← (T33−T30) T 3 A B 1000110010232 1 1( R 3 L 7−R3L4) ← (B) (T37−T34) ← (B) (R3L3−R3L0) ← (A) (T33−T30) ← (A) T 3 H A B 100011110123D 1 1( R 3 H 7−R3H4) ← (B) (R3H3−R3H0) ← (A) T 3 R 3 L 1000110100234 1 1( T 3 7) ← (R3L) S N Z T 1 1010000000280 1 1V 1 2 = 0 : (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1 : SNZT1=NOP S N Z T 2 1010000001281 1 1V 1 3 = 0 : (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1 : SNZT2=NOP S N Z T 3 1010000010282 1 1V 2 0 = 0 : (T3F) = 1 ? After skipping, (T3F) ← 0 V20 = 1 : SNZT3=NOP Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 112 of 124 REJ03B0179-0102 −− Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. −− Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. −− Transfers the high-order 4 bits (T17−T14) of timer 1 to register B. Transfers the low-order 4 bits (T13−T10) of timer 1 to register A. −− Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. −− Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13−R10) of reload register R1. −− Transfers the high-order 4 bits (T27−T24) of timer 2 to register B. Transfers the low-order 4 bits (T23−T20) of timer 2 to register A. −− Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L. −− Transfers the high-order 4 bits (T37−T34) of timer 3 to register B. Transfers the low-order 4 bits (T33−T30) of timer 3 to register A. −− Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3L. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3L. −− Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3H. Transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3H. −− Transfers the contents of timer 3 reload register R3L to timer 3. V12 = 0 : (T1F) = 1 − When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is “1”. When the T1F flag is “0”, executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) V13 = 0 : (T2F) = 1 − When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is “1”. When the T2F flag is “0”, executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) V20 = 0 : (T3F) = 1 − When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is “1”. When the T3F flag is “0”, executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2)

Rev.1.02 May 25, 2007 Page 113 of 124 REJ03B0179-0102 MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Input/Output operation I A P 0 1001100000260 1 1( A ) ← (P0) O P 0 A 1000100000220 1 1( P 0 ) ← (A) I A P 1 1001100001261 1 1( A ) ← (P1) O P 1 A 1000100001221 1 1( P 1 ) ← (A) I A P 2 1001100010262 1 1( A 1, A0) ← (P21, P20) (A3, A2) ← 0 O P 2 A 1000100010222 1 1( P 2 1, P20) ← (A1, A0) I A P 3 1001100011263 1 1( A 1, A0) ← (P31, P30) (A3, A2) ← 0 O P 3 A 1000100011223 1 1( P 3 1, P30) ← (A1, A0) C L D 0000010001011 1 1( D ) ← 1 R D 0000010100014 1 1( D ( Y ) ) ← 0 (Y) = 0 to 4 S D 0000010101015 1 1( D ( Y ) ) ← 1 (Y) = 0 to 4 S Z D 0000100100024 2 2( D ( Y ) ) = 0 ? (Y) = 0 to 4 000010101102B R C P 101000110028C 1 1( C ) ← (0) S C P 101000110128D 1 1( C ) ← (1) T F R 0 A 1000101000228 1 1( F R 0 ) ← (A) T F R 1 A 1000101001229 1 1( F R 1 ) ← (A) T A P U 0 1001010111257 1 1( A ) ← (PU0) T P U 0 A 100010110122D 1 1( P U 0 ) ← (A) T A P U 1 100101111025E 1 1( A ) ← (PU1) T P U 1 A 100010111022E 1 1( P U 1 ) ← (A) T A P U 2 100101111125F 1 1( A ) ← (PU2) T P U 2 A 100010111122F 1 1( P U 2 ) ← (A) I A K 100110111126F 1 1( A 0) ← (K) (A3−A1) ← 0 Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 114 of 124 REJ03B0179-0102 −− Transfers the input of port P0 to register A. −− Outputs the contents of register A to port P0. −− Transfers the input of port P1 to register A. −− Outputs the contents of register A to port P1. −− Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. −− Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. −− Transfers the input of port P3 to the low-order 2 bits (A1, A0) of register A. “0” is stored to the high-order 2 bits (A3, A2) of register A. −− Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P3. −− Sets (1) to port D. −− Clears (0) to a bit of port D specified by register Y . −− Sets (1) to a bit of port D specified by register Y . (D(Y)) = 0 Y = 0 to 4 − Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction when a bit of port D specified by register Y is “1”. −− Clears (0) to port C. −− Sets (1) to port C. −− Transfers the contents of register A to port output structure control register FR0. −− Transfers the contents of register A to port output structure control register FR1. −− Transfers the contents of pull-up control register PU0 to register A. −− Transfers the contents of register A to pull-up control register PU0. −− Transfers the contents of pull-up control register PU1 to register A. −− Transfers the contents of register A to pull-up control register PU1. −− Transfers the contents of pull-up control register PU2 to register A. −− Transfers the contents of register A to pull-up control register PU2. −− Transfers the input of port K to the least significant bit (A0) of register A. “0” is stored to the high-order 3 bits (A3−A1) of register A.

Rev.1.02 May 25, 2007 Page 115 of 124 REJ03B0179-0102 Note 1.This instruction cannot be used for the M34571G4/G6. MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Mnemonic Instruction code Number of words Number of cycles Function D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hexadecim al notation Input/Output operation T A K 0 1001010110256 1 1( A ) ← (K0) T K 0 A 100001101121B 1 1( K 0 ) ← (A) T A K 1 1001011001259 1 1( A ) ← (K1) T K 1 A 1000010100214 1 1( K 1 ) ← (A) T A K 2 100101101025A 1 1( A ) ← (K2) T K 2 A 1000010101215 1 1( K 2 ) ← (A) T A L 1 100100101024A 1 1( A ) ← (L1) T L 1 A 100000101020A 1 1( L 1 ) ← (A) Other operation T A M R 1001010010252 1 1( A ) ← (MR) T M R A 1000010110216 1 1( M R ) ← (A) N O P 0000000000000 1 1( P C ) ← (PC) + 1 P O F 0000000010002 1 1R A M b a c k - u p E P O F 000101101105B 1 1P O F i n s t r u c t i o n v a l i d S N Z P 0000000011003 1 1( P ) = 1 ? W R S T 10101000002A0 1 1( W D F 1 ) = 1 ? (WDF1) ← 0 D W D T 101001110029C 1 1S t o p o f w a t c hdog timer function enabled S R S T 0000000001001 1 1S y s t e m r e s e t R U P T 0001011000058 1 1( U P T F ) ← 0 S U P T 0001011001059 1 1( U P T F ) ← 1 S N Z V D 101000101028A 1 1V 2 3 = 0 : (VDF) = 1? V23 = 1 : SNZVD = NOP RBK (Note 1) 0001000000040 1 1p 6 ← 0 when TABP p instruction is executed. SBK (Note 1) 0001000001041 1 1p 6 ← 1 when TABP p instruction is executed. Para meter Type of instructi ons

Rev.1.02 May 25, 2007 Page 116 of 124 REJ03B0179-0102 −− Transfers the contents of key-on wakeup control register K0 to register A. −− Transfers the contents of register A to key-on wakeup control register K0. −− Transfers the contents of key-on wakeup control register K1 to register A. −− Transfers the contents of register A to key-on wakeup control register K1. −− Transfers the contents of key-on wakeup control register K2 to register A. −− Transfers the contents of register A to key-on wakeup control register K2. −− Transfers the contents of key-on wakeup control register L1 to register A. −− Transfers the contents of register A to key-on wakeup control register L1. −− Transfers the contents of clock control register MR to register A. −− Transfers the contents of register A to clock control register MR. −− No operation; Adds 1 to program counter value, and others remain unchanged. −− Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Operations of all functions are stopped. −− Makes the immediate after POF instruction valid by executing the EPOF instruction. (P) = 1 − Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0”. (WDF1) = 1 Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. −− Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. −− System reset occurs. −− Clears (0) to the high-order bit reference enable flag UPTF. −− Sets (1) to the high-order bit reference enable flag UPTF. V23 = 0 : (VDF) = 1 − When V23 = 0 : Skips the next instruction when voltage detector interrupt request flag VDF is “1”. The VDF flag is not cleared to “0“. When the VDF flag is “0”, executes the next instruction. When V23 = 1 : This instruction is equivalent to the NOP instruction. −− Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. −− Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction.

Rev.1.02 May 25, 2007 Page 117 of 124 REJ03B0179-0102 The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is al so provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

• *, , and * cannot be used in the M34571G4.
• and * cannot be used in the M34571G6.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the M34571GD. The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63. The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 127 (Ex. TABP 0 TABP 64). When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63. INSTRUCTION CODE TABLE D9− 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 00 1111 010000 to 010111 011000 to 011111 D3− Hex, notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 −17 18 −F 0000 0 NOP BLA SZB

0 BMLA RBK

*** TASP A LA TABP TABP TABP 32* TABP 48 BML BML BL BL BM B 0001 1 SRST CLD SZB 1 − SBK * TAD A LA TABP TABP TABP 33* TABP 49** BML BML BL BL BM B 0010 2 POF − SZB 2 −− TAX A LA TABP TABP TABP 34* TABP 50** BML BML BL BL BM B 0011 3 SNZP INY SZB 3 −− TAZ A LA TABP TABP TABP 35* TABP 51** BML BML BL BL BM B 0100 4 DI RD SZD − RT TAV1 A LA TABP TABP TABP 36* TABP 52** BML BML BL BL BM B 0101 5 EI SD SEAn − RTS TAV2 A LA TABP TABP TABP 37* TABP 53** BML BML BL BL BM B 0110 6 RC − SEAM − RTI − A LA TABP TABP TABP 38* TABP 54** BML BML BL BL BM B 0111 7 SC DEY −−−− A LA TABP TABP TABP 39* TABP 55** BML BML BL BL BM B 1000 8 − AND − SNZ0 LZ

0 RUPT A

40* TABP 56** BML BML BL BL BM B 1001 9 − OR TDA SNZ1 LZ

1 SUPT A

41* TABP 57** BML BML BL BL BM B

1010 A AM TEAB TABE SNZI

2 − A LA TABP TABP TABP 42* TABP 58** BML BML BL BL BM B

1011 B AMC −− SNZI

3 EPOF A

43* TABP 59** BML BML BL BL BM B

1100 C TYA CMA −− RB

A LA TABP TABP TABP 44* TABP 60** BML BML BL BL BM B

1101 D − RAR −− RB

A LA TABP TABP TABP 45* TABP 61** BML BML BL BL BM B

1110 E TBA TAB − TV2A RB

A LA TABP TABP TABP 46* TABP 62** BML BML BL BL BM B

1111 F − TAY SZC TV1A RB

A LA TABP TABP TABP 47* TABP 63** BML BML BL BL BM B The second word BL 10 0aaa aaaa BML 10 0aaa aaaa BLA 10 0p00 pppp BMLA 10 0p00 pppp SEA 00 0111 nnnn SZD 00 0010 1011

Rev.1.02 May 25, 2007 Page 118 of 124 REJ03B0179-0102 The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D 9– D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is al so provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. INSTRUCTION CODE TABLE D9− 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 10 1111 110000 to 111111 D3− Hex, notation 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 −3F 0000 0 − TW3A OP0A T1AB −− IAP0 TAB1 SNZT 1 − WRST TMA TAM XAM XAMI XAMD

0 LXY

0001 1 −− OP1A T2AB −− IAP1 TAB2 SNZT 2 −− TMA TAM XAM XAMI XAMD

1 LXY

0010 2 − TW5A OP2A T3AB − TAMR IAP2 TAB3 SNZT 3 −− TMA TAM XAM XAMI XAMD

2 LXY

3 LXY

4 LXY

5 LXY

6 LXY

7 LXY

8 LXY

9 LXY

1010 A TL1A −−− TAL1 TAK2 −− SNZVD − TPAA TMA

10 LXY

11 LXY

12 LXY

1101 D −− TPU0A T3HAB TAW3 −−− SCP −− TMA

13 LXY

14 LXY

1111 F TW2A − TPU2A TR1AB TAW5 TAPU2 IAK −−−− TMA

15 LXY

Rev.1.02 May 25, 2007 Page 119 of 124 REJ03B0179-0102

Electrical characteristics

Table 25 Absolute maximum ratings Symbol Parameter Conditions Ratings Unit VDD Supply voltage - −0.3 to 6.5 V VI Input voltage P0, P1, P20/INT0, P21/INT1, P3, D0–D3, D4/CNTR0, K, RESET, XIN - −0.3 to VDD+0.3 V VO Output voltage P0, P1, P2, P3, D0–D3, D4/CNTR0, RESET Output transistors in cut-off state −0.3 to VDD+0.3 V VO Output voltage C, XOUT - −0.3 to VDD+0.3 V Pd Power dissipation Ta = 25 °C 300 mW Topr Operating temperature range - −20 to 85 °C Tstg Storage temperature range - −40 to 125 °C

Rev.1.02 May 25, 2007 Page 120 of 124 REJ03B0179-0102 Recommended operating conditions Note 1.The average output current is the average value during 100ms. Table 26 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Limits UnitMin. Typ. Max. VDD Supply voltage (with a ceramic resonator) f(STCK) ≤ 6MHz 4 5.5 V f(STCK) ≤ 4.4MHz 2.7 5.5 f(STCK) ≤ 2.2MHz 2 5.5 f(STCK) ≤ 1.1MHz 1.8 5.5 VDD Supply voltage (when an external clock is used) f(STCK) ≤ 4.8MHz 4 5.5 V f(STCK) ≤ 3.2MHz 2.7 5.5 f(STCK) ≤ 1.6MHz 2 5.5 f(STCK) ≤ 0.8MHz 1.8 5.5 VRAM RAM back-up voltage (at RAM back-up) 1.6 5.5 V VSS Supply voltage 0V VIH “H” level input voltage P0, P1, P2, P3, D 0–D4, K 0.8V DD VDD V XIN 0.7VDD VDD RESET, INT0, INT1 0.85VDD VDD CNTR0 0.85V DD VDD VIL “L” level input voltage P0, P1, P2, P3, D 0–D4, K 0 0.3V DD mA XIN 00 . 3 V DD RESET, INT0, INT1 00 . 3 V DD CNTR0 0 0.15V DD IOH(peak) “H” level peak output current P3, D 0–D3 VDD = 5V −20 mA VDD = 3V −10 C, CNTR1 V DD = 5V −30 VDD = 3V −15 IOH(avg) “H” level average output current (Note 1) P3, D0–D3 VDD = 5V −10 mA VDD = 3V −5 C, CNTR1 V DD = 5V −15 VDD = 3V −7 IOL(peak) “L” level peak output current P0, P1, P2, P3, D0–D4, C, RESET, CNTR0, CNTR1, VDD = 5V 24 mA VDD = 3V 12 IOL(avg) “L” level average output current (Note 1) P0, P1, P2, P3, D0–D4, C, RESET, CNTR0, CNTR1, VDD = 5V 12 mA VDD = 3V 6 ΣIOH(avg) “H” level total average current P3, D 0–D3, C, CNTR1 −30 mA ΣIOL(avg) “L” level total average current P0, P10, P11, RESET 30 mA P10, P11, P2, P3, D0–D4, C, CNTR0, CNTR1 30

Rev.1.02 May 25, 2007 Page 121 of 124 REJ03B0179-0102 Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Fig 71. System clock (STCK) operating condition map Table 27 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Conditions Limits UnitMin. Typ. Max. f(XIN) Oscillation frequency (with a ceramic resonator) Through mode V DD = 4.0 V to 5.5 V 6 MHz VDD = 2.7 V to 5.5 V 4.4 VDD = 2.0 V to 5.5 V 2.2 VDD = 1.8 V to 5.5 V 1.1 Internal frequency divided by 2 VDD = 2.7 V to 5.5 V 6 VDD = 2.0 V to 5.5 V 4.4 VDD = 1.8 V to 5.5 V 2.2 Internal frequency divided by 4, 8 VDD = 2.0 V to 5.5 V 6 VDD = 1.8 V to 5.5 V 4.4 f(XIN) Oscillation frequency (with an external clock input) Through mode V DD = 4.0 V to 5.5 V 4.8 MHz VDD = 2.7 V to 5.5 V 3.2 VDD = 2.0 V to 5.5 V 1.6 VDD = 1.8 V to 5.5 V 0.8 Internal frequency divided by 2 VDD = 2.7 V to 5.5 V 4.8 VDD = 2.0 V to 5.5 V 3.2 VDD = 1.8 V to 5.5 V 1.6 Internal frequency divided by 4, 8 VDD = 2.0 V to 5.5 V 4.8 VDD = 1.8 V to 5.5 V 3.2 f(CNTR) Timer external input frequency CNTR0, CNTR1 f(STCK)/6 Hz tw(CNTR) Timer external input period (“H” and “L” pulse width) CNTR0, CNTR1 3/f(STCK) s T PON Power-on reset circuit valid supply voltage rising time (Note 1) V DD = 0 → 1.8V 100 µs 1.1 2.2 4.4 1.8 2 2.7 4 5.5 Recommended operating conditions with a ceramic resonator f(STCK) [MHz] VDD [V] 0.8 1.6 3.2 4.8 1.8 2 2.7 4 5.5 Recommended operating conditions at external clock oscillation f(STCK) [MHz] VDD [V]

Rev.1.02 May 25, 2007 Page 122 of 124 REJ03B0179-0102 Note 1.The voltage drop detection circuit operation current (IRST) is added. Table 28 Electrical charac teristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol Parameter Test conditions Limits UnitMin. Typ. Max. VOH “H” level output voltage P3, D 0–D4 VDD = 5V I OH = −10mA 3 V CNTR0 I OH = −3mA 4.1 VDD = 3V I OH = −5mA 2.1 IOH = −1mA 2.4 VOH “H” level output voltage C CNTR1 VDD = 5V I OL = −20mA 3 V IOL = −6mA 4.1 VDD = 3V I OL =−10mA 2.1 IOL = −3mA 2.4 VOL “L” level output voltage P0, P1, P2, P3, D 0–D4 RESET, C, CNTR0, CNTR1 VDD = 5V I OL = 15mA 2 V IOL = 5mA 0.9 VDD = 3V I OL = 9mA 1.4 IOL = 3mA 0.9 IIH “H” level input current P0, P1, P2, P3, D 0–D4, K RESET, INT0, INT1 CNTR0 VI = VDD 2 µA IIL “L” level input current P0, P1, P2, P3, D 0–D4, K RESET, INT0, INT1 CNTR0 VI = 0V P0, P1, P2 No pull-up −2 µA RPU Pull-up resistor value P0, P1, P2 RESET VI = 0V V DD = 5V 30 60 125 k Ω VDD = 3V 50 120 250 VT+ −VT− Hysteresis RESET, INT0, INT1 V DD = 5V 1 V VDD = 3V 0.4 VT+ −VT− Hysteresis CNTR0 V DD = 5V 0.2 V VDD = 3V 0.2 IDD Supply current at active mode (with a ceramic resonator) (Note 1) VDD = 5V f(XIN) = 6MHz f(RING) = stop f(STCK) = f(XIN)/8 1.2 2.4 mA f(STCK) = f(XIN)/4 1.3 2.6 f(STCK) = f(XIN)/2 1.6 3.2 f(STCK) = f(XIN)2 . 2 4 . 4 VDD = 3V f(XIN) = 4MHz f(RING) = stop f(STCK) = f(XIN)/8 0.3 0.6 mA f(STCK) = f(XIN)/4 0.4 0.8 f(STCK) = f(XIN)/2 0.6 1.2 f(STCK) = f(XIN)0 . 8 1 . 6 at RAM back-up mode (POF instruction execution) Ta = 25°C0 . 1 3 µA VDD = 5V 10 VDD = 3V 6

Rev.1.02 May 25, 2007 Page 123 of 124 REJ03B0179-0102 Voltage drop detection circuit characteristics Note 1.The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. Note 2.The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. Note 3.When the supply voltage goes lower than the detection voltage (V INT), the voltage drop detection circuit interrupt request flag (VDF) is set to “1“. Note 4.IRST is added to IDD (power current). Note 5.The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V]. Basic timing diagram Table 29 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Limits UnitMin. Typ. Max. VRST- Detection voltage (reset occurs) (Note 1) Ta = 25°C1 . 6 5 V 0°C≤ Ta < 50°C1 . 3 2 . 1 50°C≤ Ta ≤ 85°C1 . 1 1 . 8 VRST+ Detection voltage (reset release) (Note 2) Ta = 25°C1 . 7 5 V 0°C≤ Ta < 50°C1 . 4 2 . 2 50°C≤ Ta ≤ 85°C1 . 2 1 . 9 VINT Detection voltage (Interrupt occurs) (Note 3) Ta = 25°C1 . 8 5 V 0°C≤ Ta < 50°C1 . 5 2 . 3 50°C≤ Ta ≤ 85°C1 . 3 2 . 2 VRST+ −VRST- Detection voltage hysteresis 0.1 V IRST Voltage drop detection circuit operation current (Note 4) VDD = 5V 40 80 µA VDD = 3V 20 40 VDD = 1.65V 7 15 TRST Detection time (Note 5) V DD → (VRST- −0.1V) 0.2 1.2 ms System clock STCK Port output D 0 to D4 P00 to P03 P10 to P13 P20,P 21 P30,P 31,C Port input D 0 to D4 P00 to P03 P10 to P13 P20,P 21 P30,P 31,K Interrupt input INT0, INT1 Parameter Pin name Machine cycle Mi Mi + 1

Rev.1.02 May 25, 2007 Page 124 of 124 REJ03B0179-0102 PACKAGE OUTLINE F 1 12 1324 Index mark y E HE e bp D A c Detail F A1A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. A1 0 0.1 0.2 Previous CodeJEITA Package Code RENESAS Code PRSP0024GA-A 24P2Q-A MASS[Typ.] 0.2gP-SSOP24-5.3x10.1-0.80 0.250.20.18 0.450.350.3 MaxNomMin Dimension in Millimeters Symbol Reference 10.210.110.0D 5.45.35.2E 1.8A2 8.17.87.5 2.1A 0.80.60.4L 8°0° c 0.8e 0.10y HE bp 0.65 0.95

(1/1) REVISION HISTORY 4571 Group Datasheet Rev. Date Description Page Summary 1.00 Feb. 20, 2006 − First edition issued 1.01 Apr. 18, 2007 1 FEATURES: Description revised

4 Table 2: Subroutine nesting added

6 Table 5: Port P2; P2 0 → P20/INT0, P21 → P21/INT1

30 Table 17: Timer control register W1; CNTR1 input → CNTR0 input

31 • Timer control register PA: Description revised

• Timer control register W3: Description revised (2) Prescaler: PRS → RPS 32 (5) Timer 3: Description revised

37 WATCHDOG TIMER: Description revised

47 Table 21: Title revised

48 Table 22: Title revised

49 Fig 50: Ceramic resonator circuit → Ceramic oscillation circuit

51 QzROM Writing Mode added

59 NOTES ON NOISE added

64 Timer control register W1: CNTR1 input → CNTR0 input

69 SNZ1: V1

0 → V11

86 SUPT: Description revised

112 T3HAB: Description revised

122 Table 28: I DD; (with a ceramic oscillator) → (with a ceramic resonator)

1.02 May. 25, 2007 All pages “PRELIMINARY” deleted

REVISION HISTORY

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