4570

4570 RENESAS

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The 4570 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with a carrier wave output circuit for remote control, an 8-bit timer with a reload register, a 10-bit timer with a reload register, and an 8-bit timer with two reload registers. The various microcomputers in the 4570 Group include variations of the built-in memory size. The mask ROM version and One Time PROM version of 4570 Group are produced as shown in the table below.

FEATURES

l Minimum instruction execution time (f(XIN)=2.0 MHz, VDD =4.5 V to 5.5 V) (f(XIN)=4.2 MHz, VDD =2.0 V to 5.5 V) l Supply voltage l System clock switch function l Timers Timer 1... 10-bit timer with a reload register and carrier wave output auto-control function Timer 3... 8-bit timer with two reload registers and carrier wave generation function l Power-on reset circuit l Key-on wakeup function (Ports P0, P1, and P4, ON/OFF of port P4 can be switched) port P4 can be switched) l Voltage drop detection circuit l Clock generating circuit (ceramic resonance) APPLICATION Remote control transmitter Outline 36P2R-A PIN CONFIGURATION (TOP VIEW) M34570Mx-XXXFP Product M34570M4-XXXFP M34570M8-XXXFP M34570MD-XXXFP M34570E8FP M34570EDFP * *: Under development (Jan. 1999) ROM type Mask ROM Mask ROM Mask ROM One Time PROM One Time PROM Package 36P2R-A 36P2R-A 36P2R-A 36P2R-A 36P2R-A RAM size (5 4 bits) 128 words 128 words 128 words 128 words 128 words ROM (PROM) size (5 10 bits) 4096 words 8192 words 16384 words 8192 words 16384 words D 1 P40 P41 P42 P43 CNV SS P13 P12 P02 P10 RESET VDD XOUT XIN VSS D 0 P01 P00 P20 P11 P03 P21/INT CARR P32 P31 P30 VDCE M34570Mx-XXXFP D 3 D 5 D 4 D 7 D 6 D 8 D 9/TOUT D 2 P33

4570 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BLOCK DIAGRAM RAM 128 words 5 4 bits ROM (Note) 4096 to 16384 words 5 10 bits Port P0 Port P1

4500 Series

Internal peripheral functions Timers/Carrier wave generation Timer 1 (10 bits) Clock generating circuit Timer 2 (8 bits) XIN –XOUT Watchdog timer (16 bits) Register B (4 bits)Register A (4 bits) Register D (3 bits)Register E (8 bits) Stack registers SKs (8 levels) Interrupt stack register SDP(1 level) ALU(4 bits) Port DPort P2 10244 Timer 3 (8 bits) Note: PROM 16384 words 5 10 bits for the built-in PROM version. Port P3 Port P4 (Carrier wave generation) Reset (Voltage drop detection circuit)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PERFORMANCE OVERVIEW Function 1.5 µs (f(XIN) = 2.0 MHz:system clock = f(XIN): VDD = 5.0 V) 2.86 µs (f(XIN) = 4.2 MHz:system clock = f(XIN)/4: VDD = 5.0 V) 4096 words 5 10 bits 8192 words 5 10 bits 16384 words 5 10 bits 8192 words 5 10 bits 16384 words 5 10 bits 128 words 5 4 bits Ten independent output ports; port D9 is also used as the TOUT output pin. 4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function. 4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function. 2-bit input port, port P21 is also used as INT input pin. 4-bit I/O port 4-bit input port; both pull-up function and key-on wakeup function can be switched by software. 1-bit output port (CMOS output) 1-bit output pin; T OUT output pin is also used as port D9. 1-bit input pin with a key-on wakeup function. INT input pin is also used as port P21. 10-bit timer with a reload register and carrier wave output auto-control function 8-bit timer with a reload register 8-bit timer with two reload registers and carrier wave generation function 4 (one for external and three for timer) 1 level 8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction is executed) CMOS silicon gate 36-pin plastic molded SSOP –20 °C to 70 °C 2.0 V to 5.5 V for mask ROM version (2.5 V to 5.5 V for One Time PROM version) 1.3 mA (f(X IN) = 4.2 MHz: system clock = f(XIN)/4, VDD =5.0 V) 0.5 mA (f(XIN) = 1.0 MHz: system clock = f(XIN), VDD =3.0 V) 0.1 µA (Ta=25 °C, VDD =5V, typical value) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 9 P00–P03 P10–P13 P20, P21 P30–P33 P40–P43 CARR T OUT INT Timer 1 Timer 2 Timer 3 Sources Nesting at active at RAM back-up M34570M4 M34570M8 M34570MD M34570E8 M34570ED Output I/O I/O Input I/O Input Output Output Input DEFINITION OF CLOCK AND CYCLE l System clock The system clock is the basic clock for controlling this product. The system clock can be selected by bit 3 of the clock control register MR as shown in the table below. Table Selection of system clock l Instruction clock The instruction clock is the standard clock for controlling CPU. The instruction clock is a signal derived from dividing the system clock by 3. The one cycle of the instruction clock is equivalent to the one machine cycle. l Machine cycle The machine cycle is the standard cycle required to execute the instruction. System clock f(X IN) f(XIN)/4 MR 3 Note: f(XIN)/4 is selected immediately after system is released from reset.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Name Power supply Ground CNV SS Reset input Clock input Clock output Output port D I/O port P0 I/O port P1 Input port P2 I/O port P3 Input port P4 Carrier wave output for remote control Interrupt input Timer output Voltage drop detection circuit enable Input/Output Input I/O Input Output Output I/O I/O I/O I/O Input Output Input Output Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. A pull-up transistor and a capacitor are built-in this pin. When the watchdog timer causes the system to be reset or the low-supply voltage is detected, the RESET pin outputs “L” level. I/O pins of the clock generating circuit. Connect a ceramic resonator between XIN pin and XOUT pin. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide output function. Port D9 is also used as TOUT output pin. The output structure is N-channel open-drain. 4-bit I/O port. It can be used as an input port when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. 4-bit I/O port. It can be used as an input port when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. 2-bit input port. Port P2 1 is also used as the INT input pin. 4-bit I/O port. It can be used as an input port when the output latch is set to “1.” The output structure is N-channel open-drain. 4-bit input port. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Carrier wave output pin for remote control transmit. The output structure is the CMOS circuit. INT input pin accepts an external interrupt and has a key-on wakeup function. INT input pin is also used as port P2 TOUT output pin has the function to output the timer 2 underflow signal divided by 2. TOUT output pin is also used as port D9. VDCE pin is used to control the operation/stop of the voltage drop detection circuit. The circuit is operating when “H” level is input to the VDCE pin. It is stopped when “L” level is input to this pin. Pin VDD VSS CNV SS RESET XIN XOUT D 0–D 9 P00–P03 P10–P13 P20, P21 P30–P33 P40–P43 CARR INT T OUT VDCE

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MULTIFUNCTION Pin D 9 P21 Multifunction TOUT INT Multifunction D 9 P21 Pin TOUT INT Notes 1: Pins except above have just single function. 2: The port D9 is the output port and port P21 is the input port. CONNECTIONS OF UNUSED PINS Connection Connect to VSS , or set the output latch to “0” and open. Set the output latch to “1” and open. Connect to VSS (Note 1). Connection Connect to VSS , or set the output latch to “0” and open. Connect to VSS (Note 2) or open (Note 3). Open. Pin P30–P33 P40–P43 CARR Pin D 0–D 8 D 9/TOUT P00–P0 3 P10–P1 3 P20, P21/INT Notes 1: When the P21/INT pin is connected to VSS pin, set the return level to “H” level by software (interrupt control register I12=“1”). When the P21/INT pin is connected to VSS pin while the return level is set to “L” level, system returns from RAM back-up state immediately after system enters the RAM back-up state. 2: In order to connect ports P40–P43 to VSS , turn off their pull-up transistors (pull-up control register PU0i=“0”) by software and also invalidate the key-on wakeup functions (key-on wakeup control register K0i=“0”). When these pins are connected to VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. In order to make these pins open, turn on their pull-up transistors (register PU0i=“1”) by software (i = 0, 1, 2, 3). Be sure to select the key-on wakeup function and the pull-up function with every one port. 3: In order to make ports P4 0–P4 3 open, turn on their pull-up transistors (register PU0i = “1”) by software (i = 0, 1, 2, 3). (Note in order to set the output latch to “0” or “1” or make pins open)

• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note in order to connect unused pins to V SS )
• To avoid noise, connect the unused pins to VSS at the shortest distance using a thick wire. PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Port P3 Port P4 Control bits Control instructions SD RD CLD OP0A IAP0 OP1A IAP1 IAP2 SNZI0 (Note) OP3A IAP3 IAP4 Control registers PU0 Output structure N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain Remark Pull-up functions Key-on wakeup functions Pull-up functions Key-on wakeup functions Key-on wakeup function Pull-up functions (programmable) Key-on wakeup functions (programmable) W2 2 controls the switch of D9/ TOUT pin Note: Level of the P21/INT pin can be examined with the SNZI0 instruction. Pin D 0–D 8, D9/TOUT P00–P03 P10–P13 P20 P21/INT P30–P33 P40–P43 Input/ Output Output (10) I/O (4) I/O (4) Input (2) I/O Input (4)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS IAP4 instruction P42 PU0 2 K02 IAP4 instruction P43 PU0 3 K03 IAP4 instruction P41 PU0 1 K01 IAP4 instruction P40 PU0 0 K00 P21/INT IAP2 instruction External interrupt circuit P20 IAP2 instruction P30–P3 3 IAP3 instruction D T Q OP3A instruction Ai D T Q OP0A instruction Key-on wakeup input IAP0 instruction Pull-up transistor P00–P0 3Register A Ai(Note 2) D T Q OP1A instruction IAP1 instruction P10–P1 3 Ai D 9/TOUT Timer 2 underflow signal output W2 2 Decoder SD instruction RD instruction S RQ CLD instruction Decoder SD instruction RD instruction S RQ CLD instruction D 0–D 8 This symbol represents a parasitic diode. 2. i represents 0, 1, 2 or 3. Notes 1. (Note 1) Register A Key-on wakeup input (Note 1) Register A (Note 1) (Note 2) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 1) Register A Register A Register A Register A Register A Register Y Register Y Register A Pull-up transistor(Note 1) Pull-up transistor (Note 1) Pull-up transistor Pull-up transistor Key-on wakeup input Key-on wakeup input Key-on wakeup input Key-on wakeup input Key-on wakeup input (Note 1) Pull-up transistor Applied potential to ports P20 and P21 must be VDD or less.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS (continued) Timer 1 underflow signal C2 0 W1 0 Port CARR To timer 1 CARRY MR 3 Timer 2 underflow signal ORCLK Register B Register A (T3AB) Reload register R3L (8) Timer 3(8) Register B Register A (T3HAB) Reload register R3H (8) W3 3 Reload control circuit (TAB3) W3 1,W3 0 Not available (T3AB) (TAB3) T3F Timer 3 interrupt C2 1 W3 3 Q R T Q R T XIN This symbol represents a parasitic diode. Note : (Note)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag (CY) Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Fig. 4 TABP p instruction execution example Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2 DR 1 DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 84 0 Middle-order 4 bits Low-order 4 bits Register A (4) Register B (4) The contents of register A High-order 2 bits Register B (4) Register W5 (2)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used when using an interrupt service routine or when executing a table reference instruction. Accordingly, be careful not to stack over when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3- bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. SK 0 SK 1 SK 2 SK 3 SK 4 SK 5 SK 6 SK 7 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Program counter (PC) Executing the return or table reference instruction Executing the subroutine call or table reference instruction Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK 0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. (SP) 0 (SK0) 000116 (PC) SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) (SK0) (SP) 7 Note: Ý Ý Ý Ý Ý

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD or RD instruction (Figure 9). Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register Z (2) Register X (4) Register Y (4)Specifying RAM digit Specifying RAM file Specifying RAM file group p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter (PC) PC H Specifying page PC L Specifying address 01 01 1 Set Specifying bit position Port D output latchRegister Y (4) D 5 D 4 D 0D 6D 9

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PROGRAM MEMORY (ROM) 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34570M8. Table 1 ROM size and pages Product M34570M4 M34570M8 M34570E8 M34570MD M34570ED ROM size (5 10 bits) 4096 words 8192 words 8192 words 16384 words 16384 words Pages 32 (0 to 31) 64 (0 to 63) 64 (0 to 63) 128 (0 to 127) 128 (0 to 127) Fig. 10 ROM map of M34570Mx Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure Note: When the TABP instruction is executed after executing the SBK instruction, data in pages 64 to 127 can be referred. When the TABP instruction is executed after executing the RBK instruction, data in pages 0 to 63 can be referred. A top part of page 1 (addresses 0080 16 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction. 90 87654321 Interrupt address page 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 1FFF 16 018016 Page 1 Page 2 Page 0 Page 3 Page 127 0FFF 16 Page 31 90 87654321 External 0 interrupt address008016

008416 Timer 1 interrupt address

Timer 2 interrupt address008616 00FF16 Timer 3 interrupt address008816

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Table 2 RAM size RAM size 128 words 5 4 bits (512 bits) Fig. 12 RAM map Product M34570Mx M34570Ex Register Y Register Z Register X 0 1 7 RAM 128 words 5 4 bits (512 bits) 23 6 128 words ...

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• Interrupt enable flag (INTE) = “1” (Interrupt enabled)
• Interrupt enable bit = “1” (Interrupt request occurrence enabled)
• An interrupt activated condition is satisfied (request flag = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bits (V1 0–V1 3, V20–V2 3) Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt request or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Priority level Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Skip instruction SNZ0 SNZT1 SNZT2 SNZT3 Request flag EXF0 T1F T2F T3F Enable bit V10 V12 V13 V20 Table 5 Interrupt enable bit function Skip instruction Invalid Valid Interrupt enable bit Occurrence of interrupt request Enabled Disabled

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

• Program counter (PC)
• Stack register (SK)
• Interrupt enable flag (INTE)
• Interrupt request flag (only the flag for the current interrupt source)
• Data pointer, carry flag, registers A and B, skip flag Fig. 13 Program example of interrupt processing (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after a branch to a sequence for storing data into stack register is performed. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return to main routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning to the main routine. (Refer to Figure 13) Fig. 14 Internal state when interrupt occurs Fig. 15 Interrupt system diagram EI RTI Interrupt service routine Interrupt occurs Interrupt is enabled Main routine : Interrupt enabled state : Interrupt disabled state T1F V12 EXF0 V10 Address 4 in page 1 Address 0 in page 1 T2F V1 3 Address 6 in page 1 Timer 1 underflow Request flag (state retained) Enable bit Enable flagActivated condition INT pin (L → H or H → L input) INTE Timer 2 underflow T3F V2 0 Timer 3 underflow Address 8 in page 1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Interrupt control register l Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control register V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V1 at reset : 0000

2 RAM back-up : 00002 R/W

Timer 3 interrupt enable bit This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) Interrupt control register V2 at reset : 0000 2 at RAM back-up : 00002 R/W This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Note: “R” represents read enabled, and “W” represents write enabled. l Interrupt control register V2 Interrupt enable bit of timer 3 is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10–V1 3 and V20–V2 3), and interrupt request flags (EXF0, T1F, T2F, T3F) are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of instructions other than one-cycle instructions (Refer to Figure 16). Fig. 16 Interrupt sequence Notes 1: The system clock = f(XIN)/4 is selected just after system is released from reset. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the instruction executed at the time when each interrupt activated condition is satisfied. 2 to 3 machine cycles (Notes 2, 3) Software starts from interrupt address. Flag cleared Interrupt enabled state EI instruction execution cycleInterrupt enable flag (INTE) Retaining level for 4 cycles or more of f(XIN) is necessary. Interrupt disabled state Flag EXF0 Flag T1F, T2F T3F INT pin External interrupt Timer 1, timer 2, timer 3 interrupts Interrupt activated condition satisfied T1 T2 T3 T1 T2 T3 T1 T2 T3 1 machine cycle f(XIN) System clock=f(XIN)/4 selected T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3T1 T2 T3 T1 T2 T3 f(XIN) System clock=f(XIN) selected l When an interrupt request flag is set after its interrupt is enabled (Note 1)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER EXTERNAL INTERRUPTS An external interrupt request occurs when a valid waveform (= waveform causing the external 0 interrupt) is input to an interrupt input pin (edge detection). The external 0 interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated condition Name External 0 interrupt Input pin P21/INT Valid waveform Falling waveform (“H”→ “L”) Rising waveform (“L”→ “H”) Valid waveform selection bit (I12) Fig. 17 External interrupt circuit structure One-sided edge detection circuit EXF0 I12 P21/INT Skip SNZI0 instruction External 0 interrupt Falling Rising

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P21/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. The P2 1/INT pin need not be selected the external interrupt input INT function or the normal input port P21 function. However, the EXF0 flag is set to “1” when a valid waveform is input to P2 1/INT pin even if it is used as an input port P21. l External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P2 1/INT pin. The valid waveform can be selected from rising waveform or falling waveform. An example of how to use the external 0 interrupt is as follows. À Select the valid waveform with the bit 2 of register I1. \` Clear the EXF0 flag to “0” with the SNZ0 instruction. ´ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ˆ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the P21/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External interrupt control register l Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt, the return level (valid level of wakeup signal) from the RAM back-up and P2 1/INT pin function. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Depending on the input state of P21/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction. I13 I12 I11 I10 Not used Interrupt valid waveform for INT pin/return level selection bit (Note 2) Not used Not used This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt control register I1 R/Wat reset : 00002 at RAM back-up : state retained

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TIMERS The 4570 Group has the programmable timers and a fixed dividing frequency timer. l Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). l Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” every n count of a count pulse. Fig. 18 Auto-reload function FF16 n 0016 n : Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time An interrupt occurs or a skip instruction is executed. Timer 1 interrupt request flag The contents of counter “1” “0”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER The 4570 Group timer consists of the following circuits.

• Prescaler : frequency divider
• Timer 1 : 10-bit programmable timer with the interrupt function and the carrier wave output auto-control function
• Timer 2 : 8-bit programmable timer with the interrupt function
• Timer 3 : 8-bit programmable timer with the interrupt function and the carrier wave generation function
• 16-bit timer Prescaler, timer 1, timer 2 and timer 3 can be controlled with the timer control registers W1, W2 and W3. 16-bit timer is the free-run counter without the control register. Each function is described below. Table 9 Function related timers Count source
• Instruction clock
• Prescaler output (ORCLK)
• Carrier wave generating circuit output (CARRY)
• Prescaler output (ORCLK)
• Timer 1 underflow
• Instruction clock
• 16-bit timer underflow
• Prescaler output (ORCLK)
• Timer 2 underflow
• f(X IN) or f(XIN)/2
• Instruction clock Structure Frequency divider 10-bit programmable binary down counter 8-bit programmable binary down counter 8-bit programmable binary down counter 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Timer 3 16-bit timer Use of output signal
• Timer 1, 2 and 3 count sources
• Timer 1 interrupt
• Carrier wave output auto-control
• Timer 2 count source
• Timer 2 interrupt
• Timer 3 count source
• T OUT output
• Timer 3 interrupt
• Timer 1 count source
• Carrier wave
• Watchdog timer (15-th bit output is counted twice.)
• Timer 2 count source (16-bit timer underflow) Frequency dividing ratio 4, 8 1 to 1024 1 to 256 1 to 256 65536 Control register (W5)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 19 Timers structure Notes 1: Count source is stopped by setting to “0.” 2: When the T1AB instruction is executed after setting W1 0 to “1,” data is only written to reload register R1. Register A ORCLK Timer 1 underflow signal WDF1 WDF2 W1 3 (Note 1) W1 2 Prescaler (TAB1) Register A Register A Register A Reload control circuit (TAB2) (Note 2) (TAB3) W3 3 T A B Q R T Timer 2 underflow signal D 9/TOUT D 9 output Register B W2 2 W1 0(Note 1) XIN T2F Timer 2 interrupt T1F Timer 1 interrupt Reload register R1 (10) System reset 16-bit timer (WDT) Instruction clock 1511 6 WRST instruction Reset signal Q R S WEF Timer 2 underflow signal Timer 1(10) (T1AB) Instruction clock Internal clock generating circuit (divided by 3)Frequency dividing circuit (divided by 4) MR 3 (TAB1) Register W5 CARRY Reload register R2 (8) Timer 2 (8) Register B (TR2AB) (TAB2) W2 3(Note 1) W2 1,W20 T3F Timer 3 interrupt Register B (T3AB) Reload register R3L (8) Timer 3(8) Register B (T3HAB) Reload register R3H (8) W3 3(Note1) MR 3 CARRY (TAB3) 16-bit timer underflow signal W1 1 W3 1,W30 Not available (T3AB) (to timer 1/port CARR) T A B System clock

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 10 Timer control registers Timer control register W1 W1 3 W1 2 W1 1 W1 0 at reset : 00002 at RAM back-up : 00002 R/W Stop (prescaler state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 8 Prescaler output (ORCLK) Carrier output (CARRY) Stop (state retained) Operating Prescaler control bit Prescaler dividing ratio selection bit Timer 1 count source selection bit Timer 1 control bit Timer control register W2 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating Port D TOUT pin W2 3 W2 2 W2 1 W2 0 Timer 2 control bit Port D9/TOUT pin function selection bit Timer 2 count source selection bits W2 1 Count source Prescaler output (ORCLK) Timer 1 underflow signal Instruction clock 16-bit timer underflow signal Timer control register W3 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating This bit has no function, but read/write is enabled. W3 3 W3 2 W3 1 W3 0 Timer 3 control bit Not used Timer 3 count source selection bits W2 0 W3 1 W3 0 Count source Timer 2 underflow signal Prescaler output (ORCLK) f(X IN) or f(XIN)/2 Not available Timer count value store register W5 at reset : 002 at RAM back-up : state retained R/W 2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address (D2D 1D 0A3A2A1A0) in page p specified by registers D and A is stored in this register W5 with the TABP p instruction. In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5 instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction. Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) Timer control registers l Timer control register W1 Register W1 controls the count source and count operation of timer 1, the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. l Timer control register W2 Register W2 controls the count operation and count source of timer 2 and D 9/TOUT pin function. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. l Timer control register W3 Register W3 controls the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register l Timer count value store register W5 2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address in page p specified by registers D and A is stored in this register W5 with the TABP p instruction. In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5 instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction. (2) Precautions Note the following for the use of timers. l Prescaler Stop the prescaler operation to change its frequency dividing ratio. l Count source Stop timer 1, 2 or 3 counting to change its count source. l Reading the timer count value Stop each of the timers and then execute the TAB1, TAB2 or TAB3 instruction to read timer 1, 2 or 3 data. l Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. l Writing to reload register R3H When writing data to reload register R3H while timer 3 is operating, avoid a timing when timer 3 underflows. (3) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. When the bit 3 of register W1 is cleared to “0,” prescaler is initialized, and the output signal (ORCLK) stops. (4) Timer 1 (interrupt function) Timer 1 is a 10-bit binary down counter with the timer 1 reload register (R1). The 10-bit data can be set in timer 1 through registers A, B and W5. Set bits 0 to 3 to register A, bits 4 to 7 to regiser B and bits 8 to 9 to register W5 to set data to timer 1. Also, ROM pattern (bits 0 to 9) can be set to registers A, B and W5 with the TABP p instruction. Execute the T1AB instruction to set data in timer 1. When timer 1 stops, 10-bit data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer 1 is operating, data can be set only in the reload register (R1) with the T1AB instruction. When setting the next count data to reload register R1 while timer 1 is operating, be sure to set data before timer 1 underflows. Timer 1 starts counting after the following process; À set data in timer 1, \ select the count source with bit 1 of register W1, ´ set the bit 0 of register W1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 1023). Data can be read from timer 1 to registers A, B and W5. Stop counting and then execute the TAB1 instruction to read its data. (5) Timer 2 (interrupt function) Timer 2 is an 8-bit binary counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the TAB2 instrucion. Also, data can be set only in the reload register (R2) with the TR2AB instruction. Timer 2 starts counting after following process; À set data in timer 2, \ select the count source with bits 0 and 1 of register W2, ´ set the bit 3 of register W2 to “1.” Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). When a value set in reload register R2 is n, timer 2 divides the count source signal by n+1 (n = 0 to 255). Data can be read from timer 2 to registers A and B with the TAB2 instruction. Stop counting and then execute the TAB2 instruction to read its data.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Timer 3 Timer 3 is an 8-bit binary down counter with the timer 3 reload registers (R3H, R3L). Data can be set simultaneously in timer 3 and the reload register (R3L) with the T3AB instruction. Data can be set in reload register R3H with the T3HAB instruction. Timer 3 starts counting after the following process; À set data in timer 3, \` select the count source with the bits 1 and 0 of register W3, ´ set the bit 3 of register W3 to “1.” The f(X IN) or f(XIN)/2 is selected as the count source by setting W3 1 to “1” and W30 to “0.” When the f(XIN) is selected as the system clock (bit 3 of clock control register MR= “0”), f(XIN) is selected as the count source. When the f(XIN)/4 is selected as the system clock (bit 3 of clock control register MR= “1”), f(XIN)/2 is selected as the count source. Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 become “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3H, and count coutinues (auto- reload function). When the timer 3 underflows again after auto-reload is performed, the timer 3 interrupt request flag (T3F) is set to “1” and new data is reloaded from the reload register R3L and count continues. Timer 3 reloads data from reload register R3H or R3L alternately every underflow. When the T3AB instruction is executed while timer 3 is operating, new data is set in timer 3 and reload register R3L, count is started again at the next machine cycle. At the next underflow, data is reloaded from R3H and count continues regardless that auto-reload is performed from reload register R3H or R3L at the previous underflow. Data can be read from timer 3 through registers A and B. Stop counting and then execute the TAB3 instruction to read its data. Timer 3 can be also used as the carrier wave generating circuit. (7) Timer output pin (D 9/TOUT ) Timer output pin (D9/TOUT ) is used to output the timer 2 underflow signal. The D 9/TOUT pin function can be selected by the bit 2 of register W2. (8) Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control registers V1 and V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). Timer WDT starts downcounting the instruction clocks as the count source immediately after system is released from reset. The underflow signal is generated when the count value reaches “0000 16.” This underflow signal can be used as the timer 2 count source. When the WRST instruction is executed after system is released from reset, the WEF flag is set to “1.” At this time, the watchdog timer starts operating. When the count value of timer WDT reaches “BFFF 16” or “3FFF16,” WDF1 flag is set to “1.” Then, if the WRST instruction is not executed while the timer WDT counts 32767, the WDF2______ flag is set to “1” and the RESET pin outputs “L” level to reset the microcomputer. In software using the watchdog timer, make sure that the WRST instruction is executed in 32766 machine cycles or less in order to keep the microcomputer operating normally. To prevent the watchdog timer from stopping in the event of misoperation, the WEF flag is designed not to be initialized once the WRST instruction has been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start. Fig. 20 Watchdog timer function Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer Value of timer WDT Flag WDF2 RESET pin output System resetWRST instruction execution Flag WEF FFFF 16 0000 16 Flag WDF1 3FFF 16 BFFF 16 WRST instruction execution The contents of the WEF flag, the WDF1 and WDF2 flags and the timer WDT are initialized at the RAM back-up mode. However, if the WDF2 flag is set to “1” at the same time that the microcomputer enters the RAM back-up mode, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up mode (refer to Figure 21).

• ••• POF EPOF ; POF instruction execution enabled (RAM back-up mode)Oscillation stop WRST ; Clear WDF1 flag

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CARRIER WAVE GENERATING CIRCUIT The 4570 Group has a carrier wave generating circuit that generates the transfer waveform for various remote control carrier wave. The carrier wave generating circuit outputs the signal inverted every timer 3 underflow (CARRY) from port CARR. When using the carrier wave generating circuit, select the f(X IN) or f(XIN)/2 for the timer 3 count source (W31=“1”, W30=“0”). When the bit 3 of the clock control register MR is “0” (system clock=f(X IN)), f(XIN) is selected as the count source. When the bit 3 of the clock control register MR is “1” (system clock=f(XIN)/4), f(XIN)/2 is selected as the count source. Set the count value corresponding to “L” interval of carrier wave output to timer 3 reload register R3L. Set the count value corresponding to “H” interval of carrier wave output to timer 3 reload register R3H. Also, timer 1 can auto-control the carrier wave output of port CARR by setting the carrier wave output control register (C2). When timer 3 is stopped, the output level of port CARR is initialized. (“L” level) (1) Carrier wave output control register (C2) Timer 1 can auto-control the output enable interval and the output disable interval of the carrier wave output from port CARR by setting the bit 0 of register C2 to “1.” Set the contents of this register through register A with the TC2A instruction. The setting of the output enable/disable interval is described below. À Validate the carrier wave output auto-control function (C2 0=“1”). \` Set the count value (“L” interval of carrier wave output) to timer 3 and reload register R3L. ´ Set the count value (“H” interval of carrier wave output) to timer 3 reload register R3H. ˆ Set the count value (the output enable interval of carrier wave from port CARR) to timer 1. ˜ Select the carrier wave (W1 1 = “1”) as the timer 1 count source. ¯ Operate timer 1 (W10=“1”). ˘ Operate timer 3 (W33=“1”). ˙ Set the next count value (the output disable interval of carrier wave from port CARR) to reload register R1 before timer 1 underflow occurs. The carrier wave is output from port CARR until the first timer 3 underflow occurs. The output of the carrier wave from port CARR is disabled and the next count value is loaded from reload register R1 to timer 1 by the first timer 1 underflow. Then, the output of carrier wave is disabled until the second timer 1 underflow occurs. Also, the next enable interval of the carrier wave output can be set by setting the third count value to timer 1 reload register R1 before the second timer 1 underflow occurs. If the carrier wave output auto-control function is invalidated (C2 0=“0”) while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto-control is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W10=“0”). When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto- control of carrier wave output is started again when the next timer 1 underflow occurs. Stop the timer 3 and invalidate the auto-control function by timer 1 to use the port CARR output contorl bit (C2 1). (2) Notes when using the carrier wave output auto-control function l Set the timer 1 and register C2 before timer 3 is started to operate (W33=“1”). l Stop the timer 1 (W10=“0”) after stopping the timer 3 (W3 3=“0”) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. l If the carrier wave output auto-control function is invalidated (C20=“0”) while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto- control is invalidated regardless of timer 1 underflow. When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto-control by timer 1 is validated again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit (C20) is changed during timer 1 underflow, the error-operation may occur. l When the carrier wave output auto-control function is selected, use the carrier wave CARRY as the timer 1 count source. If the ORCLK is used as the count source, a short pulse may occur in port CARR output because ORCLK is not synchronized with the carrier wave. l When the carrier wave output auto-control function is selected and data is set to reload register R1 while timer 1 is operating, avoid the timing that the contents of timer 1 becomes “0” to execute the T1AB instruction. Table 11 Carrier wave output control register C2 1 Port CARR output control bit at reset : 002Carrier wave output control register C2 at RAM back-up : 00 2 W C2 0 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Port CARR “L” level output Port CARR “H” level output Carrier wave output auto-control bit Note: “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 22 Carrier wave output auto-control by timer 1 (C20) 0 Register C20 t (C20) 1 t (C2 0) 0 (C2 0) 1 t Interval “a” is set by timer 1 t t t(C20) 1 Carrier wave output start Carrier wave output start Port CARR output“H” “L” Timer 1 underflow Timer 1 start t“1” “0” Timer 1 underflow “1” “0” Port CARR output “H” “L” “1” “0” Timer 3 underflow CARRY Timer 3 start t “H” “L” “1” “0” f(XIN) (divided by 3) “H” “L” 21 0 3 210 2 10 3 2 10 2 10 R3H Timer 3 Timer 3 reload register R3H “L” interval TW3A instruction Machine cycle R3L R3H R3L 0316 0216 set by R3L CARRY “H” “L” CARRY “H” “L” “H” interval set by R3H “L” interval set by R3L “H” interval set by R3H Timer 3 reload register R3L Interval “b” is set by reload register R1 Interval “c” is set by reload register R1 Interval “d” is set by reload register R1 t t t Ý Ý Ý Ý Ý

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied;

• the value of supply voltage is the minimum value or more of Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. VDD Power-on reset circuit output voltage Internal reset signal Power-on RESET pin WEF Watchdog timer output Internal reset signal Reset state Reset released This symbol represents a parasitic diode. Note: Applied potential to RESET pin must be V DD or less. (Note) Power-on reset circuit Pull-up transistor Voltage drop detection circuit f(XIN) RESET f(XIN) is counted 10757 to 10786 times Software start (Address 0 in page 0) Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed. (Note) “H” “L” Fig. 23 Reset release timing Fig. 24 RESET pin input waveform and reset operation (1) Power-on reset Reset can be automatically performed at power on (power- on reset) by the built-in power-on reset circuit. When the built- in power-on reset circuit is used, the time for the supply voltage to reach the minimum operating voltage must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Fig. 25 Power-on reset circuit example Note: Keep the value of supply voltage the minimum value or more of the recommended operating conditions. RESET Software start (Address 0 in page 0) Reset input 1machine cycle or more 0.3VDD f(XIN) is counted 10757 to 10786 times (Note) 0.85VDD

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Address 0 in page 0 is set to program counter. (2) Internal state at reset Table 12 shows port state at reset, and Figure 26 shows internal state at reset (they are retained after system is released from reset). Name D 0–D 8, D9/TOUT P00–P0 3 P10–P1 3 P20, P21/INT P30–P3 3 P40–P4 3 CARR State High impedance (Note 1) “H” (VDD ) level (Note 1) High impedance High impedance (Note 1) High impedance (Note 2) “L” (VSS ) level Function D 0–D 8, D9 P00–P03 P10–P13 P20, P21 P30–P33 P40–P43 CARR Table 12 Port state at reset The contents of timers, registers, flags and RAM except those shown in Figure 26 are undefined, so set the initial values to them. Notes 1: Output latch is set to “1.” 2: The pull-up transistor is turned off. Fig. 26 Internal state at reset 00000000000000 55555555 00 0 0 “5 ” represents undefined. 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0 0 0 0 (Prescaler and timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0 0 0 0 (Timer 3 stopped) 1000 00 0 0 0000 00 0 0 00 0 0 0000 555 00 0 0 0000 111

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 27 Voltage drop detection reset circuit Fig. 28 Voltage drop detection circuit operation waveform RESET pin WEF Watchdog timer output Internal reset signal Power-on reset circuit Pull-up transistor Voltage drop detection circuit VDD Reset voltage Internal reset signal The microcomputer starts operation after the f(XIN) is counted 10757 to 10786 times. Note: Set the VDCE pin to “H” level to operate the voltage drop detection circuit. The voltage drop detection circuit is not operated at the RAM back-up mode.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RAM BACK-UP MODE The 4570 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equivalent to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation is stopped retaining RAM, the function of reset circuit and states at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 13 shows the function and states retained at RAM back- up. Figure 29 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up mode) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up mode by executing the EPOF and POF instructions continuously, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the software from address 0 in page 0 when;

• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop. In this case, the P flag is “0.” Table 13 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Clock control register MR Timer control register W1 Timer control registers W2, W3 Timer count value store register W5 Interrupt control registers V1, V2 Interrupt control register I1 Carrier wave output control register C2 8-bit general-purpose register SI Timer 1 function Timer 2 function Timer 3 function Pull-up control register PU0 Key-on wakeup control register K0 External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Watchdog timer flag 1 (WDF1) Watchdog timer flag 2 (WDF2) Watchdog timer enable flag (WEF) 16-bit timer (WDT) Interrupt enable flag (INTE) RAM back-up O O O O O O O (Note 3) (Note 3) O O (Note 3) (Note 3) 5 (Note 4) 5 (Note 4) 5 (Note 4) 5 (Note 4) Notes 1: “O” represents that the function can be retained, and “5 ” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “1112” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the EPOF and POF instructions.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 14 shows the return condition for each return source. (5) Port P4 control registers

• Key-on wakeup control register K0 Register K0 controls the port P4 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register
• Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P4 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 14 Return source and return condition Remarks Port P0 shares the falling edge detection circuit with ports P1 and P4. Key-on wakeup functions of ports P0 and P1 are always valid. The key- on wakeup function valid/invalid of port P4 can be controlled with register K0. Set the port using the key-on wakeup function selected to “H” level before going into the RAM back-up mode. Select the return level (“L” level or “H” level) with the bit 2 of register I1 according to the external state before going into the RAM back-up mode. Return condition Return by an external falling edge Return by an external “H” level or “L” level input. The EXF0 flag is not set. Return source Ports P0, P1 and P4 P21/INT pin External wakeup signal

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 29 State transition S R Q Power down flag P POF instruction Reset input or voltage drop detection circuit output l Set source POF instruction is executed l Clear source Reset input Software start P = “1” Yes Warm startCold start No Fig. 30 Set source and clear source of the P flag Fig. 31 Start condition identified example using the SNZP instruction Table 15 Key-on wakeup control register and pull-up control register K03 K02 K01 K00 Port P43 key-on wakeup control bit Port P42 key-on wakeup control bit Port P41 key-on wakeup control bit Port P4 0 key-on wakeup control bit Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 0000 2 at RAM back-up : state retainedR/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P4 3 pull-up transistor control bit Port P4 2 pull-up transistor control bit Port P41 pull-up transistor control bit Port P4 0 and P01 pull-up transistor control bit at reset : 00002 at RAM back-up : state retainedPull-up control register PU0 R/W PU0 3 PU0 2 PU0 1 PU0 0 Note: “R” represents read enabled, and “W” represents write enabled. : The time required to stabilize f(XIN) oscillation is automatically generated by hardware. Stabilizing time a POF instruction is executed A f(XIN) oscillationReturn input (Stabilizing time a ) B (RAM back-up mode) f(XIN) stop Reset (Stabilizing time a )

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CLOCK CONTROL The clock control circuit consists of the following circuits. l Clock generating circuit l Control circuit to stop the clock oscillation l System clock selection circuit l Instruction clock generating circuit l Control circuit to return from the RAM back-up mode Fig. 32 Clock control circuit structure Fig. 33 Ceramic resonator external circuit Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built-in between pins XIN and XOUT . ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) M34570M4-XXXFP Mask ROM Order Confirmation Form, M34570M8-XXXFP Mask ROM Order Confirmation Form, or M34570MD-XXXFP Mask ROM Order Confirmation Form (three sets containing the identical data) The wait time control circuit is automatically used to generate the time required to stabilize the f(XIN) oscillation. Internal clock generating circuit (devided by 3) Insturuction clock I12 “H” level “L” level MR 3 RESET Falling detected Port P40 Multi- plexer K00,K01,K02,K03 Counter Wait time control circuit (Note) Software start signal Frequency dividing circuit (divided by 4) R S Q POF instruction XIN XOUT P21/INT Oscillation circuit Key-on wakeup control register Ports P0, P1 Port P41 Port P42 Port P43 System clock Note: M34570 XIN XOUT Rd C IN C OUT Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF PRECAUTIONS À Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire. In the One Time PROM version, CNV SS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to V SS through a resistor about 5 kΩ (connect this resistor to CNV SS /VPP pin as close as possible). \` Prescaler Stop the prescaler operation to change its frequency dividing ratio. ´ Count source Stop timer 1, timer 2 or timer 3 counting to change its count source. ˆ Reading the timer count value Stop each of the timers and then execute the TAB1, TAB2 or TAB3 instruction to read timer 1, 2 or 3 data. ˜ Writing to reload register R1 When writing the data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. ¯ Writing to reload register R3H When writing the data to reload register R3H while timer 3 is operating, avoid a timing when timer 3 underflows. ˘ Notes on timer 3 operation start Set the timer 1 and register C2 before timer 3 is started to operate (W3 3=“1”). ˙ Notes on carrier wave output auto-control operation stop Stop the timer 1 (W1 0=“0”) after stopping the timer 3 (W33=“0”) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. ¨ Notes on setting carrier wave output control regiter C2 If the carrier wave output auto-control function is invalidated (C2 0=“0”) while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto-control is invalidated regardless of timer 1 underflow. When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto-control by timer 1 is validated again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit (C20) is changed during timer 1 underflow, the error-operation may occur. É Notes on timer 1 count source When the carrier wave output auto-control function is selected, use the carrier wave CARRY as the timer 1 count source. If the ORCLK is used as the count source, a short pulse may occur in port CARR output because ORCLK is not synchronized with the carrier wave. Notes on writing to reload register R1 when carrier wave output auto-control operation When the carrier wave output auto-control function is selected and data is set to reload register R1 while timer 1 is operating, avoid the timing that the contents of timer 1 becomes “0” to execute the T1AB instruction. One Time PROM version The operating power voltage of the One Time PROM version is within the range of 2.5 V to 5.5 V. Multifunction Note that the port D 9 output function and P21 input function can be used even when TOUT and INT pin function is selected. POF instruction Note that system cannot enter the RAM back-up state when executing only the POF instruction. Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction. Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. P21/INT pin When the interrupt valid waveform of P21/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes.
• Clear the bit 0 of register V1 to “0” and then change the interrupt valid waveform of P2 1/INT pin with the bit 2 of register I1 (refer to Figure 34À ).
• Clear the bit 2 of register I1 to “0” and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 34\ ). Depending on the input state of the P21/INT pin, the external 0 interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. LA 4 ; ( 555 02) TV1A ; The SNZ0 instruction is valid À LA 4 TI1A ; Change of the interrupt valid waveform NOP \ SNZ0 ;The SNZ0 instruction is executed NOP ... ... 5 : this bit is not related to the setting of INT. Fig. 34 External 0 interrupt program example

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SYMBOL The symbols shown below are used in the following list of instruction function and machine instructions. Symbol A B DR E SI PU0 MR X Y Z DP PC PC H PC L SK SP CY R3H R3L T1F T2F T3F

Contents

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Carrier wave output control register C2 (2 bits) 8-bit general-purpose register SI (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer count value store register W5 (2 bits) Key-on wakeup control register K0 (4 bits) Pull-up control register PU0 (4 bits) Clock control register MR (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 5 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 3 reload register Timer 3 reload register Timer 1 Timer 2 Timer 3 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag Port D (10 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (2 bits) Port P3 (4 bits) Port P4 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Symbol WDF1 WDF2 WEF INTE EXF0 P D x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4570 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PC L) ← (DR 2–DR 0, A3–A0) (W5) ← (ROM(PC))9 to 8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A)AND(M(DP)) (A) ← (A)OR(M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 LIST OF INSTRUCTION FUNCTION Grouping GroupingMnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Register to register transferRAM addressesRAM to register transfer Arithmetic operation RAM to register transfer Bit operation Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PC L) ← (DR 2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Grouping Comparison operationBranch operationSubroutine operationReturn operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Interrupt operation Function (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) (W5) ← (T19–T18) (B) ← (T17–T14) (A) ← (T13–T10) at timer 1 stop (W1 0=0) (R19–R1 8) ← (W5) (T19–T18) ← (W5) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) At timer 1 operating (W1 0=1), (R19–R1 8) ← (W5) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (R27–R2 4) ← (B) (R23–R2 0) ← (A) Mnemonic TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW5 TW5A TAB1 T1AB TAB2 T2AB TR2AB Timer operation Function (B) ← (T37–T34) (A) ← (T33–T30) (R3L7–R3L 4) ← (B) (T37–T34) ← (B) (R3L3–R3L 0) ← (A) (T33–T30) ← (A) (R3H7–R3H 4) ← (B) (R3H3–R3H 0) ← (A) (T1F) = 1 ? After skipping the next instruction, (T1F) ← 0 (T2F) = 1 ? After skipping the next instruction, (T2F) ← 0 (T3F) = 1 ? After skipping the next instruction, (T3F) ← 0 GroupingMnemonic TAB3 T3AB T3HAB SNZT1 SNZT2 SNZT3 Mnemonic DI EI SNZ0 SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A Grouping GroupingFunction (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping the next instruction, (EXF0) ← 0 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) Timer operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Function (PC) ← (PC) + 1 RAM back-up mode POF instruction valid (P) = 1 ? WDF1 ) ← 0, (WEF ) ← 1 (A) ← (MR3–MR 0) (MR 3–MR 0) ← (A) (B) ← (SI7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) When executing the TABP p instruction, p6 ← 1 When executing the TABP p instruction, p 6 ← 0 Mnemonic NOP POF EPOF SNZP WRST TAMR TMRA TABSI TSIAB SBK RBK Mnemonic IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4 CLD RD SD TK0A TAK0 TPU0A TAPU0 TC2A Grouping GroupingFunction (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A3, A2) ← (0) (A) ← (P3) (P3) ← (A) (A) ← (P4) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (K0) ← (A) (A) ← (K0) (PU0) ← (A) (A) ← (PU0) (C2 1, C20) ← (A1, A0) Input/Output operation Other operation C arrier wave generating operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE D 9—D 4 000000 Hex. notation D 3— D 0 000001000010 000011000100 000101000110 000111001000 001001001010 001011001100 001101001110 001111 010000 010111 011000 011111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F NOP POF SNZP DI EI RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY SZB SEAn SEAM TDA TABE SZC BMLA SNZ0 TV1A RT RTS RTI TASP TAD TAX TAZ TAV1 EPOF LZ LZ LZ LZ RB RB RB RB SB SB SB SB 05 06 07 08 09 0A A A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 10* TABP 11* TABP 12* TABP 13* TABP 14* TABP 15* BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML 0C 0D BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0E 0F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 10—17 B B B B B B B B B B B B B B B B 18—1F SZB SZB SZB SNZI0 TV2A TAV2 TABP 16* TABP 17* TABP 18* TABP 19* TABP 20* TABP 21* TABP 22* TABP 23* TABP 24* TABP 25* TABP 26* TABP 27* TABP 28* TABP 29* TABP 30* TABP 31* TABP 32 TABP 48 TABP 33 TABP 49 TABP 34 TABP 50 TABP 35 TABP 51 TABP 36 TABP 52 TABP 37 TABP 53 TABP 38 TABP 54 TABP 39 TABP 55 TABP 40 TABP 56 TABP 41 TABP 57 TABP 42 TABP 58 TABP 43 TABP 59 TABP 44 TABP 60 TABP 45 TABP 61 TABP 46 TABP 62 TABP 47 TABP 63 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL — — — — ——— — — — — The above table shows the relationship between machine language codes and machine language instructions. D 3—D 0 show the low- order 4 bits of the machine language code, and D9—D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "—." ** cannot be used at M34570M4. For M34570M4/M8/E8, the SBK and RBK instructions cannot be used. For M34570MD/ED, the pages which is referred with the TABP instruction (*, **) can be switched with the SBK and RBK instructions. After executing the SBK instruction, the pages which can be referred with the TABP instruction are 64 to 127. (ex. TABP 0 fi TABP 64) After executing the RBK instruction, the pages which can be referred with the TABP instruction are 0 to 63. If the SBK instruction is not executed, the pages which can be referred with the TABP instruction are always 0 to 63. The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 1 p p a a a a a a a 1 p p a a a a a a a 1 p p p 0 0 p p p p 1 p p p 0 0 p p p p 0 0 0 1 1 1 n n n n 0 0 0 0 1 0 1 0 1 1 RBK SBK

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE (CONTINUED) D 9—D 4 100000 Hex. notation D 3— D 0 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111 110000 111111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F TW1A TW2A TI1A OP0A TAI1 — TAW1 TAW2 — 25 26 27 28 29 2A IAP0 IAP1 SNZT2 TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI 2E 2F LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY 30—3F OP1A SNZT1 WRST TMA TAM XAM XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD IAP2 — — — — — — — — — — — — — — — — — — BL BML BLA BMLA SEA SZD The second word 1 p p a a a a a a a 1 p p a a a a a a a 1 p p p 0 0 p p p p 1 p p p 0 0 p p p p 0 0 0 1 1 1 n n n n 0 0 0 0 1 0 1 0 1 1 TPU0A TAB1 TMRA TAMR TAPU0 — — — — — — — — — — TW3A TAW3 TC2A TK0A OP3A T2AB T3AB TSIAB TAW5 TAK0 TABSI IAP3 IAP4 SNZT3 TAB2 TAB3 TW5A T1AB T3HAB TR2AB The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code Continuous (Y) = 0 (Y) = 15 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Transfers the contents of register D to register A. Transfers the contents of register Z to register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. Register to register transferRAM addresses MACHINE INSTRUCTIONS TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3x2x1x0y3y2y1y0 00010010z1z0 0000010011 0000010111 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR0) ← (A2–A0) (A2–A0) ← (DR2–DR0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017

(Y) = 15 (Y) = 0 Continuous After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 9 and 8 to register W5, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in

page p. When this instruction is executed, 1 stage of stack register is used. When this instruction is executed after executing the SBK instruction, pages 64 to 127 are specified. When this instruction is executed after executing the RBK instruction, pages 0 to 63 are specified. When this instruction is executed after system is released from reset or returned from RAM back-up, pages 0 to 63 are specified. RAM to register transferArithmetic operation TAM j XAM j XAMD j XAMI j TMA j LA n TABP p (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H) ← p (PCL) ← (DR2–DR0, A3–A0) (W5) ← (ROM(PC))9 to 8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (Note) 2C j 2D j 2F j 2E j 2B j 07 n 08 p 101100jjjj 101101jjjj 101111jjjj 101110jjjj 101011jjjj 000111nnnn 0010p 5p4p3p2p1p0 MACHINE INSTRUCTIONS (CONTINUED) Note: p is 0 to 31 for M34570M4 and p is 0 to 63 for M34570E8 and M34570M8. p is 0 to 127 for M34570ED and M34570MD, and p6 is specified with the SBK and RBK instructions. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Performs the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Performs the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets carry flag CY to “1.” Clears carry flag CY to “0.” Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit. Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “1.” Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “0.” Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Arithmetic operationBit operation Comparison operation AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn 00A 00B 06n 018 019 007 006 02F 01C 01D 05 C 04 C 02 j 02 6 02 5 07 n (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A)AND(M(DP)) (A) ← (A)OR(M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 MACHINE INSTRUCTIONS (CONTINUED)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code Skip unconditionally Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and

A in page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally. Branch operationSubroutine operation Return operation B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6a5a4a3a2a1a0 00111p4p3p2p1p0 10p5a6a5a4a3a2a1a0 0000010000 10p5p400p3p2p1p0 010a6a5a4a3a2a1a0 00110p4p3p2p1p0 10p5a6a5a4a3a2a1a0 0000110000 10p 5p400p3p2p1p0 0001000110 0001000100 0001000101 18 a 0E p 2p a 01 0 2p p 1a a 0C p 2pa 03 0 2p p 04 6 04 4 04 5 (PC L) ← a6–a0 (PCH) ← p (PCL) ← a6–a0 (Note) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (Note) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Note: p is 0 to 31 for M34570M4 and p is 0 to 63 for M34570E8 and M34570M8. p is 0 to 127 for M34570ED and M34570MD, and p6 is specified with the SBK and RBK instructions. MACHINE INSTRUCTIONS (CONTINUED)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code (EXF0) = 1 (INT) = “H” However, I12 = 1 (INT) = “L” However, I12 = 0 Clears the interrupt enable flag INTE to “0,” and disables the interrupt. Sets the interrupt enable flag INTE to “1,” and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is “1.” After skipping, clears the EXF0 flag to “0.” When bit 2 (I1 2) of register I1 is “1” : Skips the next instruction when the level of INT pin is “H.” When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer count value store register W5 to the low-order 2 bits of register A. The contents of the high-order 2 bits of register A is set to “0.” Transfers the contents of the low-order 2 bits of register A to timer count value store register W5. Interrupt operation MACHINE INSTRUCTIONS (CONTINUED) DI EI SNZ0 SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW5 TW5A 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 1001001111 1000010010 00 4 00 5 03 8 03 A 054 03F 055 03E 253 217 24B 20E 24C 20F 24D 210 24F 212 (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping the next instruction, (EXF0) ← 0 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) Timer operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code Transfers the contents of the high-order 2 bits of timer 1 to register W5, and transfers the contents of the low-order 8 bits of timer 1 to registers A and B. When stopping (W1 0=0), transfers the contents of register W5 to the contents of the high-order 2 bits of timer 1 and of the timer 1 reload register, and transfers the contents of registers A and B to the contents of the low-order 8 bits of timer 1 and of the timer 1 reload register. When operating (W1 0=1), transfers the contents of register W5 to the contents of the high-order 2 bits of the timer 1 reload register, and transfers the contents of registers A and B to the contents of the low- order 8 bits of the timer 1 reload register. Transfers the contents of timer 2 to registers A and B. Transfers the contents of registers A and B to timer 2 and timer 2 reload register. Transfers the contents of registers A and B to timer 2 reload register. Transfers the contents of timer 3 to registers A and B. Transfers the contents of registers A and B to timer 3 and timer 3 reload register R3L. Transfers the contents of registers A and B to timer 3 reload register R3H. TAB1 T1AB TAB2 T2AB TR2AB TAB3 T3AB T3HAB Timer operation 1001110000 1000110000 1001110001 1000110001 1000111010 1001110010 1000110010 1000111101 270 230 271 231 23A 272 232 23D (W5) ← (T1 9, T18) (B) ← (T17–T14) (A) ← (T13–T10) At timer 1 stop (W10=0), (R19, R18) ← (W5) (T19, T18) ← (W5) (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) At timer 1 operating (W10=1), (R19, R18) ← (W5) (R17–R14) ← (B) (R13–R10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R24) ← (B) (T27–T24) ← (B) (R23–R20) ← (A) (T23–T20) ← (A) (R27–R24) ← (B) (R23–R20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R3L7–R3L4) ← (B) (T37–T34) ← (B) (R3L3–R3L0) ← (A) (T33–T30) ← (A) (R3H7–R3H4) ← (B) (R3H3–R3H0) ← (A) MACHINE INSTRUCTIONS (CONTINUED)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code (T1F) = 1 (T2F) = 1 (T3F) = 1 Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears T1F flag. Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears T2F flag. Skips the next instruction when the contents of T3F flag is “1.” After skipping, clears T3F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P4 to register A. Sets port D to “1.” Clears a bit of port D specified by register Y to “0.” Sets a bit of port D specified by register Y to “1.” Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A. SNZT1 SNZT2 SNZT3 IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4 CLD RD SD TK0A TAK0 TPU0A TAPU0 1010000000 1010000001 1010000010 1001100000 1000100000 1001100001 1000100001 1001100010 1001100011 1000100011 1001100100 0000010001 0000010100 0000010101 1000011011 1001010110 1000101101 1001010111 280 281 282 260 220 261 221 262 263 223 264 011 014 015 21B 256 22D 257 (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 (T3F) = 1 ? After skipping the next instruction (T3F) ← 0 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A3, A2) ← 0 (A) ← (P3) (P3) ← (A) (A) ← (P4) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (K0) ← (A) (A) ← (K0) (PU0) ← (A) (A) ← (PU0) MACHINE INSTRUCTIONS (CONTINUED) Input/Output operation Timer operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function Mnemonic D9D8D7D6D5D4D3D2D1D0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code TC2A NOP POF EPOF SNZP WRST TABSI TSIAB TAMR TMRA SBK RBK 1010101001 0000000000 0000000010 0 001011011 0000000011 1010100000 1001111000 1000111000 1001010010 1000010110 0001000001 0001000000 (C2 1, C20) ← (A1, A0) (PC) ← (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? (WDF1) ← 0, (WEF) ← 1 (B) ← (SI 7–SI4) (A) ← (SI3–SI0) (SI7–SI4) ← (B) (SI3–SI0) ← (A) (A) ← (MR3–MR0) (MR3–MR0) ← (A) When executing the TABP p instruction, p6 ← 1 When executing the TABP p instruction, p 6 ← 0 2A9 000 002 05B 003 2A0 278 238 252 216 041 040 Transfers the contents of register A to carrier wave output control register C2. No operation Puts the system in RAM back-up mode state by executing the POF instruction after executing the EPOF instruction. Validates the POF instruction which is executed after the EPOF instruction by executing the EPOF instruction. Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. Operates the watchdog timer and initializes the watchdog timer flag (WDF1). Transfers the contents of general-purpose register SI to registers A and B. Transfers the contents of registers A and B to general-purpose register SI. Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR. Data area which is referred when executing the TABP p instruction is set to pages 64 to 127. This setting is valid only for the TABP p instruction. Data area which is referred when executing the TABP p instruction is set to pages 0 to 63. This setting is valid only for the TABP p instruction. If the SBK instruction is not executed, p 6 when executing the TABP p instruction is “0.” (P) = 1 Other operation Carrier generating circuit operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONTROL REGISTERS V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V1 at reset : 0000 Timer 3 interrupt enable bit This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) Interrupt control register V2 at reset : 0000 2 at RAM back-up : 00002 R/W This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Depending on the input state of P21/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction. I13 I12 I11 I10 Not used Interrupt valid waveform for INT pin /return level selection bit (Note 2) Not used Not used This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt control register I1 R/Wat reset : 00002 at RAM back-up : state retained

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONTROL REGISTERS (CONTINUED) Timer control register W1 W1 3 W1 2 W1 1 W1 0 at reset : 00002 at RAM back-up : 00002 R/W Stop (prescaler state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 8 Prescaler output (ORCLK) Carrier output (CARRY) Stop (state retained) Operating Prescaler control bit Prescaler dividing ratio selection bit Timer 1 count source selection bit Timer 1 control bit Timer control register W2 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating Port D9 TOUT pin W2 3 W2 2 W2 1 W2 0 Timer 2 control bit Port D9/TOUT pin function selection bit Timer 2 count source selection bits W2 1 Count source Prescaler output (ORCLK) Timer 1 underflow signal Instruction clock 16-bit timer underflow signal Timer control register W3 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating This bit has no function, but read/write is enabled. W3 3 W3 2 W3 1 W3 0 Timer 3 control bit Not used Timer 3 count source selection bits W2 0 W3 1 W3 0 Count source Timer 2 underflow signal Prescaler output (ORCLK) f(XIN) or f(XIN)/2 Not available Timer count value store register W5 at reset : 002 at RAM back-up : state retained R/W 2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address (D2D 1D 0A3A2A1A0) in page p specified by registers D and A is stored in this register W5 with the TABP p instruction. In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5 instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction. Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONTROL REGISTERS (CONTINUED) C2 1 Port CARR output control bit at reset : 002Carrier wave output control register C2 at RAM back-up : 00 2 W C2 0 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Port CARR “L” level output Port CARR “H” level output Carrier wave output auto-control bit K02 K01 K00 Port P43 key-on wakeup control bit Port P42 key-on wakeup control bit Port P41 key-on wakeup control bit Port P4 0 key-on wakeup control bit Key-on wakeup control register K0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 0000 2 at RAM back-up : state retainedR/W Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P4 3 pull-up transistor control bit Port P4 2 pull-up transistor control bit Port P41 pull-up transistor control bit Port P40 and P01 pull-up transistor control bit at reset : 00002 at RAM back-up : state retainedPull-up control register PU0 R/W PU0 3 PU0 2 PU0 1 PU0 0 f(XIN) f(XIN)/4 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. System clock selection bit Not used Not used Not used at reset : 10002 at RAM back-up : state retainedClock control register MR R/W MR 3 MR 2 MR 1 MR 0 at reset : 0016 at RAM back-up : state retained8-bit general purpose register PU0 R/W 8-bit general purpose register. 8-bit data can be transferred between this register PU0 and registers A and B with the TSIAB instruction and TABSI instruction. Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, RESET , XIN, VDCE Output voltage P0, P1, P3, D Output voltage CARR, XOUT Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Symbol V DD VI VO VO Pd Topr Tstg Ratings –0.3 to 7.0 –0.3 to V DD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 70 –40 to 125 Unit V V V V mW RECOMMENDED OPERATING CONDITIONS1 (Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Min. 2.0 4.5 2.0 2.5 4.5 2.5 1.8 2.0 Limits Symbol VDD VRAM VSS f(XIN) Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 4.2 2.0 1.0 4.2 2.0 1.0 Typ. Unit V V V V MHz Conditions f(XIN) ≤ 4.2 MHz Ceramic resonator f(XIN) ≤ 2.0 MHz Ceramic resonator f(XIN) ≤ 1.0 MHz Ceramic resonator f(XIN) ≤ 4.2 MHz Ceramic resonator f(XIN) ≤ 2.0 MHz Ceramic resonator f(XIN) ≤ 1.0 MHz Ceramic resonator RAM back-up VDD =2.0 V to 5.5V VDD =4.5 V to 5.5V VDD =2.0 V to 5.5V VDD =2.5 V to 5.5V VDD =4.5 V to 5.5V VDD =2.5 V to 5.5V Parameter Supply voltage RAM back-up voltage Supply voltage Mask ROM version System clock =f(X IN)/4 Mask ROM version System clock =f(X IN) One Time PROM version System clock =f(XIN)/4 One Time PROM version System clock =f(XIN) Mask ROM version One Time PROM version Mask ROM version System clock =f(XIN)/4 Mask ROM version System clock =f(X IN) One Time PROM version System clock =f(XIN)/4 One Time PROM version System clock =f(XIN) Oscillation frequency (at ceramic resonance)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS 2 (Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Limits Max. Typ. UnitConditions Min.ParameterSymbol VIH VIH VIH VIH VIL VIL VIL VIL IOL (peak) IOL (peak) IOL (avg) IOL (avg) IOH (peak) IOH (avg) Σ IOL Σ IOL TPON “H” level input voltage P0, P1, P2, P3, P4, VDCE “H” level input voltage XIN “H” level input voltage RESET “H” level input voltage INT “L” level input voltage P0, P1, P2, P3, P4, VDCE “L” level input voltage X IN “L” level input voltage RESET “L” level input voltage INT “L” level peak output current P0, P1, D 0–D 9, CARR “L” level peak output current P3 “L” level average output current P0, P1, D0–D 9, CARR (Note) “L” level average output current P3 (Note) “H” level peak output current CARR “H” level average output current CARR (Note) “L” total current P0, P1, P3 “L” total current D Power reset circuit valid power rising time –30 –15 –15 100 0.7V DD 0.85VDD 0.8VDD 0.8VDD VDD VDD VDD VDD 0.3VDD 0.3VDD 0.3VDD 0.2VDD V V V V V V V V V DD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V Mask ROM version VDD = 0 to 2.0 V One Time PROM version VDD = 0 to 2.5 V mA mA mA mA mA mA mA mA µs Note: The average output current is the average current value at the 100 ms interval.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Unit V V V µA µA µA mA µA kΩ kΩ V V Max. 0.9 0.9 1.5 1.5 2.6 125 250 130

ELECTRICAL CHARACTERISTICS

(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) LimitsSymbol VOL VOL VOH IIH IIL IOZ IDD R PH VT+ – VT– Test conditions IOL = 5 mA IOL = 2 mA IOL = 15 mA IOL = 12 mA IOH = 15 mA IOH = –7 mA VI = VDD (Note) VI = 0 V (Note) VO = VDD VDD = 5.0 V, f(XIN) = 4.2 MHz System clock = f(XIN)/4 VDD = 5.0 V System clock = f(XIN) VDD = 3.0 V, f(XIN) = 4.2 MHz System clock = f(XIN)/4 VDD = 3.0 V System clock = f(XIN) f(XIN) = stop, typical value at Ta = 25 °C VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Typ. 1.3 0.1 100 0.5 0.4 1.5 0.6 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Min. 2.4 1.0 f(XIN) = 2 MHz f(XIN) = 1 MHz f(XIN) = 1 MHz f(XIN) = 500 kHz 1.9 1.3 0.6 0.5 0.4 3.8 2.6 1.2 1.0 0.8 Parameter “L” level output voltage P0, P1, D0–D 9, CARR, RESET “L” level output voltage P3 “H” level output voltage CARR “H” level input current P0, P1, P2, P3, P4, RESET , VDCE “L” level input current P2, P3, P4, RESET , VDCE Output current at off-state D0–D 9 Supply current Pull-up resistor value Hysteresis Note: In this case, the pull-up transistor of port P4 is turned off by software. at CPU operating mode at RAM back-up mode P0, P1, P4 RESET INT RESET

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BASIC TIMING DIAGRAM Clock Port D output Port P0, P1, P3 output Port P0, P1, P2, P3, P4 input Interrupt input X IN Parameter Pin name Machine cycle State T3 T1 T2 T3 Mi Mi+1 INT D 0–D 9 P00–P03 P10–P1 3 P00–P03 P10–P13 P20, P21 P30–P33 P30–P33 P40–P43 (System clock=f(XIN)) XIN (System clock=f(XIN)/4)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Product M34570E8FP M34570EDFP PROM size (5 10 bits) 8192 words 16384 words RAM size (5 4 bits) 128 words 128 words Package 36P2R-A 36P2R-A ROM type One Time PROM BUILT-IN PROM VERSION In addition to the mask ROM version, the 4570 Group has the programmable ROM version software compatible with mask ROM. The One Time PROM version has PROM which can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM version, but it has a PROM mode that enables writing to built-in PROM. Table 16 shows the product of built-in PROM version. Figure 35 shows the pin configurations of built-in PROM version. The One Time PROM version has pin-compatibility with the mask ROM version. Table 16 Product of built-in PROM version Outline 36P2R-A Fig. 35 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) RESET D 1 P40 P41 P42 P43 CNV SS P13 P12 P02 P10 V DD XOUT XIN VSS D 0 P01 P00 P20 P11 P03 P21/INT CARR P32 P31 P30 VDCE M34570ExFP D 3 D 5 D 4 D 7 D 6 D 8 D 9/TOUT D 2 P33

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 36 PROM memory map Fig. 37 Flow of writing and test of the product shipped in blank (1) PROM mode The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 17. Contact addresses at the end of this book for the appropriate PROM programmer.

• Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 36. (2) Notes on handling À A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. \` For the One Time PROM version Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 37 before using is recommended. Table 17 Programming adapter Microcomputer M34570E8FP, M34570EDFP Programming adapter PCA7425 Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Note: Address 000016 1FFF 16 400016 5FFF 16 7FFF 16 1 11 D 4 D 3 D 2 D 1 D 0 High-order 5 bits 1 11 D 4 D 3 D 2 D 1 D 0 Low-order 5 bits The shaded area can be used only for M34570ED. Set “FF16” to the shaded area.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 1. Confirmation Three sets of EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by floppy disk. Ordering by the EPROMs Specify the type of EPROMs submitted (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: [ Customer T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH55-08B <91A0>

4500 SERIES MASK ROM ORDER CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M34570M4-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked [ . 27C256 27C512 Low-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 High-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 000016 0FFF 16 400016 4FFF 16 7FFF 16 4.00K 4.00K Low-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 High-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 000016 0FFF 16 400016 4FFF 16 FFFF 16 4.00K 4.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (36P2R-A for M34570M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. [ 3. Comments Mask ROM numberGZZ-SH55-08B <91A0> SINGLE-CHIP MICROCOMPUTER M34570M4-XXXFP MITSUBISHI ELECTRIC Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall as- sume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code (hexadecimal notation) Mask file name .MSK (equal or less than eight characters)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 1. Confirmation Three sets of EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by floppy disk. Ordering by the EPROMs Specify the type of EPROMs submitted (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: [ Customer T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH55-09B <91A0> SINGLE-CHIP MICROCOMPUTER M34570M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked [ . 27C256 27C512 Low-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 High-order 5-bit data 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 000016 1FFF 16 400016 5FFF 16 7FFF 16 8.00K 8.00K Low-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 High-order 5-bit data 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 000016 1FFF 16 400016 5FFF 16 FFFF 16 8.00K 8.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (36P2R-A for M34570M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. [ 3. Comments Mask ROM numberGZZ-SH55-09B <91A0> SINGLE-CHIP MICROCOMPUTER M34570M8-XXXFP MITSUBISHI ELECTRIC Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall as- sume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code (hexadecimal notation) Mask file name .MSK (equal or less than eight characters)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 1. Confirmation Three sets of EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by floppy disk. Ordering by the EPROMs Specify the type of EPROMs submitted (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: [ Customer T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH55-10B <91A0> SINGLE-CHIP MICROCOMPUTER M34570MD-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked [ . 27C256 27C512 Low-order 5-bit data High-order 5-bit data 0000 16 3FFF 16 4000 16 7FFF 16 16.00K 16.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. Low-order 5-bit data High-order 5-bit data 0000 16 3FFF 16 4000 16 7FFF 16 16.00K 16.00K 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 FFFF 16

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER [ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (36P2R-A for M34570MD-XXXFP) and attach to the Mask ROM Order Confirmation Form. [ 3. Comments Mask ROM numberGZZ-SH55-10B <91A0> SINGLE-CHIP MICROCOMPUTER M34570MD-XXXFP MITSUBISHI ELECTRIC Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall as- sume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code (hexadecimal notation) Mask file name .MSK (equal or less than eight characters)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MARK SPECIFICATION FORM 36P2R-A (36-PIN SHRINK SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi IC catalog name 3 : The standard Mitsubishi font is used for all characters except for a logo. Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, ã,. (periods),, (commas) are usable. Mitsubishi lot number (6-digit or 7-digit) 1 18 1936 Mitsubishi lot number (6-digit or 7-digit) 1 18 1936 1 18 1936

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE SSOP36-P-450-0.80 Weight(g) JEDEC Code 0.53 Alloy 42 36P2R-A Plastic 36pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .814 .28 .6311 .30 .271 .02 .40 .150 .015 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .215 .68 .2312 .70 .150 b2 –. 5 0– 0° –1 0 ° e 36 19 181 H E E D be y F A A2 A1 L c e b2 Recommended Mount Pad Detail F

© 1999 MITSUBISHI ELECTRIC CORP. New publication, effective April. 1999. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 971022

2.0 Main revision points are described below. 990331

• M34570MD-XXXFP and M34570EDFP (ROM expansion products [size: 16K 5 10 bits] ) added.
• SBK and RBK instructions added and TABP p instruction function is expanded. (TABP p instruction: When this instruction is executed after executing the SBK instruction, pages 64 to 127 are specified. When this instruction is executed after executing the RBK in- struction, pages 0 to 63 are specified. When this instruction is executed after system is re- leased from reset and returned from the RAM back-up mode, pages 0 to 63 are specified.)
• BL, BML, BLA and BMLA instructions revised. Referred pages are expanded to pages 0 to 127 (p6 can be used for page specification.) REVISION DESCRIPTION LIST 4570 GROUP DATA SHEET (1/1) Revision Description