4551

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4-BIT SINGLE-CHIP MICROCOMPUTER

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4551 RENESAS

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

DESCRIPTION

The 4551 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with an 8-bit timer with a reload register, a 14-bit timer which is also used as a watchdog timer, a 4-bit timer with a reload register, a carrier wave output circuit and an LCD control circuit. The mask ROM version and built-in PROM version of 4551 Group are produced as shown in the table below.

FEATURES

(f(XIN)=4.0 MHz, VDD =3.0 V, system clock = f(XIN)/4) l Supply voltage l System clock switch function l LCD control circuit l Carrier wave frequency switch function System clock, system clock/2, system clock/8, system clock/12, system clock/16, system clock/24, “H” fixed l Timers l Clock generating circuit (ceramic resonance and quartz-crystal oscillation) APPLICATION Remote control transmitter Product M34551M4-XXXFP M34551E8-XXXFP (Note) ROM type Mask ROM One Time PROM Package 48P6S-A 48P6S-A RAM size (5 4 bits) 280 words 280 words ROM (PROM) size (5 10 bits) 4096 words 8192 words Note: Shipped after writing (shipped in blank: M34551E8FP) PIN CONFIGURATION (TOP VIEW) M34551M4-XXXFP Outline 48P6S-A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 COM 2 COM 3 SEG 0 SEG 1 M34551M4-XXXFP SEG 11 SEG 14 SEG 15 SEG 9 VSS XOUT XIN P10 P11 P12 P13 D 1 D 2 D 3 D 4 P00 P01 P02 P03 D 0 RESET D 7/XCOUT D 6/XCIN CARR VDD CNV SS VSS D 5 / INT COM 1 COM 0 SEG 10 SEG 13 SEG 12 P23 / SEG19 P22 / SEG18 P20 / SEG16 P21 / SEG17 MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER BLOCK DIAGRAM RAM 280 words 4 bits (LCD RAM 20 words 5 4 bits included) ROM (Note) 4096 to 8192 words 10 bits Port P0 Port P1

4500 Series CPU core

Internal peripheral functions LCD drive control circuit (max. 20 segments 4 common) Timers Timer 1 (8 bits) System clock generating circuit Timer 2 (14 bits) X IN OUT (Main clock)X CIN COUT (Sub-clock) Remote control carrier wave output Register B (4 bits) Register A (4 bits)Register D (3 bits) Register E (8 bits) Stack registers SKs (8 levels) Interrupt stack register SDP(1 level) ALU(4 bits) Port D Port P2 Timer LC (4 bits) Segment output Common output Note: PROM 8192 words 5 10 bits

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER PERFORMANCE OVERVIEW Function 1.5 µs (f(XIN) = 8.0 MHz:system clock = f(XIN)/4: VDD = 5.0 V) 4096 words 5 10 bits 8192 words 5 10 bits 280 words 5 4 bits (LCD RAM 20 words 5 4 bits included) Eight independent output ports 4-bit I/O port; each pin is equipped with a pull-up function. 4-bit I/O port; each pin is equipped with a pull-up function. 4-bit input port 1-bit output port (CMOS output) 8-bit timer with a reload register 14-bit timer/ Fixed dividing frequency timer 4-bit timer with a reload register 3 (one for external and two for timer) 1 level 8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction is executed) 1/2, 1/3 bias 2, 3, 4 duty 200 kΩ 5 3 CMOS silicon gate 48-pin plastic molded QFP –20 °C to 70 °C 2.2 V to 5.5 V (One Time PROM version: 2.5 V to 5.5 V) 2.5 mA (f(X IN) = 8.0 MHz system clock = f(XIN)/4, VDD =5 V) 27.5 µA (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 kHz, VDD =5 V) 0.1 µA (at main clock oscillation stop, sub-clock oscillation stop, Ta=25 °C, VDD =5V) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers Interrupt Subroutine nesting LCD Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 7 P00–P03 P10–P13 P20–P23 CARR Timer 1 Timer 2/ Watchdog timer Timer LC Sources Nesting Selective bias value Selective duty value Common output Segment output Internal resistor for power supply at active at clock operating at RAM back-up M34551M4 M34551E8 Output I/O I/O Input Output DEFINITION OF CLOCK AND CYCLE l System clock (STCK) The system clock is the basic clock for controlling this product. The system clock can be selected by bits 0 and 3 of the clock control register MR as shown in the table below. Table Selection of system clock l Instruction clock (INSTK) The instruction clock is the standard clock for controlling CPU. The instruction clock is a signal derived from dividing the system clock by 3. The one cycle of the instruction clock is equivalent to the one machine cycle. l Machine cycle The machine cycle is the standard cycle required to execute the instruction. Note: f(X IN)/4 is selected immediately after system is released from reset. Register MR MR 3 MR 0 System clock (STCK) f(X IN) f(XCIN) f(XIN)/4 f(XCIN)/4

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER PIN DESCRIPTION Name Power supply Ground CNV SS Reset input Main clock input Main clock output Output port D Output port D Output port D Output port D I/O port P0 I/O port P1 Input port P2 Carrier wave output for remote control Segment output Common output Pin V DD VSS CNV SS RESET XIN XOUT D 0–D 4 D 5/INT D 6/XCIN D 7/XCOUT P00–P03 P10–P13 P20/SEG 16– P23/SEG 19 CARR SEG 0–SEG 15 COM 0–COM 3 Input/Output Input I/O Input Output Output I/O I/O Output I/O I/O I/O Output Output Output Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. A pull-up resistor is built-in this pin. When the watchdog timer causes the system to be reset or the low- supply voltage is detected, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. A ceramic resonator can be connected between XIN pin and XOUT pin. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. 1-bit output port. Port D 5 is also used as an INT input pin. When D5/INT pin is used as the INT input pin, set the output latch to “1.” The output structure is N- channel open-drain. Each pin of port D has an independent 1-bit output function. Ports D 6 and D7 are also used as pins XCIN and XCOUT for the sub-clock generating circuit, respectively. When pins D6/XCIN and D7/XCOUT are used as the pins for the sub-clock generating circuit, a 32.0 kHz quartz-crystal oscillator can be connected between XCIN pin and XCOUT pin. A feedback resistor is built-in between them. 4-bit I/O port. It can be used as an input port when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. 4-bit I/O port. It can be used as an input port when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 4-bit input port. Ports P2 0–P2 3 are also used as the segment output pins SEG16– SEG 19, respectively. Carrier wave output pin for remote control transmit. The output structure is the CMOS circuit. LCD segment output pins. LCD common output pins. Pins COM 0 and COM1 are used at 1/2 duty, pins COM0– COM 2 are used at 1/3 duty and pins COM0–COM 3 are used at 1/4 duty.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER MULTIFUNCTION Notes 1: Pins except above have just single function. 2: The port D5 is the output port and ports P20–P2 3 are the input ports. CONNECTIONS OF UNUSED PINS Connection Connect to VSS , or set the output latch to “0” and open. Select ports D6 and D7 and connect to VSS , or set the output latch to “0” and open. Select port P2 and connect to V SS , or select the segment output function and open. Connection Open Open Open Set the output latch to “1” and open. Open or connect to V SS (Note) Pin CARR SEG 0–SEG 15 COM 0–COM 3 P00–P03 P10–P13 Pin D 0–D 4 D 5/INT D 6/XCIN D 7/XCOUT P2 0 /SEG 16 –P2 3 / SEG 19 Pin D 5 D 6 D 7 P20 P21 P22 P23 Multifunction INT XCIN XCOUT SEG 16 SEG 17 SEG 18 SEG 19 Multifunction D 5 D 6 D 7 P20 P21 P22 P23 Pin INT X CIN XCOUT SEG 16 SEG 17 SEG 18 SEG 19 PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Control bits Control instructions SD RD CLD OP0A IAP0 OP1A IAP1 IAP2 Control registers MR PU0 Output structure N-channel open-drain N-channel open-drain N-channel open-drain Input/ Output Output (8) I/O (4) I/O (4) Input (4) Remark Pull-up functions Key-on wakeup functions Pull-up functions (programmable) Key-on wakeup functions (programmable) Pin D 0–D 4, D5/INT, D 6/XCIN, D 7/XCOUT P00–P03 P10–P13 P20/SEG 16– P23/SEG 19 Note: In order to connect ports P10–P1 3 to VSS , turn off their pull-up transistors (Pull-up control register PU0i=“0”) by software. In order to make these pins open, turn on their pull-up transistors (register PU0i=“1”) by software, or turn off their pull-up transistors (register PU0i=“0”) and set the output latch to “0” (i = 0, 1, 2, or 3). Be sure to select the key-on wakeup function and the pull-up function with every one port. (Note in order to set the output latch to “0” and make pins open)

After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note in order to connect unused pins to VSS or VDD )
To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER PORT BLOCK DIAGRAMS D T Q Key-on wakeup input Register A Ai IAP0 instruction Ai Pull-up transistor P00–P03 (Note 1) OP0A instruction D T Q OP1A instruction Key-on wakeup input Register A Ai IAP1 instruction Pull-up transistor Ai P10–P13 PU0i (Note 1) Connected to when selecting SEG LCD power supply LCD power supply L2i Register A IAP2 instruction LCD control signal P20/SEG 16–P23/SEG 19 (Note 1) Register Y Decoder SD instruction RD instruction S RQ CLD instruction D 0–D 4 Register Y Decoder SD instruction RD instruction S R Q CLD instruction D 5/INTINT input (Note 1) (Note 1) This symbol represents a parasitic diode. Notes 1: i represents bit 0, 1, 2 or 3.2: MR 2 MR 2 MR 2 D 7/XCOUT MR 2 D 6/XCIN XCIN clock Register Y Decoder SD instruction RD instruction S RQ CLD instruction Register Y Decoder SD instruction RD instruction S RQ CLD instruction (Note 1) (Note 1)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER PORT BLOCK DIAGRAMS (continued) SEG 0–SEG 15 LCD power supply LCD power supply LCD control signal LCD control signal Pch Nch COM 0–COM 3 LCD control signal LCD control signal Pch LCD control signal LCD control signal Nch Pch Nch LCD power supply LCD power supply LCD power supply This symbol represents a parasitic diode. Note: STCR instruction SPCR instruction S R Q CR flag Carrier wave output circuit Register C1TC1A instruction W3 1 Timer LC underflow signal F/F W3 0 C2 0 Timer 1 underflow signal W2 0 CARR To timer 1 CARRY (Note) F/F

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag (CY) Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2 DR 1 DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 84 0 Middle-order 4 bits Low-order 4 bits Register A (4) Register B (4) The contents of register A Fig. 4 TABP p instruction execution example

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

branching to an interrupt service routine (referred to as an interrupt service routine),
performing a subroutine call, or
executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used when using an interrupt service routine or when executing a table reference instruction. Accordingly, be careful not to stack over when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3- bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. (SP) 0 (SK0) 000116 (PC) SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) (SK0) (SP) 7 Note: SK 0 SK 1 SK 2 SK 3 SK 4 SK 5 SK 6 SK 7 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Program counter (PC) Executing the return or table reference instruction Executing the subroutine call or table reference instruction Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK 0 is destroyed.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register Z (2) Register X (4) Register Y (4)Specifying RAM digit Specifying RAM file Specifying RAM file group p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter (PC) PC H Specifying page PC L Specifying address 01 01 1 Set Specifying bit position Port D output latchRegister Y (4) D 5 D 4 D 0D 6D 7

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER PROGRAM MEMORY (ROM) 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34551E8. Table 1 ROM size and pages Product M34551M4 M34551E8 ROM size (5 10 bits) 4096 words 8192 words Pages 32 (0 to 31) 64 (0 to 63) A top part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. Fig. 10 ROM map of M34551E8 90 87654321 Interrupt address page 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 1FFF 16 018016 Page 1 Page 2 Page 0 Page 3 Page 63 0FFF 16 Page 31 Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure 90 87654321 External 0 interrupt address008016

008416 Timer 1 interrupt address

Timer 2 interrupt address008616 00FF16

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. RAM includes the area corresponding to the LCD. A segment is turned on automatically when “1” is written in the bit corresponding to the segment. Table 2 shows the RAM size. Figure 12 shows the RAM map. Table 2 RAM size Product M34551M4 M34551E8 RAM size 280 words 5 4 bits (1120 bits) Register Y Register Z Register X 0 1 ••• 7 RAM 280 words 5 4 bits (1120 bits) 280 words 012 The area marked “–” (Z = 1, X = 0 to 2, Y = 0 to 7) is not a memory area. The numbers in the shaded area indicate the corresponding segment output pin numbers. Notes 1: Fig. 12 RAM map

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

Interrupt enable flag (INTE) = “1” (Interrupt enabled)
Interrupt enable bit = “1” (Interrupt request occurrence enabled)
An interrupt activated condition is satisfied (request flag = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bits (V1 0–V1 3) Use an interrupt enable bit of interrupt control register V1 to select the corresponding interrupt request or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Priority level Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Skip instruction SNZ0 SNZT1 SNZT2 Request flag EXF0 T1F T2F Enable bit V12 V13 Table 5 Interrupt enable bit function Skip instruction Invalid Valid Interrupt enable bit Occurrence of interrupt request Enabled Disabled

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Program counter (PC)
Stack register (SK)
Interrupt enable flag (INTE)
Interrupt request flag (only the flag for the current interrupt source)
Data pointer, carry flag, registers A and B, skip flag Fig. 13 Program example of interrupt processing (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14).
Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after a branch to a sequence for storing data into stack register is performed. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return to main routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning to the main routine. (Refer to Figure 13) Fig. 14 Internal state when interrupt occurs Fig. 15 Interrupt system diagram EI RTI Interrupt service routine Interrupt occurs Interrupt is enabled Main routine : Interrupt enabled state : Interrupt disabled state T1F V1 2 EXF0 V10 Address 4 in page 1 Address 0 in page 1 T2F V1 3 Address 6 in page 1 Timer 1 underflow Request flag (state retained) Enable bit Enable flagActivated condition INT pin (L → H or H → L input) INTE Timer 2 underflow

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (6) Interrupt control register l Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control register V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V1 at reset : 0000 2 at power down : 00002 R/W Note: “R” represents read enabled, and “W” represents write enabled. (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10–V13), and interrupt request flags (EXF0, T1F, T2F) are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Fig. 16 Interrupt sequence The address is stacked to the last cycle. This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. 2 to 3 machine cycles (Note 1, 2) Software starts from the interrupt address. Flag cleared Interrupt enabled state EI instruction execution cycleInterrupt enable flag (INTE) Retaining level for 4 cycles or more of STCK is necessary. Interrupt disabled state EXF0 flag T1F, T2F flags INT pin External interruptTimer 1 and Timer 2 interrupts Interrupt activated condition is satisfied. l When an interrupt request flag is set after its interrupt is enabled 1 machine cycle System clock (STCK) “H” “L” “1” “0” “1” “0” “1” “0” Notes 1:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER EXTERNAL INTERRUPTS An external interrupt request occurs when a valid waveform (= waveform causing the external 0 interrupt) is input to an interrupt input pin (edge detection). The external 0 interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated condition Name External 0 interrupt Input pin D 5/INT Valid waveform Falling waveform (“H”→ “L”) Rising waveform (“L”→ “H”) Valid waveform selection bit (I12) Fig. 17 External interrupt circuit structure One-sided edge detection circuit EXF0 I12 D 5/INT Skip SNZI0 instruction External 0 interrupt Falling Rising

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. The D 5/INT pin need not be selected the external interrupt input INT function or the normal output port D5 function. However, the EXF0 flag is set to “1” when a valid waveform output from port D 5 is input to INT pin even if it is used as an output port D5. l External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D 5/INT pin. The valid waveform can be selected from rising waveform or falling waveform. An example of how to use the external 0 interrupt is as follows. À Select the valid waveform with the bit 2 of register I1. \` Clear the EXF0 flag to “0” with the SNZ0 instruction. ´ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ˆ Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External interrupt control register l Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Depending on the input state of D 5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction. I13 I12 I11 I10 Not used Interrupt valid waveform for INT pin selection bit (Note 2) Not used Not used This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction) Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt control register I1 R/Wat reset : 00002 at power down : state retained

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER TIMERS The 4551 Group has the programmable timers. l Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). l Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” every n count of a count pulse. Fig. 18 Auto-reload function The 4551 Group timer consists of the following circuits.

Prescaler : frequency divider
Timer 1 : 8-bit programmable timer
Timer 2 : 14-bit fixed dividing frequency timer
Timer LC : 4-bit programmable timer (Timers 1 and 2 have the interrupt function, respectively) Table 9 Function related timers Prescaler, timer 1, timer 2 and timer LC can be controlled with the timer control registers W1, W2 and W3. Each function is described below. Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
Carrier generating circuit output (CARRY, CARRY/2)
Prescaler output (ORCLK)
f(X CIN)
Bit 3 of timer 2
System clock (STCK) Structure Frequency divider 8-bit programmable binary down counter 14-bit fixed dividing frequency 4-bit programmable binary down counter Circuit Prescaler Timer 1 Timer 2 Timer LC Use of output signal
Timer 1 and 2 count sources
Timer 1 interrupt
Port CARR output control
Timer 2 interrupt
Divider for LCD
Watchdog timer
Divider for LCD
Carrier output Frequency dividing ratio 4, 8 1 to 256 16384 1 to 16 Control register FF16 n 0016 n : Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time An interrupt occurs or a skip instruction is executed. Timer 1 interrupt request flag The contents of counter “1” “0”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 19 Timers structure Frequency dividing circuit (divided by 3)XIN XCIN Timer 1 interruptT1F INSTCK ORCLK Carrier wave output control Frequency dividing circuit (divided by 4) Reload register R1 (8) Timer 1 (8) Register BRegister A (T1AB) (TAB1) (Note 1) W2 0 MR0 W1 1, W1 0 00,01 W1 3 W1 2 Prescaler ORCLK MR 3 (Note 2) 1 2 STCK CARRY Count source is stopped by setting to “0.” When the T1AB instruction is executed after setting W2 0 to “1,” data is written only to reload register R1. When the contents of W2 3 changes from “0” to “1,” the count value of timer 2 is initialized. Timer 2 1 2 Timer LC (4) Reload register LC (4) LCD clock Count source ORCLK Timer 2 interruptT2F Count source W2 3 W2 2, W2 1 Not available Q R S WEF Reset signal WRST instruction System reset To port CARR 10,11 (Note 1) W3 0 W3 1 103 25 47 69 81 2 1 310 11 STCK Q D T WDF (Note 3) Notes 1:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Table 10 Timer control registers Prescaler control bit Prescaler dividing ratio selection bit Timer 1 count source selection bits Timer control register W1 W1 3 W1 2 W1 1 W1 0 at reset : 00002 at power down : 00002 R/W Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 8 Count source Prescaler output (ORCLK) Carrier output (CARRY) Carrier output divided by 2 (CARRY/2) W1 1 W1 0 Timer control register W2 at reset : 10002 at power down : – – – 02 R/W f(XCIN) Prescaler output (ORCLK)W2 3 W2 2 W2 1 W2 0 Timer 2 count source selection bit Timer 2 count value selection bits Timer 1 control bit W2 2 W2 1 Count source Underflow occur every 214 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) Operating Timer control register W3 at reset : 002 at power down : state retained R/W Bit 3 of timer 2 is output (timer 2 count source divided by 16) State clock (STCK) Stop (timer LC state retained) Operating W3 0 Timer LC count source selection bit Timer LC control bit Note: “R” represents read enabled, and “W” represents write enabled. “–” represents state retained. (1) Timer control registers l Timer control register W1 Register W1 controls the count source of timer 1, the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. l Timer control register W2 Register W2 controls the count operation of timer 1 and count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. l Timer control register W3 Register W3 controls the count operation and count source of timer LC. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (2) Precautions Note the following for the use of timers. l Prescaler Stop the prescaler operation to change its frequency dividing ratio. l Count source Stop timer 1 or timer LC counting to change its count source. When timer 2 count source changes from f(X CIN) to ORCLK (W2 3 = “0” → W2 3 = “1”), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(X or the same count source is set again (W23 = “0” → W23 = “0” or W23 = “1” → W2 3 = “1”), the count value of timer 2 is not initialized. l Timer 2 Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction. l Reading the count value Stop the prescaler and then execute the TAB1 instruction to read timer 1 data. l Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. (3) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock (INSTCK). Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. When the bit 3 of register W1 is cleared to “0,” prescaler is initialized, and the output signal (ORCLK) stops. (4) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer 1 stops, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer 1 is operating, data can be set only in the reload register (R1) with the T1AB instruction. When setting the next count data to reload register R1 while timer 1 is operating, be sure to set data before timer 1 underflows. Timer 1 starts counting after the following process; À set data in timer 1, \ select the count source with bits 0 and 1 of register W1, ´ set the bit 0 of register W2 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto- reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 to registers A and B. Stop counting and then execute the TAB1 instruction to read its data. (5) Timer 2 (interrupt function) Timer 2 is a 14-bit binary down counter. Timer 2 starts counting after the following process; À select the count source with the bit 3 of register W2, and \ the clock as a count source is supplied. Timer 2 stops counting and its count value is retained when supply of a clock as a count source stops. Timer 2 is initialized at reset and when the count source changes from f(X CIN) (W2 3=“0”) to ORCLK (W23=“1”). The count value to set the timer 2 interrupt request flag (T2F) to “1” can be selected from every 8192 count or every 16384 count with bits 1 and 2 of register W2. The count source signal divided by 16 is output from timer 2. Timer 2 can be used as a counter for clock in the clock operating mode (POF instruction executed). (6) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Timer LC starts counting after the following process; À set data in timer LC, \` select the count source with the bit 1 of register W3, ´ set the bit 0 of register W3 to “1.” Timer LC is the timer for LCD clock generating. Also, it can be used as the multi-carrier generator by setting the bit 1 of register W3 to “1” and selecting the system clock (STCK) as a count source. When the multi-carrier generator is selected, the waveform which is the timer LC underflow signal divided by 2 can be output as a carrier wave from port CARR. At this time, stop the carrier generating circuit and LCD control circuit. When the multi-carrier generator (duty ratio: 1/2 fixed) is used, the enable/stop of the carrier wave output from port CARR can be set by the stop of timer LC or the carrier wave output auto-control function by timer 1. (7) Timer interrupt request flags (T1F and T2F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1 and SNZT2). Use the interrupt control register V1 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of timer 2, watchdog timer enable flag (WEF), and watchdog timer flag (WDF). When the WRST instruction is executed after system is released from reset, the WEF flag is set to “1.” At this time, the watchdog timer starts operating. When the WEF flag is set to “1,” it cannot be cleared to “0” until system reset is performed. Also, when the WRST instruction is not executed once, watchdog timer does not operate because the WEF flag retains “0.” When the watchdog timer is operating, the WDF flag is set to “1” every time the bit 12 of timer 2 is cleared from “1” to “0.” This means that count is performed 8192 times. When the bit 12 of timer 2 is cleared from “1” to “0” while the WDF flag is set to “1,” the internal reset signal is generated and system reset is performed. The WDF flag can be cleared to “0” with the WRST instruction. In the RAM back-up mode, through timer 2 count operation stops, its count value is retained and the WDF flag is initialized. In the clock operating mode, timer 2 count operation is continued and the WDF flag is initialized. When using the watchdog timer, execute the WRST instruction at a certain cycle which consists of timer 2’s 8191 counts or less to keep the microcomputer operation normal. Fig. 20 Watchdog timer function Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer The contents of the WDF flag are initialized in the RAM back-up mode. If the WDF flag is set to “1” at the same time that the microcomputer enters the RAM back-up mode, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF flag with the WRST instruction just before the microcomputer enters the RAM back-up mode (refer to Figure 21).

••• POF2 EPOF ; POF instruction execution enabled (RAM back-up mode)Oscillation stop WRST ; Clear WDF flag 1FFF 16Value of timer 2 Internal reset signal WRST instruction execution System reset WRST instruction execution WEF flag 3FFF 16 0000 16 WDF flag “1” “0” “1” “0” “H” “L”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CARRIER GENERATING CIRCUIT The 4551 Group has a carrier generating circuit that generates the transfer waveform by dividing the system clock (STCK) for each remote control carrier wave. Each carrier waveform can be output by setting the carrier wave selection register (C1). Also, timer 1 can auto-control the carrier wave output from port CARR by setting the carrier wave output control register (C2). Fig. 22 Carrier wave selection register DutyFrequency Carrier waveRegister C1 Setting value No carrier wave “L” fixed C1 0C1 1C1 2 Output waveform STCK/24 STCK/16 STCR instruction SPCR instruction C1 3 STCK/12 STCK/8 STCK (at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W)Carrier wave selection register C1 STCK/2 No available “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” 000 0 000 1 001 0 001 1 010 0 010 1 011 1 100 0 100 1 101 0 101 1 110 0 110 1 011 0 111 0 111 1 “H” “L” Note:“W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Table 11 Carrier generating circuit control register and control flag C2 0 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is validCarrier wave output auto-control bit 0 at reset : 02Carrier wave output control register C2 at power down : 0 2 W CR Carrier wave generating stop (SPCR instruction) Carrier wave generating start (STCR instruction)Carrier wave generating control 0 at reset : 02Carrier wave generating control flag CR at power down : 0 2 W Note: “W” represents write enabled. (1) Carrier generating circuit related registers l Carrier wave selection register C1 Each carrier waveform can be selected by setting the register C1. Set the contents of this register through register A with the TC1A instruction. l Carrier wave output control register C2 Timer 1 can auto-control the output enable interval and the output disable interval of the carrier wave output from port CARR by setting the register C2. Set the contents of this register through register A with the TC2A instruction. The setting of the output enable/disable interval is described below. À Validate the carrier wave output auto-control function (C2 0=“1”). \` Select the carrier wave or the carrier wave divided by 2 as the timer 1 count source. ´ Set the count value (the output enable interval of carrier wave from port CARR) to timer 1. ˆ Operate timer 1 (W2 0=“1”). ˜ Operate the carrier generating circuit (STCR instruction executed). ¯ Set the next count value (the output disable interval of carrier wave from port CARR) to reload register R1 before timer 1 underflow occurs. The carrier wave is output from port CARR until the first timer 1 underflow occurs. The output of the carrier wave from port CARR is disabled and the next count value is loaded from reload register R1 to timer 1 by the first timer 1 underflow. Then, the output of carrier wave is disabled until the second timer 1 underflow. Also, the next enable interval of the carrier wave output can be set by setting the third count value to timer 1 reload register before the second timer 1 underflow occurs. If the carrier wave output auto-control function is invalidated (C2 0=“0”) while the carrier wave output is auto- controlled, the output of port CARR retains the state when the auto-control is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20=“0”). When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto- control of carrier wave output is started again when the next timer 1 underflow occurs. (2) Carrier wave generating control flag (CR) The CR flag is used to control the carrier wave generating operation of the carrier generating circuit. The CR flag is “1” and the carrier wave generating is started by executing the STCR instruction. The CR flag is “0” and the carrier wave generating is stopped by executing the SPCR instruction. The CR flag is “0” at system reset. (3) Note on the carrier generating circuit stop In order to stop the carrier wave which has the cycle longer than that of the instruction clock with the SPCR instruction, stop it at the point when the carrier wave outputs “L” level in the SPCR instruction execution cycle. If this condition is not satisfied, the last “H” output interval of carrier wave is shortened. (4) Notes when using the carrier wave output auto-control function l Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation. l Stop the timer 1 (W2 0=“0”) after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. l If the carrier wave output auto-control function is invalidated (C2 0=“0”) while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto- control is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20=“0”). When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. l Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto- control function is selected. If the ORCLK is used as the count source, a hazard may occur in port CARR output because ORCLK is not synchronized with the carrier wave.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 23 Carrier wave output auto-control by timer 1 Timer 1 underflow Port CARR output s (C20)← 0 Register C20 s (C20)← 1 s (C20)← 0 s (C20)← 1 a b c s Set the interval “a” to timer 1. s Set the interval “b” to reload register R1. s Set the interval “c” to reload register R1. s Set the interval “d” to reload register R1. d Timer 1 underflow Port CARR output (C20)← 1 Carrier wave output start Timer 1 starts Carrier wave output start “H” “L” “1” “0” “1” “0” “H” “L” “1” “0”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER LCD FUNCTION The 4551 Group has an LCD (Liquid Crystal Display) controller/ driver. When proper voltage is applied to the LCD power supply input pins and data are set in timer control registers (W2, W3), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. When the required number of segment pins is 19 or less, pins SEG 16–SEG 19 (4) can be used as input ports P20–P2 3. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. l 1/2 duty, 1/2 bias l 1/3 duty, 1/3 bias l 1/4 duty, 1/3 bias Table 12 Duty and maximum number of displayed pixels (2) LCD clock control The LCD clock is determined by the timer 2 count source selection bit (W2 3), timer LC control bit (W30), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers (À to ˜ ) shown below the formula correspond to numbers in Figure 24, respectively. l When using the prescaler output (ORCLK) as timer 2 count source (W23=“1”) F = ORCLK 5 55 l When using the f(XCIN) as timer 2 count source (W23=“0”) F = f(XCIN) 5 55 [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = (Hz) Frame period = (s) F: LCD clock frequency 1/n: Duty Fig. 24 LCD clock control circuit structure Duty Used COM pins COM 0, COM 1 (Note) COM 0–COM 2 (Note) COM 0–COM 3 Maximum number of displayed pixels 40 segments 60 segments 80 segments Note: Leave unused COM pins open. LC + 1 À\ ´ ˆ ˜ LC + 1 À\ ´ ˆ ˜ F n n F Note: Count source is stopped by clearing to “0.” À \` ˆ ˜ Timer LC 1/2 W3 0 (Note) XCIN W2 3 1ORCLK STCK W3 1 LCD clock

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 25 LCD controller/driver structure Common driver COM 0 COM 1 COM 2 COM 3 Bias control Multiplexer VLC3 Control signal SEG 0 P20/SEG 16 P23/SEG 19 Multiplexer Selector Segment driver Selector Segment driver SEG 15 RAM RAMDecoder 1/2, 1/3, 1/4 Counter L13 L12 L11 L10 LCD on/off control LCD clock (from timer block) Selector Segment driver RAM L23 L22 L21 L20 Register A ... (Note) – – Note: VLC3 =V DD . ... ...

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lV LC3 l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes V LC3 level (=VDD ). Fig. 26 LCD RAM map Table 13 LCD control registers Not used LCD on/off bit LCD duty and bias selection bits LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained R/W This bit has no function, but read/write is enabled Off On Not available L11 L10 Duty Bias LCD control register L2 at reset : 11112 at power down : state retained W SEG 19 P23 SEG 18 P22 SEG 17 P21 SEG 16 P20 L23 L22 L21 L20 P23/SEG 19 pin function switch bit P22/SEG 18 pin function switch bit P21/SEG 17 pin function switch bit P20/SEG 16 pin function switch bit Note: “R” represents read enabled, and “W” represents write enabled. Z X Y Bit COM 012 3 210 3 210 3 210 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 3 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 2 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 1 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 COM 0 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 SEG 0 SEG 0 SEG 0 SEG 8 SEG 17 SEG 18 SEG 19 SEG 16SEG 8 SEG 8 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 17 SEG 18 SEG 19 SEG 16 SEG 17 SEG 18 SEG 19 SEG 16 SEG 17 SEG 18 SEG 19 SEG 16 Note: The area marked “ ” is not the LCD display RAM.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 27 LCD controller/driver structure 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM. COM 1 COM 0 SEG 16 VLC 3 VLC 1=VLC 2 VSS VLC 3 VLC 1=VLC 2 VSS 1 frame (2/F) 1/F ON OFF Voltage level (bit 0)COM 0 COM 1 SEG 16 X X (bit 3) M (1, 2, 8) COM 1 SEG 16 COM 0 SEG 16 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM. 1 frame (3/F) 1/F ON OFF ON COM 2 VLC 3 VLC 2 VLC 1 VSS COM 1 COM 0 SEG 16 VLC 3 VLC 2 VLC 1 VSS Voltage level (bit 0)COM 0 COM 1 COM 2 SEG 16 X (bit 3) M (1, 2, 8) COM 2 SEG 16 COM 1 SEG 16 COM 0 SEG 16 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM. 1 frame (4/F) 1/F ON OFF ON COM 3 COM 2 COM 1 COM 0 SEG 16 VLC 3 VLC 2 VLC 1 VSS VLC 3 VLC 2 VLC 1 VSS OFF Voltage level (bit 0)COM 0 COM 1 COM 2 COM 3 SEG 16 (bit 3) M (1, 2, 8) COM 3 SEG 16 COM 2 SEG 16 COM 1 SEG 16 COM 0 SEG 16 F: LCD clock frequency X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Note: Keep the value of supply voltage the minimum value or more of the recommended operating conditions. RESET Software start (Address 0 in page 0) Reset input 1machine cycle or more 0.3VDD f(XIN) is counted 10757 to 10786 times (Note) 0.85VDD System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied;

the value of supply voltage is the minimum value or more of Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. VDD Power-on reset circuit output voltage Internal reset signal Power-on RESET pin WEF Watchdog timer output Internal reset signal Reset state Reset released This symbol represents a parasitic diode. Note: Applied potential to RESET pin must be V DD or less. (Note) Power-on reset circuit Pull-up transistor Voltage drop detection circuit f(XIN) RESET f(XIN) is counted 10757 to 10786 times Software start (Address 0 in page 0) Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed. (Note) “H” “L” Fig. 28 Reset release timing Fig. 29 RESET pin input waveform and reset operation (1) Power-on reset Reset can be automatically performed at power on (power- on reset) by the built-in power-on reset circuit. When the built- in power-on reset circuit is used, the time for the supply voltage to reach the minimum operating voltage must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Fig. 30 Power-on reset circuit example

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Address 0 in page 0 is set to program counter. (2) Internal state at reset Table 14 shows port state at reset, and Figure 31 shows internal state at reset (they are retained after system is released from reset). Name D 0–D 4, D5/INT D 6/XCIN, D7/XCOUT P00–P0 3 P10–P1 3 P20/SEG 16–P23/SEG 19 SEG 0–SEG 15 COM 0–COM 3 CARR State High impedance (Note 1) “H” (VDD ) level (Note 1) (Notes 1, 2) High impedance VLC3 (VDD ) level “L” (VSS ) level Function D 0–D 4, D5 D 6, D7 P00–P03 P10–P13 P20–P23 SEG 0–SEG 15 COM 0–COM 3 CARR Notes 1: Output latch is set to “1.” 2: The pull-up transistor is turned off. Table 14 Port state at reset The contents of timers, registers, flags and RAM except those shown in Figure 31 are undefined, so set the initial values to them. 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0 0 0 0 (Prescaler stopped) 0 0 0 0 (Timer 1 stopped) 0 0 (Timer LC stopped) 1000 0111 0 (Carrier wave output disabled) 0 0 0 0 (LCD off) 1 1 1 1 (Port P2 selected) 0000 0000 0000 0000 555 0000 0000 111 “5 ” represents undefined. Fig. 31 Internal state at reset 55555555

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 32 Voltage drop detection reset circuit Fig. 33 Voltage drop detection circuit operation waveform RESET pin WEF Watchdog timer output Internal reset signal Power-on reset circuit Pull-up transistor Voltage drop detection circuit Internal reset signal VDD Detection voltage The microcomputer starts operation after the f(X IN) is counted 10757 to 10786 times. Voltage drop detection circuit Operating Voltage drop detection circuit Stop Voltage drop detection circuit Operating Voltage drop detection circuit Stop Voltage drop detection circuit Operating “H” “L”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER POWER DOWN FUNCTION The 4551 Group has 2-type power down functions. Power down is performed by executing each instruction. Above power down functions are different from reset in start conditions. Table 15 shows the function and states retained at power down. Figure 36 shows the state transition. (1) Clock operating mode The following functions and states are retained. l RAM l Reset circuit l XCIN–XCOUT oscillation l LCD display l Timer 2 (2) RAM back-up mode The following functions and states are retained. l RAM l Reset circuit Unlike the clock operating mode, all oscillations stop in the RAM back-up mode. (3) Warm start condition The system returns from the power down state when; l the external wakeup signal is input or the timer 2 underflow occurs in the clock operating mode, or when; l the external wakeup signal is input in the RAM back-up mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (4) Cold start condition The CPU starts executing the software from address 0 in page 0 when; l reset pulse is input to RESET pin, or l reset by watchdog timer is performed. In this case, the P flag is “0.” Table 15 Functions and states retained at power down Power down RAM back-up O O O O O (Note 3) O (Note 4) O O O Clock operating O O O O O O O O O O O O Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Clock control register MR Timer control register W1 Timer control registers W2, W3 Interrupt control register V1 Interrupt control register I1 Carrier wave control registers and flag (C1, C2, CR) LCD display function LCD control registers L1, L2 Timer LC Timer 1 function Timer 2 function External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Watchdog timer flag (WDF) Watchdog timer enable flag (WEF) Interrupt enable flag (INTE) General-purpose register V2 Notes 1: “O” represents that the function can be retained, and “5 ” represents that the function is initialized. Registers and flags other than the above are undefined at power down, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “1112” at power down. 3: LCD is turned off. 4: The state of the timer is undefined.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition (timer 2 or external wakeup signal) can be identified by examining the state of T2F flag. Fig. 34 Set source and clear source of the P flag l Set source POF or POF2 instruction executed l Clear source Reset input S R Q Powerdown flag PPOF instruction or POF2 instruction Reset input Software start P = “1” T2F = “1” No Yes Yes Return by external wakeup signal Return by timer 2 underflow Cold start No Fig. 35 Start condition identified example using the SNZP instruction (6) Return signal An external wakeup signal or timer 2 interrupt request flag is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source. (7) Port P1 control register l Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P1 pull-up transistor and the ON/OFF of the key-on wakeup function. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 16 Return source and return condition Remarks Port P0 shares the falling edge detection circuit with port P1. The key-on wakeup function of port P0 is always valid. The only key-on wakeup function of the port P1 bit of which the pull-up transistor is turned on is valid. Set all the port using the key-on wakeup function to “H” level before going into the power down state. The timer 2 interrupt request flag (T2F) can be used only when system returns from the clock operating mode (POF instruction execution). However, if the POF and POF2 instructions are executed while the T2F = “1”, its operation is recognized as the return condition and system returns from the clock operating mode. Return condition Returns by an external falling Returns by timer 2 underflow and setting T2F to “1.” Return source Ports P0, P1 Timer 2 interrupt request flagExternal wakeup signal Note: P1 pin has the pull-up transistor which can be turned on/off by software. Table 17 Pull-up control register Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Port P1 3 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P1 0 pull-up transistor control bit at reset : 00002 at power down : state retainedPull-up control register PU0 R/W PU0 3 PU0 2 PU0 1 PU0 0 Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (8) State transition State transition is described using Figure 36. Fig. 36 State transition MR 0 ← B MR 0 ← C MR 1 ← MR 1 ← D K A MR 2 ← MR 0 ← F MR 0 ← G MR 1 ← MR 1 ← H MR 2 ← E MR 2 ← MR 3 ← 1 MR 3 ← 0 MR 3 ← 1 MR 3 ← 0 MR 3 ← 1 MR 3 ← 0 MR 3 ← 1 MR 3 ← 0 (Note 2) (Note 2) (Stabilizing time c ) (Stabilizing time c ) J f(XIN):Stop f(XCIN) : Oscillation I (Stabilizing time c ) (Stabilizing time c ) (Stabilizing time d ) (Stabilizing time d ) B , F C , G D , H B , F C , G D , H A , E A , E B , F C , G D , H B , F C , G D , H A , E (Note 2) Reset POF execution Return input 1 (Stabilizing time a ) POF execution Return input 1, 2 (Stabilizing time a ) POF execution Return input 1, 2 (Stabilizing time c ) (Note 1) Clock operating mode POF execution Return input 1, 2 (Stabilizing time c ) (Note 1) f(XIN):Stop f(XCIN):Stop Clock operating mode f(XIN):Oscillation f(XCIN):Stop System clock; f(XIN)/4 MR=(1000 2) MR 2 ← f(XIN):Oscillation f(XCIN):Oscillation f(XIN):Oscillation f(XCIN):Oscillation f(XIN):Stop f(XCIN):Oscillation System clock; f(X IN)/4 MR=(1100 2) System clock; f(X CIN)/4 MR=(1101 2) System clock; f(X CIN)/4 MR=(1111 2) f(XIN):Oscillation f(XCIN):Stop System clock; f(X IN) MR=(0000 2) f(XIN):Oscillation f(XCIN):Oscillation System clock; f(X IN) MR=(0100 2) f(XIN):Oscillation f(XCIN):Oscillation System clock; f(X CIN) MR=(0101 2) f(XIN):Stop f(XCIN):Oscillation System clock; f(X CIN) MR=(0111 2) (Stabilizing time d ) (Stabilizing time d ) (Note 2) POF2 execution Return input 1 (Stabilizing time a ) POF2 execution Return input 1 (Stabilizing time a ) POF2 execution Return input 1 (Stabilizing time b ) POF2 execution Return input 1 (Stabilizing time b ) f(XIN):Stop f(XCIN):Stop RAM back-up mode Stabilizing time a : An interval required to stabilize the f(X IN) oscillation is automatically generated by hardware. Stabilizing time b : An interval required to stabilize the f(XCIN) oscillation is automatically generated by hardware. Stabilizing time c : Generate an interval required to stabilize the f(XIN) oscillation in state C or G by software at the transition D→ C, D→ G, H→ C, H→ G, J→ C, or J→ G. Stabilizing time d : Generate an interval required to stabilize the f(XCIN) oscillation in state B, F by software at the transition A→ B, E→ F, A→ F, or E→ B. Return input 1: External wakeup signal (P00–P03, P10–P13) Return input 2: Timer 2 interrupt request flag Notes 1. MR3=“1”→ The microcomputer starts its operation after counting f(XCIN) clock signal 59 to 70 times. MR3=“0”→ The microcomputer starts its operation after counting f(XCIN) clock signal 32 to 43 times. 2. When the following 2 conditions are satisfied, the transition A→ E, B→ F, A→ F, C→ F, G→ F represented by “ ” can be executed. (1) V (2) VDD = 4.5 V to 5.5 V, f(XIN) ≤ 2.0 MHz A , E MR 2 ← 0 MR 3 ← 0 MR 2 ← 1 MR 3 ← 1 (Note 2) MR 2 ← 1 MR 2 ← 0 MR 3 ← 0 MR 3 ← 1 MR 3 ← 1 MR 0 ← 0 MR 3 ← 0 MR 0 ← 1 MR 0 ← 1 MR 0 ← 0 MR 3 ← 1 MR 3 ← 0 MR 3 ← 1 MR 1 ← 0 MR 3 ← 0 MR 1 ← 1 MR 1 ← 0 MR 3 ← 0 MR 1 ← 1 MR 3 ← 1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CLOCK CONTROL The clock control circuit consists of the following circuits. l Clock generating circuit l Control circuit to stop the clock oscillation l System clock (STCK) selection circuit l Instruction clock (INSTCK) generating circuit l Control circuit to return from the power down state Fig. 37 Clock control circuit structure (1) Clock control register l Clock control register MR Register MR controls the system clock. Set the contents of this register through register A with the TMRA OSC XIN XOUT OSC XCIN XCOUT Internal clock generating circuit (divided by 3) MR0 R S Q R S Q POF instruction POF2 instruction MR1 T2F flag Falling detected Ports P0, P1 RESET Multiplexer Frequency dividing circuit (divided by 4) MR3 STCK INSTCK instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 18 Clock control register System clock (STCK) selection bit f(XCIN) oscillation circuit control bit f(XIN) oscillation circuit control bit Clock selection bit at reset : 10002 at power down : state retainedClock control register MR R/W MR 3 MR 2 MR 1 MR 0 MR 0=0 f(XIN) MR 0=1 f(XCIN) MR 0=0 f(XIN)/4 MR 0=1 f(XCIN)/4 f(XCIN) oscillation stop, ports D6 and D7 selected f(XCIN) oscillation enabled, ports D6 and D7 not selected Oscillation enabled Oscillation stop f(XIN) f(XCIN) Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 38 Ceramic resonator external circuit (2) f(XIN) clock generating circuit Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT . (3) f(XCIN) clock generating circuit Clock signal f(XCIN) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT . ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) M34551M4-XXXFP Mask ROM Order Confirmation Form (three sets containing the identical data) M34551 XIN XOUT Rd C IN C OUT Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. Note: Fig. 39 Quartz-crystal oscillator external circuit M34551 XCIN XCOUT Rd C IN C OUT Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal oscillator manufacturer’s recommended value because constants such as capacitance depend on the quartz-crystal oscillator. Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER LIST OF PRECAUTIONS À Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
equalize its wiring in width and length, and
use the thickest wire. In the built-in PROM version, CNV SS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS / VPP pin as close as possible). \` Prescaler Stop the prescaler operation to change its frequency dividing ratio. ´ Count source Stop timer 1 or timer LC counting to change its count source. When timer 2 count source changes from f(X CIN) to ORCLK (W2 3 = “0” → W23 = “1”), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(X CIN) (W23 = “1” → W2 3 = “0”) or the same count source is the count value of timer 2 is not initialized. ˆ Timer 2 Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction. ˜ Reading the count value Stop the prescaler and then execute the TAB1 instruction to read timer 1 data. ¯ Writing to reload register R1 Write the data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. ˘ Notes when using the carrier wave output auto-control function
Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation.
Stop the timer 1 (W2 0=“0”) after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation.
If the carrier wave output auto-control function is invalidated (C2 0=“0”) while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto- control is invalidated regardless of timer 1 underflow. This state is released by timer 1 stop (W20=“0”). When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated (C20=“0”), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur.
Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto- control function is selected. If the ORCLK is used as the count source, a hazard may occur in port CARR output because ORCLK is not synchronized with the carrier wave. ˙ D 5/INT pin When the interrupt valid waveform of D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes.
Clear the bit 0 of register V1 to “0” and then change the interrupt valid waveform of D5/INT pin with the bit 2 of register I1 (refer to Figure 40À ).
Clear the bit 2 of register I1 to “0” and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 40\ ). Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. LA 4 ; ( 555 02) TV1A ; The SNZ0 instruction is valid À LA 4 TI1A ; Change of the interrupt valid waveform NOP \ SNZ0 ;The SNZ0 instruction is executed NOP 5 : this bit is not related to the setting of INT. ... ... ¨ One Time PROM version The operating power voltage of the One Time PROM version is within the range of 2.5 V to 5.5 V. É Multifunction Note that the port D 5 output function can be used even when INT function is selected. Power down instruction (POF instruction, POF2 instruction) Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. Fig. 40 External 0 interrupt program example

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PC L) ← (DR 2–DR 0, A3–A0) (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A)AND(M(DP)) (A) ← (A)OR(M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 LIST OF INSTRUCTION FUNCTION Grouping GroupingMnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Register to register transferRAM addressesRAM to register transfer Arithmetic operation RAM to register transfer Bit operation Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PC L) ← (DR 2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Grouping Comparison operationBranch operationSubroutine operationReturn operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Interrupt operation Function (TLC) ← (A) (RLC) ← (A) (T1F) = 1 ? After skipping the next instruction, (T1F) ← 0 (T2F) = 1 ? After skipping the next instruction, (T2F) ← 0 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (PU0) ← (A) (A) ← (PU0) (L1) ← (A) (A) ← (L1) (L2) ← (A) Mnemonic TLCA SNZT1 SNZT2 IAP0 OP0A IAP1 OP1A IAP2 CLD RD SD TPU0A TAPU0 TL1A TAL1 TL2A Timer operation Timer operationInput/Output operationLCD control operation Function (C1) ← (A) Carrier wave generating start Carrier wave generating stop (C20) ← (A0) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode Power down instruction (POF, POF2) valid (P) = 1 ? WDF ) ← 0, (WEF ) ← 1 (A) ← (MR) (MR) ← (A) (A) ← (V2) (V2) ← (A) GroupingMnemonic TC1A STCR SPCR TC2A NOP POF POF2 EPOF SNZP WRST TAMR TMRA TAV2 TV2A Carrier wave generating operationOther operation Function (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping the next instruction, (EXF0) ← 0 (A) ← (V1) (V1) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) at timer 1 stop (W2 0=0) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) At timer 1 operating (W2 0=1), (R17–R1 4) ← (B) (R13–R1 0) ← (A) Mnemonic DI EI SNZ0 SNZI0 TAV1 TV1A TAI1 TI1A TAW1 TW1A TAW2 TW2A TAW3 TW3A TAB1 T1AB Grouping Grouping

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER INSTRUCTION CODE TABLE Hex. notation D 9–D 4 000000 D 3– D 0 000001 000010000011000100000101000110 000111001000 001001001010001011 001100001101001110001111 010000 010111 011000 011111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F NOP POF SNZP DI EI RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY SZB SEAn SEAM TDA TABE SZC BMLA SNZ0 TV1A RT RTS RTI TASP TAD TAX TAZ TAV1 EPOF LZ LZ LZ LZ RB RB RB RB SB SB SB SB 05 06 07 08 09 0A A A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML 0C 0D BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0E 0F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 10–17 B B B B B B B B B B B B B B B B 18–1F SZB SZB SZB The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. * cannot be used at M34551M4. BL BML BLA BMLA SEA SZD The second word 1 0 p a a a a a a a 1 0 p a a a a a a a 1 0 p p 0 0 p p p p 1 0 p p 0 0 p p p p 0 0 0 1 1 1 n n n n 0 0 0 0 1 0 1 0 1 1 SNZI0 TV2A TAV2 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP POF2 TABP 32* TABP 48* TABP 33* TABP 49* TABP 34* TABP 50* TABP 35* TABP 51* TABP 36* TABP 52* TABP 37* TABP 53* TABP 38* TABP 54* TABP 39* TABP 55* TABP 40* TABP 56* TABP 41* TABP 57* TABP 42* TABP 58* TABP 43* TABP 59* TABP 44* TABP 60* TABP 45* TABP 61* TABP 46* TABP 62* TABP 47* TABP 63* BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER INSTRUCTION CODE TABLE (CONTINUED) Hex. notation D 9–D 4 100000 D 3– D 0 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111 110000 111111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F TW1A TW2A TI1A OP0A 22 23 24 TAI1 TAW1 TAW2 25 26 27 28 29 2A IAP0 IAP1 SNZT2 TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI 2E 2F LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY 30–3F OP1A SNZT1 WRST TMA TAM XAM XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD IAP2 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 1 0 p a a a a a a a 1 0 p a a a a a a a 1 0 p p 0 0 p p p p 1 0 p p 0 0 p p p p 0 0 0 1 1 1 n n n n 0 0 0 0 1 0 1 0 1 1 TPU0A T1AB TAB1– TMRA TAMR TAPU0 TW3A TL1A TL2A TAL1 TLCA TAW3 STCR TC1A SPCR TC2A –– – –––

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Register to register transferRAM addresses MACHINE INSTRUCTIONS TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Continuous (Y) = 0 (Y) = 15 Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Transfers the contents of register D to register A. Transfers the contents of register Z to register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER RAM to register transferArithmetic operation TAM j XAM j XAMD j XAMI j TMA j LA n TABP p (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (Note) 2C j 2D j 2F j 2E j 2B j 07 n 08 p 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 000111nnnn 0010p 5 p4 p3 p2 p1 p0 Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551E8. MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (Y) = 15 (Y) = 0 Continuous After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Arithmetic operationBit operation Comparison operation AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn 00A 00B 06n 018 019 007 006 02F 01C 01D 05 C 04 C 02 j 02 6 02 5 07 n (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A)AND(M(DP)) (A) ← (A)OR(M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Performs the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Performs the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets carry flag CY to “1.” Clears carry flag CY to “0.” Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit. Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “1.” Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “0.” Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Branch operationSubroutine operationReturn operation B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000010000 10p 5 p4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000110000 10p 5 p4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 18 a 0E p 2p a 01 0 2p p 1a a 0C p 2pa 03 0 2p p 04 6 04 4 04 5 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (Note) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (Note) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551E8. MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Skip unconditionally Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and

A in page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Interrupt operation MACHINE INSTRUCTIONS (CONTINUED) DI EI SNZ0 SNZI0 TAV1 TV1A TAI1 TI1A SNZT1 SNZT2 TAW1 TW1A TAW2 TW2A TAW3 TW3A 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 1001010011 1000010111 1010000000 1010000001 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 00 4 00 5 03 8 03 A 054 03F 253 217 280 281 24B 20E 24C 20F 24D 210 (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping the next instruction, (EXF0) ← 0 (A) ← (V1) (V1) ← (A) (A) ← (I1) (I1) ← (A) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) Timer operation

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (EXF0) = 1 (INT) = “H” However, I12 = 1 (INT) = “L” However, I12 = 0 (T1F) = 1 (T2F) =1 Clears the interrupt enable flag INTE to “0,” and disables the interrupt. Sets the interrupt enable flag INTE to “1,” and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is “1.” After skipping, clears the EXF0 flag to “0.” When bit 2 (I1 2) of register I1 is “1” : Skips the next instruction when the level of INT pin is “H.” When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears T1F flag. Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears T2F flag. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER TAB1 T1AB TLCA IAP0 OP0A IAP1 OP1A IAP2 CLD RD SD TPU0A TAPU0 Timer operation 1001110000 1000110000 1000001101 1001100000 1000100000 1001100001 1000100001 1001100010 0000010001 0000010100 0000010101 1000101101 1001010111 270 230 20D 260 220 261 221 262 011 014 015 22D 257 (B) ← (T1 7–T14) (A) ← (T13–T10) At timer 1 stop (W20=0), (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) At timer 1 operating (W20=1), (R17–R1 4) ← (B) (R13–R1 0) ← (A) (TLC) ← (A) (RLC) ← (A) (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A) ← (P2) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 9 (D(Y)) ← 1 (Y) = 0 to 9 (PU0) ← (A) (A) ← (PU0) MACHINE INSTRUCTIONS (CONTINUED) Input/Output operation

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Transfers the contents of timer 1 to registers A and B. When stopping (W2 0=0), transfers the contents of registers A and B to timer 1 and timer 1 reload register. When operating (W20=1), transfers the contents of registers A and B only to timer 1 reload register. Transfers the contents of register A to timer LC and timer LC reload register. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Sets port D to “1.” Clears a bit of port D specified by register Y to “0.” Sets a bit of port D specified by register Y to “1.” Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A.

D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation Type of instructions Parameter Number of words Number of cycles Instruction code MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER TL1A TAL1 TL2A TC1A STCR SPCR TC2A NOP POF POF2 EPOF SNZP WRST TAMR TMRA TAV2 TV2A 1000001010 1001001010 1000001011 1010101000 1010011000 1010011001 1010101001 0000000000 0000000010 0000001000 0001011011 0000000011 1010100000 1001010010 1000010110 0001010101 0000111110 20A 24A 20B 2A8 298 299 2A9 000 002 008 05 B 003 2A0 252 216 055 03E (L1) ← (A) (A) ← (L1) (L2) ← (A) (C1) ← (A) Carrier wave generating start Carrier wave generating stop (C2 0) ← (A0) (PC) ← (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode Power down instruction (POF, POF2) valid (P) = 1 ? (WDF) ← 0, (WEF) ← 1 (A) ← (MR) (MR) ← (A) (A) ← (V2) (V2) ← (A) MACHINE INSTRUCTIONS (CONTINUED) LCD control operation Other operation Carrier generating circuit operation

Skip condition Detailed description Carry flag CY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER (P) = 1 Transfers the contents of register A to LCD control register L1. Transfers the contents of register L1 to register A. Transfers the contents of register A to LCD control register L2. Transfers the contents of register A to carrier wave selection register C1. Starts generating carrier wave. Stops generating carrier wave. Transfers the contents of register A to carrier wave output control register C2. No operation Puts the system in clock operating mode state by executing the POF instruction after executing the EPOF instruction. f(X CIN) oscillation, LCD, timer LC and timer 2 are operated. Puts the system in RAM back-up mode state by executing the POF2 instruction after executing the EPOF instruction. Oscillation is stopped. Validates the power down instruction (POF, POF2) which is executed after the EPOF instruction by executing the EPOF instruction. Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. Operates the watchdog timer and initializes the watchdog timer flag (WDF). Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR. Transfers the contents of general-purpose register V2 to register A. Transfers the contents of register A to general-purpose register V2.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER SYMBOL The symbols shown below are used in the following list of instruction function and machine instructions. Symbol A B DR E CR PU0 MR X Y Z DP PC PC H PC L SK SP CY RLC STCK INSTK TLC T1F T2F

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) General-purpose register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (2 bits) Carrier wave selection register C1 (4 bits) Carrier wave output control register C2 (1 bit) Carrier wave generating control flag LCD control regiser L1 LCD control register L2 Pull-up control register PU0 (4 bits) Clock control register MR (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 5 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer LC reload register System clock Instruction clock Timer 1 Timer 2 Timer LC Timer 1 interrupt request flag Timer 2 interrupt request flag External 0 interrupt request flag Power down flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Symbol WDF INTE EXF0 P D x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4551 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CONTROL REGISTERS V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V1 at reset : 0000 2 at power down : 00002 R/W Prescaler control bit Prescaler dividing ratio selection bit Timer 1 count source selection bits Timer control register W1 W1 3 W1 2 W1 1 W1 0 at reset : 00002 at power down : 00002 R/W Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 8 Count source Prescaler output (ORCLK) Carrier output (CARRY) Carrier output divided by 2 (CARRY/2) W1 1 W1 0 Timer control register W2 at reset : 10002 at power down : – – – 02 R/W f(XCIN) Prescaler output (ORCLK)W2 3 W2 2 W2 1 W2 0 Timer 2 count source selection bit Timer 2 count value selection bits Timer 1 control bit W2 2 W2 1 Count source Underflow occur every 214 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) Operating Timer control register W3 at reset : 002 at power down : state retained R/W Bit 3 of timer 2 is output (timer 2 count source divided by 16) State clock (STCK) Stop (timer LC state retained) Operating W3 0 Timer LC count source selection bit Timer LC control bit Note: “R” represents read enabled, and “W” represents write enabled. “–” represents state retained.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CONTROL REGISTERS (CONTINUED) I13 I12 I11 I10 Not used Interrupt valid waveform for INT pin selection bit (Note 2) Not used Not used This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction) Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt control register I1 R/Wat reset : 00002 at power down : state retained Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Port P1 3 pull-up transistor control bit Port P12 pull-up transistor control bit Port P1 1 pull-up transistor control bit Port P10 pull-up transistor control bit at reset : 00002 at power down : state retainedPull-up control register PU0 R/W PU0 3 PU0 2 PU0 1 PU0 0 System clock (STCK) selection bit f(XCIN) oscillation circuit control bit f(XIN) oscillation circuit control bit Clock selection bit at reset : 10002 at power down : state retainedClock control register MR R/W MR 3 MR 2 MR 1 MR 0 MR 0=0 f(XIN) MR 0=1 f(XCIN) MR 0=0 f(XIN)/4 MR 0=1 f(XCIN)/4 f(XCIN) oscillation stop, ports D6 and D7 selected f(XCIN) oscillation enabled, ports D6 and D7 not selected Oscillation enabled Oscillation stop f(XIN) f(XCIN) Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER C1 3 C1 2 C1 1 C1 0 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 CONTROL REGISTERS (CONTINUED) at reset : 01112 at power down : 01112Carrier wave selection register C1 W Carrier wave frequency STCK/24 STCK/24 STCK/16 STCK/16 STCK/2 No carrier wave Not available “L” fixed STCK/12 STCK/12 STCK/8 STCK/8 STCK No carrier wave Not available “L” fixed Duty Carrier wave selection bits C2 0 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is validCarrier wave output auto-control bit 0 at reset : 02Carrier wave output control register C2 at power down : 0 2 W CR Carrier wave generating stop (SPCR instruction) Carrier wave generating start (STCR instruction)Carrier wave generating control 0 at reset : 02Carrier wave generating control flag CR at power down : 0 2 W Note: “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CONTROL REGISTERS (CONTINUED) Not used LCD on/off bit LCD duty and bias selection bits LCD control register L1 L13 L12 L11 L10 at reset : 00002 at power down : state retained R/W This bit has no function, but read/write is enabled Off On Not available L11 L10 Duty Bias LCD control register L2 at reset : 11112 at power down : state retained W SEG 19 P23 SEG 18 P22 SEG 17 P21 SEG 16 P20 L23 L22 L21 L20 P23/SEG 19 pin function switch bit P22/SEG 18 pin function switch bit P21/SEG 17 pin function switch bit P20/SEG 16 pin function switch bit 4-bit general-purpose register. The data transfer between register A and this register is performed with the TV2A and TAV2 instructions. at reset : 00002General-purpose register V2 at power down : 0000 2 R/W Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Min. 2.2 2.5 4.5 2.0 0.8VDD 0.7VDD 0.85VDD 0.8VDD –30 –15 –15 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage P0, P1, P2, RESET , XIN, XCIN Output voltage P0, P1, D Output voltage CARR, X OUT , XCOUT Output voltage SEG, COM Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Symbol V DD VI VO VO VO Pd Topr Tstg Ratings –0.3 to 7.0 –0.3 to V DD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 70 –40 to 125 Unit V V V V V mW RECOMMENDED OPERATING CONDITIONS (Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Parameter Supply voltage RAM back-up voltage Supply voltage “H” level input voltage P0, P1, P2 “H” level input voltage X IN “H” level input voltage RESET “H” level input voltage INT “L” level input voltage P0, P1, P2 “L” level input voltage X IN “L” level input voltage RESET “L” level input voltage INT “L” level peak output current P0, P1, D 0–D 7, CARR “L” level average output current P0, P1, D 0–D 7, CARR (Note) “H” level peak output current CARR “H” level average output current CARR (Note) f(X CIN) clock frequency Valid power supply rising time for power-on reset circuit Limits Symbol VDD VRAM VSS VIH VIH VIH VIH VIL VIL VIL VIL IOL (peak) IOL (avg) IOH (peak) IOH (avg) f(XCIN) TPON Max. 5.5 5.5 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.3VDD 0.3VDD 0.2VDD 100 Typ. Unit V V V V V V V V V V V mA mA mA mA kHz µs Conditions f(XIN) ≤ 4.0 MHz, ceramic resonator, STCK=f(X IN)/4 f(XIN) ≤ 1.0 MHz, ceramic resonator, STCK=f(X IN) f(XIN) ≤ 4.0 MHz, ceramic resonator, STCK=f(X IN)/4 f(XIN) ≤ 1.0 MHz, ceramic resonator, STCK=f(X IN) f(XIN) ≤ 8.0 MHz, ceramic resonator, STCK=f(X IN)/4 f(XIN) ≤ 2.0 MHz, ceramic resonator, STCK=f(X IN) RAM back-up VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V VDD =5.0 V VDD =3.0 V Quarts-crystal oscillator Mask ROM version V DD = 0 to 2.2 V One Time PROM version VDD = 0 to 2.5 V Mask ROM version One Time PROM version Note: The average output current is the average current value at the 100 ms interval.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Unit V V µA µA µA mA µA µA µA kΩ kΩ V V kΩ kΩ kΩ Max. 0.9 0.9 5.0 1.0 125 250 130 6.5 1200

ELECTRICAL CHARACTERISTICS

(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) LimitsSymbol VOL VOH IIH IIL IOZ IDD R PH VT+ – VT– R COM R SEG R VLC Parameter “L” level output voltage P0, P1, D 0–D 7, CARR, RESET “H” level output voltage CARR “H” level input current P0, P1, P2, RESET “L” level input current P1, P2 Output current at off-state D0–D 7 Supply current (Note 2) Pull-up resistor value Hysteresis COM output impedance SEG output impedance LCD power supply internal resistor value (Note 3) Test conditions IOL = 5 mA IOL = 2 mA IOH = –15 mA IOH = –7 mA VI = VDD (Note 1) VI = 0 V (Note 1) VO = VDD VDD = 5.0 V, f(XCIN) = 32 kHz, f(XIN) = 8 MHz STCK = f(XIN)/4 VDD = 5.0 V f(XCIN) = 32 kHz STCK = f(XIN) VDD = 3.0 V, f(XCIN) = 32 kHz, f(XIN) = 4 MHz STCK = f(XIN)/4 VDD = 3.0 V f(XCIN) = 32 kHz STCK = f(XIN) VDD = 5.0 V f(XIN) = stop f(XCIN) = 32 kHz VDD = 3.0 V f(XIN) = stop f(XCIN) = 32 kHz f(XIN) = stop f(XCIN) = 32 kHz Ta=25 °C f(XIN) = stop f(XCIN) = 32 kHz f(XIN) = stop, f(XCIN) = stop, Ta = 25 °C f(XIN) = stop, f(XCIN) = stop VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Impedance between VLC3 and VSS Ta=25 °C Typ. 2.5 0.1 100 0.5 0.4 1.5 0.6 1.3 1.6 1.8 2.2 600 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V at active high-speed mode while LCD is operating at active low-speed mode while LCD is operating at clock operating mode while LCD is operating at RAM back-up mode P0, P1 RESET INT RESET f(XIN) = 2 MHz f(XIN) = 1 MHz f(XIN) = 1 MHz f(XIN) = 500 kHz STCK = f(XCIN)/4 STCK = f(XCIN) STCK = f(XCIN)/4 STCK = f(XCIN) VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Min. 2.4 1.0 300 2.3 1.4 0.7 0.6 0.4 27.5 Notes 1: In this case, the pull-up transistor of port P1 is turned off and the port P2 function is selected by software. 2: The current value includes the current dissipation of the LCD power supply internal resistor (RVLC ). 3: VLC3 =V DD . 4.6 2.8 1.4 1.2 0.8 140 180 17.5

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER BASIC TIMING DIAGRAM System clock Port D output Ports P0, P1 output Ports P0, P1 and P2 input Interrupt input STCK Parameter Pin name Machine cycle Mi Mi+1 INT D 0–D 7 P00–P03 P10–P13 P00–P03 P10–P13 P20–P23

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Product M34551E8-XXXFP M34551E8FP PROM size (5 10 bits) 8192 words RAM size (5 4 bits) 280 words Package 48P6S-A ROM type One Time PROM [shipped after writing] (shipped after writing and test in factory) One Time PROM [shipped in blank] PIN CONFIGURATION (TOP VIEW) BUILT-IN PROM VERSION In addition to the mask ROM version, the 4551 Group has the programmable ROM version software compatible with mask ROM. The One Time PROM version has PROM which can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM version, but it has a PROM mode that enables writing to built-in PROM. Table 20 shows the product of built-in PROM version. Figure 41 shows the pin configurations of built-in PROM version. The One Time PROM version has pin-compatibility with the mask ROM version. Table 20 Product of built-in PROM version 123456789 1 0 1 1 1 2 1 3 1 4 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG SEG SEG SEG SEG SEG SEG COM COM SEG SEG M34551E8-XXXFP SEG 11 SEG 14 SEG 15 SEG 9 VSS XOUT XIN D D D D 4 D RESET D 7/XCOUT D 6/XCIN CARR VDD CNV SS VSS D 5 / INT COM COM SEG 10 SEG 13 SEG 12 3 / SEG 2 / SEG P20 / SEG16 P21 / SEG17 Outline 48P6S-A Fig. 41 Pin configuration of built-in PROM version

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER Fig. 42 PROM memory map Fig. 43 Flow of writing and test of the product shipped in blank (1) PROM mode The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 21. Contact addresses at the end of this book for the appropriate PROM programmer.

Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 42. (2) Notes on handling À A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. \` For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 43 before using is recommended. (Products shipped in blank: PROM contents is not written in factory when shipped) Table 21 Programming adapter Microcomputer M34551E8-XXXFP, M34551E8FP Programming adapter PCA7414 Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150°C exceeding 100 hours. Note: Address 000016 1FFF 16 400016 5FFF 16 7FFF 16 1 11 D 4 D 3 D 2 D 1 D 0 High-order 5 bits 1 11 D 4 D 3 D 2 D 1 D 0 Low-order 5 bits Set “FF16” to the shaded area.

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Rev. Rev. No. date

1.0 First Edition 971130

REVISION DESCRIPTION LIST 4551 GROUP DATA SHEET (1/1) Revision Description

Selected Specification

Renesas Technology Corp 4551 overview.

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Overview

4551 is listed in the IC category. Available datasheets include documents from Renesas Technology Corp, Heyco., RAF ELECTRONIC HARDWARE. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

4-BIT SINGLE-CHIP MICROCOMPUTER

Description

4-BIT SINGLE-CHIP MICROCOMPUTER

Source title 4551_03 Datasheet(PDF) - Renesas Technology Corp

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