HD44231P HITACHI
Document overview
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Technical content
Features
- Single Chip CMOS CODEC with Filter In 16-pins DIL Package + Power Supply Voltage +5 V+5%, Low Power Dissipation (50 mW Typ) * Follows A-Law (HD44231P, HD44233P) ‘+ Follows p-Law (HD44232P, HD44234P) + Exceeds CCITT Specifications & D4 ‘* Synchronous (All Devices)/Asynchronous (HD44233P, HD44234P Only) Operation for 2048/1544/1536 kHz PCM Rate * Internal Clock Generator * Anti-Aliasing Filter (2nd order CR Active Filter) * Voltage Reference (Internal-Trimmed) * Input Amplifier * Auto-Zero Cancel Circuit Without External Component Pin Configuration an [a vss ow] [ie) v0 on fis} eemour cute Fy on Bi] [iq 0 cata} me sono [| {is} paxo acno [7] [73] von nour FE] fa} wes pow (F] [72] 1x. sync wot [ia) see wo [o] [71] xcv. sync wot] bay cuacx ve [7] [ie] 1x. crock wef Eran pew [a] [9] rcv. cock HD44231P, HD44232P HD44233P, HD44234P Figure 1 Pin Assignment Packaging Information Part No. Package HD44231P DP-16A HD44232P DP-16A HD44233P DP-16A HD44234P DP-16A HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. + Brisbane, CA 94005-1819 » (415) 589-8300 441
Table 1. Pin Descriptions
1 AIN 1_AIN ‘Analog Input
3 GA2 3 GA2 Gain Adjust 2 10KQSRe
13 DGND 13 DGND Digital Ground
14 PD 14 PD Power Down (TL) 0" = down
15 PCMOUT 15 PCMOUT PCM Data Output Open Drain
8 NC ‘Open
2 NC Open
HD44231P/HD44232P/HD44233P/HD44234P General Description The HD44231P, HD44232P, HD44233P, HD44234P are monolithic silicon gate CMOS Companding Encoder/ Decoder chips designed to implement the per channel voice frequency Codecs used in PCM systems. The chips contain the band limiting filters and the analog/digital conversion circuits that conform to the A-law or 1-Law companding characteristic. HD44231P and HD44233P are A-Law. HD44232P and HD44234P are p-Law. These circuits provide the interface between the analog signals of the subscriber loop and digital signals of the PCM highway in a digital telephone switching system. The devices operate from dual power supplies of + 5 V. For a sampling rate of 8 kHz, PCM input/output data rate can be selected from 1536/1544/2048 kHz in ‘synchronous or asynchronous (HD44233, HD44234 only) operation. Functional Description Figure 2 shows the simplified block diagram of the HD44231P, HD44232P, HD44233P and HD44234P. The dotted lines are connected internally to get the synchronous devices (HD44231P, HD44232P). The devices contain independent circuitry for processing transmit and receive signals. Switched capacitor filters provide the necessary bandwidth limiting of voice signals in both directions. Circuitry for coding and decoding operates on the principle of successive approximation, using charge redistribution in a binary weighted capacitor array to define segments and a resistor chain to define steps. The relationship between the PCM data word and the audio signal is defined just same as CCITT G711 Table 1 for HD44231 P and HD44239P, Table 2 for HD44232P and HD44234P respectively. A band-gap voltage generator supplies the reference level for the conversion process. 2nd Order CR Active Filter is implemented on chip to avoid the aliasing noise which is caused by the clock of transmit filter. Transmit Section Input analog signals first enter the chip at the uncommitted amplifier terminals. This op amp allows gain trim to be used if desired to set the 0 dB or 0 level in the system. This amplifier also operates as the 2 nd order analog anti-aliasing filter. This filter eliminates the need for any off-chip filtering as it provides attenuation of 32 dB (typ) at 256 kHz and 40 dB (typ) at 512 kHz, the “effective” clock frequency of the following switched-capacitor Cosine Filter. From the Cosine Filter the signal enters a 5th Order Low-Pass Filter clocked at 128 kHz, followed by a 3rd Order High-Pass Filter clocked at 8 kHz. The resulting band-pass characteristics meet the CCITT, G.712 specifications. The output of the high pass filter is sampled by a capacitor array at the sampling rate of 8 kHz. The 8-bit PCM data is clocked out by the shift clock at one of 1536/1544/2048 kHz. A auto-zero loop (without any ‘external capacitor) provides DC offset cancellation by integrating the sign bit of the PCM data and feeding it back to the non-inverting input of the comparator. An additional feature of the HD44231P and HD44233P is a signbit fixation circuit to reduce the idle channel noise during quiet periods. It is of particular importance because the A-Law transfer characteristic has “mid-riser” bias which enhances low level signals from crosstalk. Receive Section A shift clock, at one of 1536/1544/2048 kHz, clock the PCM data into the input buffer register once every sampling period. A charge proportional to the received PCM data word appears on the decoder capacitor array. A sample and hold initialized to zero by a narrow pulse at the beginning of each sampling period integrates the charge and holds for the rest of the sampling period. A switched-capacitor Sth Order Low-Pass Filter clocked at 128 kHz smooths the sampled and held signal. It also performs the loss equalization to compensate for the sin x/ x distortion due to the sample and hold operation. The filter output is available for driving electronic hybrids directly as long as the impedance is greater than 600 Q. Companding Law The encoding and decoding characteristics of the Codecs comply with the requirements of CCITT G711 table HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 443
HD44231P/HD44232P/HD44233P/HD44234P 1 or Table 2, corresponding to their comparing law. The even bits of PCM words are inverted for A-Law devices. Positive logic is used (the High level corresponds to ‘1’). Power Down Logic Powering down the CODEC can be done in several ways. The most direct method is to drive the PD. pin toa low level. Stopping SYNC input will also put the chip into the stand-by mode. The input can be held high, low or disconnected. After the chip being activated by these functions, the PCMOUT is in high impedance state and the OUT is connected to AGND for about 1 ms to avoid the power-on noise. Voltage Reference Circuit A temperature compensated band-gap voltage generator provides a stable reference for the coder and decoder. Two amplifiers buffer the reference and supply it to the coder and decoder independently to minimize crosstalk. This reference voltage is trimmed to ensure a minimum gain error of +0.1 dB at the nominal power supply voltage and the room temperature. Timing Requirements The CODECs do not require that the 8 kHz transmit and receive sampling strobes should be exactly 8 bit periods wide. The device has an intemal bit counter that counts the number of data bits shifted. It is reset on the leading (+) edges of the strobe, forcing the PCM output in a high impedance state after the 8th bit is shifted out. This allows the strobe signal to have any duty cycle as long as its repetition rate is 8 kHz and shift clock is synchronized to it. The clock rate can be selected from 1536/1544/2048 kHz. System Clock The basic timing of the Codecs is provided by the shift clock. This 1.536/1.544/2.048 MHz clock is divided down internally to provide the various filter clocks and the timing for the conversions. No extemal control signal for the selection is required. HITACHI 444 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300
— SSeseeeeeeFeeSeSFeEeEeeeeee HD44231P/HD44232P/HD44233P/HD44234P Pin/Function Descriptions Pin No Descriptions * CLOCK 10 One of 1.536, 1.544, 2.048 MHz clock can be accepted with the pins. And they are automatically divided down to provide the internal clocks. **TXCLOCK 9 These TTL compatible inputs shift PCM data out of the coder on the positive going edges RCV.CLOCK 10 and PCM data into the decoder on the negative going edges after receiving a positive edge on the SYNC, TX.SYNC/RCV.SYNC respectively. * SYNC 11__ These TTL compatible pulse inputs (Typ 8 kHz) are used for analog sampling and for initiating the PCM output from the coder and initiate clocking of PCM input data into the **TX.SYNC 11 decoder. They must be synchronized with the CLOCK, TX.CLOCK/RCV.CLOCK with RCV.SYNC 12 these positive going edges occurring after the falling edge of the CLOCK, TX.CLOCK/ RCV.CLOCK respectively. The width of these signals are not critical. An internal bit counter generates the necessary timing for PCM output and input. PCMOUT 15 This is a LS-TTL compatible open-drain output. It is active only during transmission of PCM output for 8 bit periods of CLOCK, TX.CLOCK/RCV.CLOCK signal following a positive edge on the SYNC, TX.SYNC/RCV.SYNC input. Data is clocked out by the positive edge of the CLOCK. One 500 Q pull-up per 8 Codecs is required. *PCMIN 9 This is a TTL compatible input for supplying PCM input data to the decoder. Data is PCMIN % clocked in by the negative edge of CLOCK, RCV.CLOCK. AIN 1 These three pins are provided for connecting analog signals in the range of ~Vrer to GAL 2 +Vrer to the device. The input stage can be connected as a unity gain amplifier, GA2 3 amplifier with gain or amplifier with adjustable gain. The adjustable gain configuration will facilitate calibration of the transmit channel. AIN is the input of analog signal of the amplifier. GA2 is the output of the amplifier. GA2 shall be loaded by the resistor above 10 kQ or directly connected to GAL. GA1 is the negative feed back input of the amplifier. Cx should be less than 100 pF. AOUT 5 Thisis the buffered output of the recreated analog signal from the received PCM data words. It can drive the impedance of 600 ohms. Ci. should be less than 100 pF. Voo 7 These are power supply pins. Von and Vss are positive and negative supply pins Vss 16 respectively (Typ +5 V, -5 V). Analog and digital ground pins are separate for minimiz- AGND 4 —_ ing crosstalk. DGND 13 PD 14 When this TTL compatible input is held low, the chip is put into the powered down mode regardless of strobes. The chip will also power down if the strobes stop. The strobes can be high, low or floating, but as long as they are static, the powered down mode is in effect. This pin should be pulled-up to Voo to keep the device active or to control On/Off with 5 strobes. #7 for HD44231P, HD44232P : for HD44233P, HD44234P HITACHI Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 445
HD44231P/HD44232P/HD44233P/HD44234P eee SSR Absolute Maximum Ratings Item Rating Voo -0.31047V Vss 40.3 0-7V Storage Temperature =55°C to +125°C Power Dissipation OsW Digital Inpu/Output Voltage 0.3 V< Viv < Voo +03 Analog Input/Output Voltage Vss - 0.3 V < Viv < Voo +03
Electrical Characteristics
Static Characteristics (Voo = 5 + 0.25 V, Vss =-5 + 0.25 V, Vec= 5 + 0.25 V, Ta = 0-70°C) Symbol Pin Pin Descriptions Min Typ Max Unit Note/Conditions HD44231P HD44233P HD44232P_HD44234P. Too 7 7 Voo Current (OPE.) 5510 mA ‘0 Iss 16 16 Vss Current (OPE) __-10_ —4.5 AIN=0V Ibpst 7 7 Vo Current (St.By.) 03 PCMIN = +0 CODE Isssr 16 16 Vss Current (StBy.) 0.2 RUGA2) = 10k Ru(AQUT) = 600 kQ I 1,29, 1,28, Leax Current =10.0 10.0 WA Vm=08V 10,14 9,10, 14 =10.0 10.0 pA Vm=2.0V 10.0 yA Vop=Vu=5.25V Tee i 11,12 Pull Up Current =100 0 HA Tou 15 15 Leak Current 10.0 pA Vop=Vm=5.25V Cana 1,2 1,2 Analog Input Cap. 10 pF__at | MHz Vbias=0V Cow 9, 10, 8,9,10, Input Capacitance 10 pF at 1 MHz Vbias=0V 11,14 11, 12, 14 Roura 5 5 AOUT Resistance 1 0 & _ Roura 3 3 GA2 Resistance 30 -Q tel Vasw 3 3 GA2 Output Swing 3.0 30 V_ Ri=10kQ VorrN 1 1 “Analog Offset Input___-500 500 mV Note! Vorrs 3 3 GA2 Offset Output -50 50 _mV__Note1 Vorra 5 5 AOUT Offset Output -50 50__mV__PCMIN=+0-Code Coour 15 15 PCMOUT Capacitance 15.0 pF at! MHz Vbias=0V Vow 15 15 PCMOUT Low Voltage 04 V RL=500Q +To.. = 0.8 mA Vou 15 15 PCMOUT High Vec-0.3 V low =-150 mA Voltage Vie 10,11, 8, 10,11, Digital Input High 2.0 v 914 9,12,14 Voltage 7 Vu. 10,11 8,10,11, Digital Input Low 08 Vv 914 9,12,14 Voltage ~ Note 1) Analog Input Amplifier Gain = 0 dB (Gal is connected to GA3) HITACHI 446 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300
HD44231P/HD44232P/HD44233P/HD44234P Dynamic-Characteristics (Vo = 5 + 0.25 V, Vss = -5 + 0.25 V, Vec = 5 £0.25 V, Ta = 0 to +70°C) Sym. Descriptions Min Typ Max Unit Note FS Synchronization Rate g kHz FC PCM Bit Clock Rate 15367 kHz 1544/ 2048 we Clock Pulse Width 200 ns twstt SYNC Pulse High Width 200 ns twsl, SYNC Pulse Low Width 8 Bs ra Logic Input Rise Time 5 50 ns if Logic Input Fall Time 5 350 ns tas. Previous Clock To SYNC Delay 40 ns feet tes Clock To SYNC Delay 100__ns Noe 1.3 tedl Clock To PCM MSB Delay 170__ns bela sd ‘SYNC To PCM MSB Delay 170s wan 36 ted Clock To PCMOUT Delay 180s. te 23 ‘su PCMIN Setup Time 65 ns nee thd PCMIN Hold Time 120 ns Nee Notes 1) tr, tf of digital input o clock is assumed Sns for timing measurement. 2) PCMOUT Load Condition: 500.0 + 165 pF + two LS-TTL Equivalent (Ii. = 0.8 mA, Ini =-150 1A) Threshold Level (Vou =24V, Voi =0.4V) 3). Positive value shows SYNC delay from CLOCK. 4) ted], tsd are specified by CLOCK or SYNC which has slower rise time. 5) ted specification is valid for the data except MSB. System Related Characteristics (Vpn = 5 + 0.25 V, Vss=-5+0.25 V, Voc=5 £0.25 V,Ta=0to +70°C, Input Amplifier Gain = 0 dB, GA2 Load = 10k, Aout Load = 600 , Synchronous operation. FC (PCM Bit Clock) = 2048 kHz) For HD44231P, HD44233P Sym Descriptions Test Conditions Min Typ___Max__Unit__Note SDA Signal to Dist 820 Hz tone 45 dBm0 25 dB op-wgt (Ato A) 40 30 4B 3010 43 35 4B SNA Signal to Dist Noise 55 dBm0 14 B (Ato A) ~40 29 6B 34 34 aB 2710-6 36 4B 3 28 4B 5 SDX Signal to Dist 820 Hz tone ~45 dBm0 26 aBOp-wet (Ato D) 40 31 aB -30 to +3 36 dB SNX Signal to Dist Noise 55 dBm0 15 B (AtoD) 40 30 B =34 35. 4B =27 10-6 37 dB SDR Signal to Dist 820 Hz tone ~45 dBm0 26 dB op-wgt (Dto A) 40 31 4B 30 to +3 36, dB HITACHI Hitachi America, Ltd. « Hitachi Plaza + 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300 447
HD44231P/HD44232P/HD44233P/HD44234P (con'd) Sym. __ Descriptions Test Conditions Min Typ Max Unit Note ‘SNR Signal to Dist Noise =55 dBm0 15 B (oA) ~40 30 <B 34 35 4B 2710-6 37 Bo GTA Gain Track 820 Hz tone =55 to -50 1.0 10 4B (Ato A) Relative to dBm0 -10dBm0 50 to 40 05 05 B 40 0 +3 03 03 GNA Gain Track Noise Relative 6010 08 08 4B (Ato A) to -10 dBm0 55 dBm0 =55 0-10 04 04 4B GTX Gain Track 820 Hz tone =55 10-50 08 08 GB (AtoD) Relative to =50 to -40 04 04 B 10 dBm0 40 to 02 02 B 43.dBm0 GNX Gain Track Noise ~60 to 06 06 4B (Aw D) Relative to 55 dBmO -10 dBm0 =550-40 04 04 4B —40 to -10 0.2 02 dB GTR Gain Track 820 Hz tone =55t0-50 08 08 dB (wa) Relative to 5000-40 0.4 04 dB -10dBm0 —40 to 02 02 4B +3dBm0 GNR Gain Track Noise 60 to ~04 04 «dB (oA) Relative to 55 dBm0 -10 dBm0 =55t0-10 0.2 02 4B FRX FreqResponse Relative to 0.06 kHz 4 aB (AtoD) 820 Hz 02 0 20 (Loss) OdBm0 03103 15 0.15 3.18 0.15 0.65 34 0 08 3.78 65 FRR Freq. Response Relative Ow3kHz 0.15 015 4B (DwA) to 820 Hz 3.18 0.15 0.65 (Loss) 0 dBm0 34 0 08 3.78 65 AIL Analog Input 820 Hz 25°C 1.217 1.231 1.246 Vrms Level 0 dBm0 nomP.S. AOL ‘Analog Output 820 Hz 25°C 1.217 1231 1.246 Vrms Level 0dBmO nom. PS. ICNA___IdleCh. Noise AtoA IN = AGND ~78_ dBmOP ICNX__Idle Ch. Noise AtoD ‘AIN=AGND -80_dBmOP CNR IdleCh.Noise DtoA PCMIN = 81 dBmOP +0-CODE XTKA AINtoAOUT —_820Hz 0dBm0 5 GB Crosstalk XTKD _PCMINto 820 Hz 0dBm0 “5 ~B PCMOUT HITACHI 448 Hitachi America, Ltd, © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300
HD44231P/HD44232P/HD44233P/HD44234P For HD44232P, HD44234P Sym. Descriptions _Test Conditions Min Typ _Max__Unit Note SDA SignaltoDist 1020 Hz tone ~45 dBm 25 GB c-wgt (Ato A) 40 30 B -30 to +3 35, dB SDX ——Signalto Dist —_1020Hz tone 45 dBm0 26 dB c-wgt (AtoD) ~40 31 B =30 10 +3 36 B SDR SignaltoDist. 1020 Hz tone =45 dBm0 26 dB c-wgt (DA) 40 31 aB =30 to +3 36 aB GTA Gain Tracking ‘1020 Hz tone =55 to -50 dBm0 -1.0 10 dB (Ato A) Relative to =50 to -40 05 05 4B -10 dBm0 40 to +3 0.3 0.3 dB GTX Gain Tracking 1020 Hz tone -55 10-50 0.8 08 dB (AtoD) Relative to =50 to -40 04 04 B 10 dBm0 4010 +3 dBm0_-0.2 02 _ GTR Gain Tracking 1020 Hz tone =55 0-50 0.8 08 4B (@wA) Relative to =50 to -40 0.4 04 dB 10 dBmO 40 to +3 dBm0_-0.2 02 aB FRX FreqResponse Relative to 0.06 kHz 24 (AtoDyLoss) 1020 Hz 0.2 0 2.0 OdBm0 0.3t03 0.15 0.15 B 318 0.15 0.65 34 0 08 3.78 65 FRR Freq.Response Relativeto 1020Hz Oto3kHz = -0.15 0.15 (DtoA) (Loss) 0 dBm0 3.18 0.15 065__ gy 34 0) 08 3.78 65 Level OdBm0 Level 0 dBm0 ICNA___ IdleCh.Noise _ AtoA AIN = AGND 15__dBmCO ICNX__ Idle Ch. Noise A toD. AIN=AGND 15__dBmCO ICNR IdleCh. Noise DtoA PCMIN = 9 dBmCO 5° +0-Code XTKA AINtoAOUT —_1020Hz 0 dBm0 5B Crosstalk XTKD —PCMINto 1020 Hz 0 dBm 65GB PCMOUT HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 449
HD44231P/HD44232P/HD44233P/HD44234P For HD44231P, HD44232P, HD44233P, HD44234P Sym. Descriptions Test Conditions Min Typ Max Unit__ Note AT AIL, AOL Variation Relative to 25°C #20 ppc with temp. nominal P.S. AP AIL,AOL Variation 25°C, £0.01 «B with P.S. Supplies + 5% ALS — Gain Variation over A toD Initial 02 02 dB‘) Temp. P.S. DtoA AIP Peak Analog Input 3.0 Vv AOP Peak Analog Output 25 Vv PDL Propagation Delay Ato A 0.aBmO 450 480s DD _ Delay Distortion AwA 0510 14 0dBmO 0.6 KHz 0.6 to 1.0 07 ms rel. to min. 1,010.26 02 delay 2.6 t0 28 14 PSRR PSRR AwA Vop Mod. = 30 B AIN= +5.V +100 mVop AGND Vss Mod. = 03- -5V+100mVop 30 50 kHz IMI _ Intermodulation ‘Ato A(a-b) a; 0.47 kHz, 4 dBmO -38 «4B b:0.32, 4 IM2 _Intermodulation Ato A(@-b) a; 1.02 kHz, -4 dBmO -52 GB b;.0.05, -23 ICS Single Freq.Noise AtoA 8,16,24, AIN= 32,40 kHz -50 dBmO AGND DIS Discrimination AtoA 4.610 0dBmO 200 kHz 30. dB Note 1) Total variation of GAIN including the initial fluctuation temperature variation and power supply dependence (Oto 70°C, Vov/Vss = + 5 V t 5%) HITACHI 450 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300
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