4192 ETC1
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PRELIMINARY | 92 si a we “ial i I . a iil 12-Bit Fast i A/D Converter A The 4192 is intended for applications requiring extremely fast, FEATURES precise analog-to-digital conversion. The maximum conver- —— sion speed is 500ns. Proven monolithic circuits and recent ¢ 12-Bit Resolution advanced designs are combined to produce a device with ¢ 500ns Max. Conversion Time improved performance but low cost. The 4192 is manufactured m using thick and thin film hybrid technology. Low Power, 1.8W Max. Three selectable input ranges are provided; 0 to +10V; +10v | ® Three-State Output Buffers and 0 to +20V. Factory laser trims adjust all parameters so that —55°C to +125°C Operation most applications will require no additional adjustment. Option- . al gain and offset adjustments are provided for the user's - convenience. APPLICATIONS Conversions are initiated by a single pulse 50ns minimum. i . Two timing signals are produced by the converter.End ofcon- | ® Medical Instrumentation vert signals data is ready at the outputs. Sample/Hold signals an High Speed Data external Track/Hold to begin acquiring the next analog data Acquisition Systems point. This technique reduces the overall conversion time for a combined A/D and T/H, thus increasing throughput. Tri-state outputs are supplied for bus applications. Also included is an overflow pin. Overflow indicates the analog sig- nal being converted was outside the range of the converter. Power requirements are +15 and 5V. Power consumption is typically 1.5W. The standard 4192 is specified for 0°C to +70°C operation. The 4192-83 is fully specified for operation over the -55°C to +125°C temperature range and meets the high reliability requirements of MIL-STD-883C, Class “B”. May also be ordered screened to Class “S”. Oe rr! PACKAGE DIMENSIONS nessa 7 “ily H H 4, 410V REF 17, SAMPLE/HOLD CONTROL ! ye Sorceraowst —Zt-arrto 0.160 (4.1) MAX i eqrrow ' ‘ , : Le ' ' ~ SEAREE ars 710) Beare ome Kame KOA t H 10:ENABLE (GITS 1-680F) 26.8175 corouron —| #1 ai |—Yoreo WeowMALGROUND — ahatrs ee Ge IGANALOG GROUND 2. GANADIUST OS TELEDYNE PHILBRICK microcincurs 61
+15V Supply (Pin 13) OV to +18V —15V Supply (Pin 14) OV to -18V. 4+5V Supply (Pin 11) ~0.5V to +7.0V —5V Supply (Pin 15) +0.5V to —7.0V Digital Inputs: (Pins 7, 9, 13, 31) -0.3V to +6.0V Analog Input: (Pin 3) +25V ‘SPECIFICATIONS (Ta = +25°C, +15V and +5V supplies unless otherwise indicated). [PanamereR ins ve, ax. Tunis] ANALOG INPUTS Input Voltage Range =_ Oto HO Vv _ 0 to +20 Vv ~~ +10 Vv Input Impedance: Unipolar 3.75 5 kQ Bipolar 1,75 25 kQ Analog Input Settling Time — ~ nsec DIGITAL INPUTS Input Capacitance 50 pf Logic Levels: Logic "1" _ v Logic “o" 05 Vv Logic Loading: Logic “1” 5 uA Logic “o” —100 ur Start Convert Pulse Width nom + nseo Start Convert Rise & Fall Time 30 nsec DIGITAL OUTPUTS Output Coding: (Pin 7 - High) Straight Binary/Offset Binary (Pin 7 - Low) Complementary Binary Logic Levels: Logic “1" _ a Vv Logic “Oo” _ 0.5 v Logic Loading: Logic "1" ~ —160 uh Logic “oO” a 6.0 mA Start Convert Low to EOC High Propagation Delay _ 25 nsec Start Convert Low to Previous Output Data Invalid _ _ nsec Data Valid before EOC s088 Low a om nsec Enable to Output to Data Valid Propagation Delay _ 10 nsec TRANSFER CHARACTERISTICS Integral Nonlinearity: +25°C. - _ +% LSB 55°C to +125°C 4192-83 _ _ +2 LsB Integral Nonlinearity Tempco _ _ +3 ppm/C Differential Nonlinearity: +25°C _ - tk LSB 55°C to +125°C = 4192-83 _ _ 1 LSB Differential Nonlinearity Tempco _ _ +2 ppm/C Full Scale Absolute Accuracy: 0°C to +70°C 4192 TBD _ - 2 %FSR 65°C to +125°C 4192-83 TBD _ - 4 %FSR No Missing Codes (12 Bits): 0°C to +70°C 4192 Over the Operating Temperature Range 85°C to +125°C 4192-83 Unipolar Zero Error, +25°C —_ _ 40.01 %FSR Unipolar Zero Tempco -_ — 213 ppm/C Bipolar Offset Error, +25°C. _ _ 40,01 %FSR Bipolar Offset Tempco _ ~ 413 ppm/G Gain Error, +25°C. _ _ +£0.01 %FSR Gain Tempco =~ +17 435 ppnvC asnanemeenem =TTT anl
62 TELEDYNE PHILBRICK merocircurs
SPECIFICATIONS (Ta = +25°C, ++15V and +5V supplies untess otherwise indicated). Figure 1. Functional Block Diagram