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Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201184 07/25/2019 Rev#A4 ECN# DFN 4117 Series

FEATURES

LOW POWER IDSS<600 µA (4117DFN) MINIMUM CIRCUIT LOADING IGSS<200 pA (4117DFN Series) ABSOLUTE MAXIMUM RATINGS (NOTE 3) @ 25°C (unless otherwise noted) Gate-Source or Gate-Drain Voltage -40V Gate-Current 50mA Total Device Dissipation (Derate 2.8mW/ºC above 25ºC) 300mW Storage Temperature Range -55ºC to+150ºC ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted) SYMBOL CHARACTERISTIC 4117DFN 4118DFN 4119DFN UNITS CONDITIONS MIN MAX MIN MAX MIN MAX BVGSS Gate-Source Breakdown Voltage -40 -- -40 -- -40 -- V IG =-1µA, VDS=0 VGS(off) Gate-Source Cutoff Voltage -0.6 -1.8 -1 -3 -2 -6 VDS =10V, ID=1nA IDSS Saturation Drain Current IGSS Gate Reverse Current -- -200 -- -200 -- -200 pA VGS =-10V, VDS=0V gfs Common-Source Forward Transconductance 70 450 80 650 100 700 µS VDS =10V, VGS=0 f=1kHz gos Common-Source Output Conductance (NOTE 4) -- 3 -- 5 -- 10 Ciss Common-Source Input Capacitance (NOTE 4) -- 3 -- 3 -- 3 pF f=1MHz Crss Common-Source Reverse Transfer Capacitance (NOTE 4) -- 1.5 -- 1.5 -- 1.5 DFN SERIES 8 7 6 5 439F YYWW SD G LEADS 1, 2, 4, 5 & 7 – NO CONNECTION TOP VIEW 1 2 3 4 411F 4117DFN SERIES MINIATURE/NON MAGNETIC 8-PIN DFN PACKAGE ULTRA-HIGH INPUT IMPEDANCE N-CHANNEL JFET AMPLIFIER

Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201184 07/25/2019 Rev#A4 ECN# DFN 4117 Series NOTES: 1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged. 2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.) 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. 4. Not production tested, guaranteed by design. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Linear Integrated Systems. STANDARD PACKAGE DIMENSIONS: 2.0±0.10 (4 SIDES) TOP VIEW 0.76±0.05 SIDE VIEW ALL DIMENSIONS IN MILLIMETERS 5 8 4 1 CHAMFERED CORNER FOR PIN 1 INDICATOR 0.25X0.25 0.25±0.05 (8x) 1.60±0.15 0.29±0.10 (8x) 0.50 (6x) TYP. 0.90±0.15 0.20 MIN. BOTTOM VIEW EXPOSED PAD SOLDER PAD PITCH & DIMENSIONS 1.05±0.10 (2 SIDES)

0.20 MIN

0.675±0.05 0.50 (4x) TYP . 0.30 (4x) TYP . 1.80±0.05 (2 SIDES) 0.25±0.05 (8X) 0.42±0.05 (8X) 2.50±0.05 PACKAGE OUTLINE DFN SERIES Linear Integrated Systems develops and produces the highest performance semiconductors of their kind in the industry. Li near Systems, founded in 1987, uses patented and proprietary processes and designs to create its high performance discrete semiconductors. Expertise brought to the company is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company founder John H. Hall.