39SF020 SST

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Technical content

2 Megabit (256K x 8) Multi-Purpose Flash

Preliminary Specifications © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. 326-10 12/98 These specifications are subject to change without notice. FEATURES:

  • Organized as 256 K X 8
  • Single 5.0V Read and Write Operations
  • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention
  • Low Power Consumption: – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical)
  • Sector Erase Capability – Uniform 4 KByte sectors
  • Fast Read Access Time: – 70 and 90 ns
  • Latched Address and Data
  • Fast Sector Erase and Byte Program: – Sector Erase Time: 7 ms (typical) – Chip Erase Time: 15 ms (typical) – Byte Program time: 20 µs (typical) – Chip Rewrite Time: 5 seconds (typical)
  • Automatic Write Timing - Internal V pp Generation
  • End of Write Detection – Toggle Bit – Data# Polling
  • TTL I/O Compatibility
  • JEDEC Standard – EEPROM Pinouts and command set
  • Packages Available – 32-Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST39SF020 is a 256K x 8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF020 device writes (Program or Erase) with a 5.0V-only power supply. The SST39SF020 device conforms to JEDEC standard pinouts for x8 memories. Featuring high performance byte program, the SST39SF020 device provides a maximum byte-pro- gram time of 30 µsec. The entire memory can be erased and programmed byte by byte typically in 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, the SST39SF020 device has on-chip hardware and soft- ware data protection schemes. Designed, manufac- tured, and tested for a wide spectrum of applications, the SST39SF020 device is offered with a guaranteed endur- ance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39SF020 device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applica- tions, the SST39SF020 device significantly improves performance and reliability, while lowering power consumption. The SST39SF020 inherently uses less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash tech- nology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash tech- nologies. The SST39SF020 device also improves flex- ibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of endurance cycles that have occurred. Therefore the system soft- ware or hardware does not have to be modified or de- rated as is necessary with alternative flash technologies, whose erase and program times increase with accumu- lated endurance cycles. To meet high density, surface mount requirements, the SST39SF020 device is offered in 32-pin TSOP and 32- pin PLCC packages. A 600 mil, 32-pin PDIP is also available. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while

© 1998 Silicon Storage Technology, Inc. 326-10 12/98

2 Megabit Multi-Purpose Flash

Preliminary Specifications keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39SF020 device is con- trolled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is dese- lected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Byte Program Operation The SST39SF020 device is programmed on a byte-by- byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, which- ever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 30 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 14 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the inter- nal Program operation will be ignored. Sector Erase Operation The Sector Erase operation allows the system to erase the device on a sector by sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector Erase operation is initiated by executing a six-byte-command load sequence for software data pro- tection with sector erase command (30H) and sector address (SA) in the last bus cycle. The address lines A12-A17 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse , while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The end of Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands written during the Sector Erase opera- tion will be ignored. Chip-Erase Operation The SST39SF020 device provides a Chip-Erase opera- tion, which allows the user to erase the entire memory array to the “1’s” state. This is useful when the entire device must be quickly erased. The Chip Erase operation is initiated by executing a six- byte software data protection command sequence with Chip Erase command (10H) with address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 17 for the flowchart. Any commands written during the Chip Erase operation will be ignored. Write Operation Status Detection The SST39SF020 device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits : Data# Polling (DQ 7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising edge of WE# which initiates the internal program or erase cycle. The actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ When the SST39SF020 device is in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Program opera- tion is completed, DQ 7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program opera- tion. For sector or chip erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart.

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating 0’s and 1’s, i.e., toggling between 0 and 1. The Toggle Bit will begin with “1”. When the internal Program or Erase opera- tion is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector or Chip Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. Data Protection The SST39SF020 device provides both hardware and software features to protect nonvolatile data from inadvert- ent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Software Data Protection (SDP) The SST39SF020 provides the JEDEC approved soft- ware data protection scheme for all data alteration opera- tions, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Pro- gram operation, providing optimal protection from inad- vertent write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF020 device is shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid com- mands will abort the device to read mode, within TRC. Product Identification The product identification mode identifies the device as the SST39SF020 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39SF020 device. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 16 for the ID entry com- mand sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 16 for a flowchart. F UNCTIONAL BLOCK DIAGRAM OF SST39SF020 TABLE 1: PRODUCT IDENTIFICATION TABLE Address Data Manufacturer’s Code 0000H BF H Device Code 0001H B6 H 326 PGM T1.2 Y -Decoder I/O Buffers and Data Latches 326 ILL B1.3 Address Buffers & Latches X-Decoder DQ 7 - DQ0 A17 - A0 OE# CE# WE# 2,097,152 bit EEPROM Cell Array Control Logic

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES (8mm x 14mm) FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PDIPS AND 32-LEAD PLCC S A11 A13 A14 A17 WE# VCC NC A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 326 ILL F01.0 Standard Pinout Top View Die Up DQ0 A14 A13 A11 OE# A10 CE# DQ7 4 3 2 1 32 31 30 A12 A15 A16 NC VCC WE# A17 32-Lead PLCC Top View 32-Pin PDIP Top View 326 ILL F02.0 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 NC A16 A15 A12 DQ0 DQ1 DQ2 VSS VCC WE# A17 A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A17-A0 Address Inputs To provide memory addresses. During sector erase A17-A12 address lines will select the sector. DQ 7-DQ 0 Data Input/output To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the write operations. Vcc Power Supply To provide 5-volt supply (± 10%) Vss Ground NC No Connection Unconnected pins. 326 PGM T2.1 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# A9 DQ Address Read V IL VIL VIH AIN D OUT AIN Program V IL VIH VIL AIN D IN AIN Erase V IL VIH VIL X X Sector address, XXh for chip erase Standby V IH X X X High Z X Write Inhibit X V IL X X High Z/D OUT X XX V IH X High Z/D OUT X Product Identification Hardware Mode V IL VIL VIH VH Manufacturer Code (BF) A17 - A1 = VIL, A0 = VIL Device Code (B6) A 17 - A1 = VIL, A0 = VIH Software Mode V IL VIL VIH AIN ID Code See Table 4 326 PGM T3.4

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr(1) Data Addr (1) Data Addr (1) Data Addr (1) Data Addr (1) Data Addr (1) Data Byte Program 5555H AAH 2AAAH 55H 5555H A0H BA (3) Data Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA x(2) 30H Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit XXH F0H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Notes: (1) Address format A14-A0 (Hex), Addresses A15, A16 and A17 are a “Don’t Care” for the Command sequence. (2) SA x for sector erase; uses A17-A12 address lines (3) BA = Program Byte address (4) Both Software ID Exit operations are equivalent Notes for Software ID Entry Command Sequence 1. With A17 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, SST39SF020 Device Code = B6H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. 326 PGM T4.0

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) CC + 0.5V Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. AC C ONDITIONS OF TEST See Figures 12 and 13 O PERATING RANGE Range Ambient Temp V CC Commercial 0 °C to +70 °C 5V±10% Industrial -40 °C to +85 °C 5V±10%

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications TABLE 6: RECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units TPU-READ (1) Power-up to Read Operation 100 µs TPU-WRITE (1) Power-up to Write Operation 100 µs 326 PGM T6.1 TABLE 7: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C I/O(1) I/O Pin Capacitance V I/O = 0V 12 pF C IN(1) Input Capacitance V IN = 0V 6 pF Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 326 PGM T7.0 TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N END (1) Endurance 10,000 Cycles MIL-STD-883, Method 1033 TDR (1) Data Retention 100 Years JEDEC Standard A103 VZAP_HBM (1) ESD Susceptibility 1000 Volts JEDEC Standard A114 Human Body Model VZAP_MM (1) ESD Susceptibility 200 Volts JEDEC Standard A115 Machine Model ILTH (1) Latch Up 100 + I CC mA JEDEC Standard 78 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 326 PGM T8.3 TABLE 5: DC OPERATING CHARACTERISTICS VCC = 5V±10% Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=V IL,WE#=V IH , all I/Os open, Read 30 mA Address input = V IL/VIH, at f=1/TRC Min., VCC =VCC Max Write 50 mA CE#=WE#=V IL, OE#=V IH, VCC =VCC Max. ISB1 Standby VCC Current 3 mA CE#=V IH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 50 µA CE#=V CC -0.3V. (CMOS input) V CC = VCC Max. ILI Input Leakage Current 1 µA V IN =GND to VCC , VCC = VCC Max. ILO Output Leakage Current 1 µA V OUT =GND to VCC , VCC = VCC Max. VIL Input Low Voltage 0.8 V V CC = VCC Max. VIH Input High Voltage 2.0 V V CC = VCC Max. VOL Output Low Voltage 0.4 V I OL = 2.1 mA, VCC = VCC Min. VOH Output High Voltage 2.4 V I OH = -400µA, VCC = VCC Min. VH Supervoltage for A9 pin 11.4 12.6 V CE# = OE# =V IL, WE# = VIH IH Supervoltage Current 200 µA CE# = OE# = V IL, WE# = VIH, A9 = VH Max. for A9 pin 326 PGM T5.2

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VCC = 4.5-5.5V SST39SF020-70 SST39SF020-90 Symbol Parameter Min Max Min Max Units T RC Read Cycle time 70 90 ns TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ (1) CE# Low to Active Output 0 0 ns TOLZ (1) OE# Low to Active Output 0 0 ns TCHZ (1) CE# High to High-Z Output 15 20 ns TOHZ (1) OE# High to High-Z Output 15 20 ns TOH (1) Output Hold from Address Change 0 0 ns 326 PGM T9.2 TABLE 10: PROGRAM /ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte Program time 30 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 0 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH (1) WE# Pulse Width High 30 ns TCPH (1) CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH (1) Data Hold Time 0 ns TIDA (1) Software ID Access and Exit Time 150 ns TSE Sector Erase 10 ms TSCE Chip Erase 20 ms Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 326 PGM T10.4 Note: CL = 100 pF for 90 ns, CL = 30 pF for 70 ns

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 3: READ CYCLE TIMING DIAGRAM FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM 326 ILL F03.0 ADDRESS A 17-0 DQ 7-0 WE# OE# CE# TCE TRC TAA TOE TOLZVIH HIGH-Z TCLZ TOH TCHZ HIGH-Z DATA VALIDDATA VALID TOHZ 326 ILL F04.3 ADDRESS A 17-0 DQ 7-0 TDH TWPH TDS TWP TAH TAS TCH TCS CE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# WE# TBP

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM FIGURE 6: DATA # POLLING TIMING DIAGRAM 326 ILL F06.0 ADDRESS A 17-0 DQ 7 DD # D # D WE# OE# CE# TOEH TOE TCE TOES 326 ILL F05.3 ADDRESS A 17-0 DQ 7-0 TDH TCPH TDS TCP TAH TAS TCH TCS WE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# CE# TBP

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 7: TOGGLE BIT TIMING DIAGRAM FIGURE 8: WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM 326 ILL F07.0 ADDRESS A 17-0 DQ 6 WE# OE# CE# TOETOEH TCE TOES TWO READ CYCLES WITH SAME OUTPUTS NOTE: (1) TOGLE BIT OUTPUT IS ALWAYS HIGH FIRST. (1) Note: The device also supports CE# controlled sector erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) SA X = Sector Address 326 ILL F08.4 ADDRESS A 17-0 DQ 7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 3055AA 80 AA SA X OE# CE# SIX-BYTE CODE FOR SECTOR ERASE TSE TWP

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 10: SOFTWARE ID ENTRY AND READ 326 ILL F09.3 ADDRESS A 14-0 TIDA DQ 7-0 WE# SW0 SW1 SW2 5555 2AAA 5555 0000 0001 OE# CE# Three-byte sequence for Software ID Entry TWP TWPH TAA BF B655AA 90 FIGURE 9: WE# CONTROLLED CHIP ERASE TIMING DIAGRAM Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) 326 ILL F17.1 ADDRESS A 17-0 DQ 7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 1055AA 80 AA 5555 OE# CE# SIX-BYTE CODE FOR CHIP ERASE TSCE TWP

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 11: SOFTWARE ID EXIT AND RESET 326 ILL F10.0 ADDRESS A 14-0 DQ 7-0 TIDA TWP T WHP WE# SW0 SW1 SW2 5555 2AAA 5555 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET OE# CE# AA 55 F0

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 12: AC INPUT /OUTPUT REFERENCE WAVEFORMS AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% ↔ 90%) are <10 ns. FIGURE 13: A TEST LOAD EXAMPLE 326 ILL F12.1 TEST LOAD EXAMPLE TO TESTER TO DUT C L R L LOW R L HIGH VCC Note: VHT –VHIGH Test VLT–VLOW Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test 326 ILL F11.1 REFERENCE POINTS OUTPUTINPUT VHT VLT VHT VLT VIHT VILT

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 14: BYTE PROGRAM ALGORITHM 326 ILL F13.3 Start Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: A0 Address: 5555 Byte Address/Byte Data Wait for end of Program (TBP , Data# Polling bit, or Toggle bit operation) Program Completed

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 15: WAIT OPTIONS 326 ILL F14.4 Wait TBP , TSCE, or TSE Program/Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ 6 match? Read same byte Data# Polling Write Completed Write Completed Read byte Is DQ7 = true data? Read DQ 7 Byte Program Initiated Byte Program/ Sector Erase Initiated

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 16: SOFTWARE PRODUCT COMMAND FLOWCHARTS 326 ILL F15.1 Write data: AA Address: 5555 Software Product ID Entry Command Sequence Write data: 55 Address: 2AAA Write data: 90 Address: 5555 Wait TIDA Read Software ID Write data: AA Address: 5555 Software Product ID Exit & Reset Command Sequence Write data: 55 Address: 2AAA Write data: F0 Address: 5555 Write data: F0 Address: XX Return to normal operation Wait TIDA Wait TIDA Return to normal operation

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications FIGURE 17: ERASE COMMAND SEQUENCE 326 ILL F16.0 Write data: AA Address: 5555 Chip Erase Command Sequence Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: 55 Address: 2AAA Write data: 10 Address: 5555 Write data: AA Address: 5555 Wait TSCE Chip Erase to FFH Write data: AA Address: 5555 Sector Erase Command Sequence Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: 55 Address: 2AAA Write data: 30 Address: SAX Write data: AA Address: 5555 Wait TSE Sector Erase to FFH

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications Device Speed Suffix1 Suffix2 SST39SF020 - XXX - XX - XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Temperature Range C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns, 90 = 90 ns SST39SF020 Valid combinations SST39SF020-70-4C-WH SST39SF020-70-4C-NH SST39SF020-70-4C-PH SST39SF020-90-4C-WH SST39SF020-90-4C-NH SST39SF020-90-4C-PH SST39SF020-90-4C-U1 SST39SF020-70-4I-WH SST39SF020-70-4I-NH SST39SF020-90-4I-WH SST39SF020-90-4I-NH Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications PACKAGING DIAGRAMS 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE : NH 32-LEAD PLASTIC DUAL -IN-LINE PACKAGE (PDIP) SST PACKAGE CODE : PH 32.pdipPH-ILL.0 pin 1 index CL Optional Ejector Pin Indentation Shown for Conventional Mold Only Base Plane Seating Plane Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .170 .200 4 PLCS. .600 BSC.100 BSC .120 .150.016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 15˚ .600 .625 .530 .550 .030 .040 .013 .021 .490 .530 .075 .095 .015 Min. .125 .140 TOP VIEW SIDE VIEW BOTTOM VIEW 123 2 .026 .032 .400 BSC KO R EA 32.PLCC.NH-ILL.0 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. .050 BSC. .050 BSC. .020 High x .002 Deep Characters .076/.125 Dia. Ejector Pin 1.026 .032 .023 .029 .447 .453 .042 .048 .042 .048 .045 Dia. x .000/.010 Deep Polished (Optional) .547 .553 .585 .595 .485 .495 .020 R. MAX. .106 .112 R.x 30˚

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE : WH 32.TSOP-WH-ILL.0 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 1.10 0.90 PIN # 1 IDENT. DIA. 1.00 14.20 13.80 0.70 0.50

© 1998 Silicon Storage Technology, Inc. 326-10 12/98 Preliminary Specifications NOTES: