SST39LF512 SST
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©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 FEATURES:
- Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF512/010/020/040 – 2.7-3.6V for SST39VF512/010/020/040 Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 1 µA (typical) Sector-Erase Capability – Uniform 4 KByte sectors Fast Read Access Time: – 45 ns for SST39LF512/010/020/040 – 55 ns for SST39LF020/040 – 70 and 90 ns for SST39VF512/010/020/040 Latched Address and Data Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) for SST39LF/VF512 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040 Automatic Write Timing – Internal V PP Generation End-of-Write Detection – Toggle Bit – Data# Polling CMOS I/O Compatibility JEDEC Standard – Flash EEPROM Pinouts and command sets Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 48-ball TFBGA (6mm x 8mm) for 1 Mbit PRODUCT DESCRIPTION The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST ’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tun- neling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/ 010/020/040 devices write (Program or Erase) with a 3.0- 3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indi- cate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufac- tured, and tested for a wide spectrum of applications, they are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configu- ration, or data memory. For all system applications, they significantly improves performance and reliability, while low- ering power consumption. They inherently use less energy during Erase and Program than alternative flash technolo- gies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program oper- ation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. To meet surface mount requirements, the SST39LF512/ 010/020/040 and SST39VF512/010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. The 39LF/VF010 is also offered in a 48-ball TFBGA package. See Figures 1 and 2 for pinouts. SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 Device Operation Commands are used to initiate the memory operation func- tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high imped- ance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Byte-Program Operation The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the ris- ing edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initi- ated after the rising edge of the fourth WE# or CE#, which- ever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program opera- tion, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector- Erase operation is initiated by executing a six-byte-com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit meth- ods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the Chip- Erase operation will be ignored. Write Operation Status Detection The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detec- tion includes two status bits: Data# Polling (DQ 7) and Tog- gle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Pro- gram or Erase operation. The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid.
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 Data# Polling (DQ7) When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ 7 will produce a ‘0’. Once the internal Erase opera- tion is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip- Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia- gram and Figure 16 for a flowchart. Data Protection The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Software Data Protection (SDP) The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide the JEDEC approved Software Data Pro- tection scheme for all data alteration operation, i.e., Pro- gram and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program opera- tion, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power- down. Any Erase operation requires the inclusion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T RC . Product Identification The Product Identification mode identifies the devices as the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multi- ple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 17 for the Software ID entry command sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accom- plished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing wave- form, and Figure 17 for a flowchart. TABLE 1: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST39LF/VF512 0001H D4H SST39LF/VF010 0001H D5H SST39LF/VF020 0001H D6H SST39LF/VF040 0001H D7H T1.1 395
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 1: P IN ASSIGNMENTS FOR 32-LEAD PLCC Y -Decoder I/O Buffers and Data Latches 395 ILL B1.1 Address Buffers & Latches X-Decoder DQ 7 - DQ0 Memory Address OE# CE# WE# SuperFlash Memory Control Logic FUNCTIONAL BLOCK DIAGRAM DQ0 DQ0 DQ0 DQ0 A14 A13 A11 OE# A10 CE# DQ7 A14 A13 A11 OE# A10 CE# DQ7 A14 A13 A11 OE# A10 CE# DQ7 A14 A13 A11 OE# A10 CE# DQ7 4 3 2 1 32 31 30 A12 A15 NC NC VDD WE# NC A12 A15 A16 NC VDD WE# NC A12 A15 A16 NC VDD WE# A17 A12 A15 A16 A18 VDD WE# A17 32-lead PLCC Top View 395 ILL F02b.3 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512 SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 2: P IN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM ) FIGURE 3: P IN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM ) FOR 1 MBIT A11 A13 A14 NC WE# VDD NC NC A15 A12 A11 A13 A14 NC WE# VDD NC A16 A15 A12 A11 A13 A14 A17 WE# VDD NC A16 A15 A12 A11 A13 A14 A17 WE# VDD A18 A16 A15 A12 SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 395 ILL F01.0 Standard Pinout Top View Die Up 395 ILL F01a.0.eps A B C D E F G H SST39LF/VF010 TOP VIEW (balls facing down) A14 WE# NC A13 NC NC NC A15 A11 NC NC A16 A12 NC NC NC NC DQ5 DQ2 DQ0 NC A10 NC DQ3 NC CE# NC DQ6 VDD VDD NC OE# VSS DQ7 DQ4 NC DQ1 VSS
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 TABLE 2: P IN DESCRIPTION Symbol Pin Name Functions AMS 1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS -A12 address lines will select the sector. During Block-Erase AMS -A16 address lines will select the block. DQ 7-DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V DD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040 2.7-3.6V for SST39VF512/010/020/040 VSS Ground NC No Connection Unconnected pins. T2.1 395 1. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 TABLE 3: O PERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read V IL VIL VIH D OUT AIN Program V IL VIH VIL D IN AIN Erase V IL VIH VIL X1 1. X can be VIL or VIH, but no other value. Sector address, XXH for Chip-Erase Standby V IH XX H i g h Z X Write Inhibit X V IL XH i g h Z / DOUT X XX V IH High Z/ DOUT X Product Identification Software Mode V IL VIL VIH See Table 4 T3.4 395
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 TABLE 4: S OFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Addr 1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA 2 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA X3 30H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit6 XXH F0H Software ID Exit6 5555H AAH 2AAAH 55H 5555H F0H T4.2 395 1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512. Addresses A15-A16 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF010. Addresses A15-A17 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF020. Addresses A15-A18 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF040. 2. BA = Program Byte address 3. SA X for Sector-Erase; uses AMS -A12 address lines AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 4. The device does not remain in Software Product ID Mode if powered down. 5. With A MS -A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST39LF/VF512 Device ID = D4H, is read with A0 = 1 SST39LF/VF010 Device ID = D5H, is read with A0 = 1 SST39LF/VF020 Device ID = D6H, is read with A0 = 1 SST39LF/VF040 Device ID = D7H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) DD + 0.5V 1. Outputs shorted for no more than one second. No more than one output shorted at a time. O PERATING RANGE FOR SST39LF512/010/020/040 Range Ambient Temp V DD Commercial 0 °C to +70°C 3.0-3.6V O PERATING RANGE FOR SST39VF512/010/020/040 Range Ambient Temp V DD Commercial 0 °C to +70°C 2.7-3.6V Industrial -40 °C to +85°C 2.7-3.6V AC C ONDITIONS OF TEST Output Load C L = 30 pF for SST39LF512/010/020/040 C L = 100 pF for SST39VF512/010/020/040 See Figures 13 and 14
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 TABLE 5: DC O PERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040 Symbol Parameter Limits Test ConditionsMin Max Units IDD Power Supply Current Address input=V IL/VIH, at f=1/TRC Min VDD =V DD Max Read 20 mA CE#=OE#=V IL, WE#=VIH, all I/Os open Write 20 mA CE#=WE#=V IL, OE#=VIH ISB Standby VDD Current 15 µA CE#=V IHC, VDD =V DD Max ILI Input Leakage Current 1 µA V IN=GND to VDD , VDD =VDD Max ILO Output Leakage Current 10 µA V OUT =GND to VDD , VDD =V DD Max VIL Input Low Voltage 0.8 V V DD =V DD Min VIH Input High Voltage 0.7V DD VV DD =V DD Max VIHC Input High Voltage (CMOS) V DD -0.3 V V DD =V DD Max VOL Output Low Voltage 0.2 V I OL =100 µA, VDD =V DD Min VOH Output High Voltage V DD -0.2 V I OH =-100 µA, VDD =VDD Min T5.2 395 TABLE 6: R ECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units T PU-READ 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Power-up to Read Operation 100 µs TPU-WRITE 1 Power-up to Program/Erase Operation 100 µs T6.1 395 TABLE 7: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C I/O1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF C IN1 Input Capacitance V IN = 0V 6 pF T7.0 395 TABLE 8: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N END 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Endurance 10,000 Cycles JEDEC Standard A117 TDR 1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 + I DD mA JEDEC Standard 78 T8.2 395
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 AC CHARACTERISTICS TABLE 9: R EAD CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040 Symbol Parameter SST39LF512-45 SST39LF010-45 SST39LF020-45 SST39LF040-45 SST39LF020-55 SST39LF040-55 SST39VF512-70 SST39VF010-70 SST39VF020-70 SST39VF040-70 SST39VF512-90 SST39VF010-90 SST39VF020-90 SST39VF040-90 UnitsMin Max Min Max Min Max Min Max T RC Read Cycle Time 45 55 70 90 ns TCE Chip Enable Access Time 45 55 70 90 ns TAA Address Access Time 45 55 70 90 ns TOE Output Enable Access Time 30 30 35 45 ns TCLZ 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. CE# Low to Active Output 0 0 0 0 ns TOLZ 1 OE# Low to Active Output 0 0 0 0 ns TCHZ 1 CE# High to High-Z Output 15 15 25 30 ns TOHZ 1 OE# High to High-Z Output 15 15 25 30 ns TOH 1 Output Hold from Address Change 0000 n s T9.2 395 TABLE 10: PROGRAM /ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte-Program Time 20 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. WE# Pulse Width High 30 ns TCPH 1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns TDH 1 Data Hold Time 0 ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms T10.1 395
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 4: R EAD CYCLE TIMING DIAGRAM FIGURE 5: WE# C ONTROLLED PROGRAM CYCLE TIMING DIAGRAM 395 ILL F03.0 ADDRESS A MS-0 DQ 7-0 WE# OE# CE# TCE TRC TAA TOE TOLZVIH HIGH-Z TCLZ TOH TCHZ HIGH-Z DATA VALIDDATA VALID TOHZ Note: A MS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 395 ILL F04.0 ADDRESS A MS-0 DQ 7-0 TDH TWPH TDS TWP TAH TAS TCH TCS CE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# WE# TBP Note: A MS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 6: CE# C ONTROLLED PROGRAM CYCLE TIMING DIAGRAM FIGURE 7: D ATA # POLLING TIMING DIAGRAM 395 ILL F05.0 ADDRESS A MS-0 DQ 7-0 TDH TCPH TDS TCP TAH TAS TCH TCS WE# SW0 SW1 SW2 5555 2AAA 5555 ADDR AA 55 A0 DATA INTERNAL PROGRAM OPERATION STARTS BYTE (ADDR/DATA) OE# CE# TBP Note: A MS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 395 ILL F06.0 ADDRESS A MS-0 DQ 7 DD # D # D WE# OE# CE# TOEH TOE TCE TOES Note: A MS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 8: T OGGLE BIT TIMING DIAGRAM FIGURE 9: WE# C ONTROLLED SECTOR -ERASE TIMING DIAGRAM 395 ILL F07.0 ADDRESS A MS-0 DQ 6 WE# OE# CE# TOETOEH TCE TOES TWO READ CYCLES WITH SAME OUTPUTSNote: A MS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 334 ILL F08.0 ADDRESS A MS-0 DQ 7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 3055AA 80 AA SA X OE# CE# SIX-BYTE CODE FOR SECTOR-ERASE TSE TWP Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SA X = Sector Address AMS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 10: WE# C ONTROLLED CHIP-ERASE TIMING DIAGRAM FIGURE 11: SOFTWARE ID ENTRY AND READ 334 ILL F17.0 ADDRESS A MS-0 DQ 7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 5555 2AAA 2AAA 5555 5555 55 1055AA 80 AA 5555 OE# CE# SIX-BYTE CODE FOR CHIP-ERASE TSCE TWP Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) AMS = Most significant address AMS =A 15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 395 ILL F09.2 Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040. ADDRESS A 14-0 TIDA DQ 7-0 WE# SW0 SW1 SW2 5555 2AAA 5555 0000 0001 OE# CE# Three-byte sequence for Software ID Entry TWP TWPH TAA BF Device ID55AA 90
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 12: SOFTWARE ID EXIT AND RESET 395 ILL F10.0 ADDRESS A 14-0 DQ 7-0 TIDA TWP T WHP WE# SW0 SW1 SW2 5555 2AAA 5555 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET OE# CE# AA 55 F0
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 13: AC INPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 14: A TEST LOAD EXAMPLE 395 ILL F12.1 REFERENCE POINTS OUTPUTINPUT VIT VIHT VILT VOT AC test inputs are driven at VIHT (0.9 VDD ) for a logic “1” and VILT (0.1 VDD ) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD ) and VOT (0.5 VDD ). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Tes t VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 395 ILL F11.1 TO TESTER TO DUT C L
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 15: BYTE -PROGRAM ALGORITHM 395 ILL F13.1 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP , Data# Polling bit, or Toggle bit operation) Program Completed
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 16: W AIT OPTIONS 395 ILL F14.0 Wait TBP , TSCE, or TSE Byte-Program/ Erase Initiated Internal Timer Toggle Bit Ye s Ye s No No Program/Erase Completed Does DQ 6 match? Read same byte Data# Polling Program/Erase Completed Program/Erase Completed Read byte Is DQ7 = true data? Read DQ 7 Byte-Program/ Erase Initiated Byte-Program/ Erase Initiated
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 17: SOFTWARE ID COMMAND FLOWCHARTS 395 ILL F15.2 Load data: AAH Address: 5555H Software ID Entry Command Sequence Load data: 55H Address: 2AAAH Load data: 90H Address: 5555H Wait TIDA Read Software ID Load data: AAH Address: 5555H Software ID Exit & Reset Command Sequence Load data: 55H Address: 2AAAH Load data: F0H Address: 5555H Load data: F0H Address: XXH Return to normal operation Wait TIDA Wait TIDA Return to normal operation
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 FIGURE 18: ERASE COMMAND SEQUENCE 395 ILL F16.1 Load data: AAH Address: 5555H Chip-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: AAH Address: 5555H Wait TSCE Chip erased to FFH Load data: AAH Address: 5555H Sector-Erase Command Sequence Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 55H Address: 2AAAH Load data: 30H Address: SAX Load data: AAH Address: 5555H Wait TSE Sector erased to FFH
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST39x Fxxx -X X -X X -X X Package Modifier H = 32 leads K = 48 balls Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) B3 = TFBGA (6mm x 8mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 55 = 55 ns 70 = 70 ns 90 = 90 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 Valid combinations for SST39LF512 SST39LF512-45-4C-NH SST39LF512-45-4C-WH Valid combinations for SST39VF512 SST39VF512-70-4C-NH SST39VF512-70-4C-WH SST39VF512-90-4C-NH SST39VF512-90-4C-WH SST39VF512-90-4C-U4 SST39VF512-70-4I-NH SST39VF512-70-4I-WH SST39VF512-90-4I-NH SST39VF512-90-4I-WH Valid combinations for SST39LF010 SST39LF010-45-4C-NH SST39LF010-45-4C-WH SST39LF010-45-4C-B3K Valid combinations for SST39VF010 SST39VF010-70-4C-NH SST39VF010-70-4C-WH SST39VF010-70-4C-B3K SST39VF010-90-4C-NH SST39VF010-90-4C-WH SST39VF010-90-4C-B3K SST39VF010-90-4C-U4 SST39VF010-70-4I-NH SST39VF010-70-4I-WH SST39VF010-70-4I-B3K SST39VF010-90-4I-NH SST39VF010-90-4I-WH SST39VF010-90-4I-B3K Valid combinations for SST39LF020 SST39LF020-45-4C-NH SST39LF020-45-4C-WH SST39LF020-55-4C-NH SST39LF020-55-4C-WH Valid combinations for SST39VF020 SST39VF020-70-4C-NH SST39VF020-70-4C-WH SST39VF020-90-4C-NH SST39VF020-90-4C-WH SST39VF020-90-4C-U4 SST39VF020-70-4I-NH SST39VF020-70-4I-WH SST39VF020-90-4I-NH SST39VF020-90-4I-WH Valid combinations for SST39LF040 SST39LF040-45-4C-NH SST39LF040-45-4C-WH SST39LF040-55-4C-NH SST39LF040-55-4C-WH Valid combinations for SST39VF040 SST39VF040-70-4C-NH SST39VF040-70-4C-WH SST39VF040-90-4C-NH SST39VF040-90-4C-WH SST39VF040-90-4C-U1 SST39VF040-70-4I-NH SST39VF040-70-4I-WH SST39VF040-90-4I-NH SST39VF040-90-4I-WH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 PACKAGING DIAGRAMS 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE : NH 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH .030 .040 .013 .021 .490 .530 .075 .095 .015 Min. .125 .140 TOP VIEW SIDE VIEW BOTTOM VIEW 123 2 .026 .032 .400 BSC 32.PLCC.NH-ILL.2 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. .050 BSC. .050 BSC. .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 Optional Pin #1 Identifier .547 .553 .585 .595 .485 .495 .020 R. MAX. .106 .112 R.x 30˚ 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 Pin # 1 Identifier 14.20 13.80 0.70 0.50
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 48-BALL THIN-PROFILE , FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE : B3K A1 CORNER H G F E D C B AA B C D E F G H BOTTOM VIEW TOP VIEW SIDE VIEW SEATING PLANE 0.35 ± 0.05 1.10 ± 0.10 0.15 6.00 ± 0.20 0.45 ± 0.05 (48X) A1 CORNER 8.00 ± 0.20 0.80 4.00 0.80 5.60 48ba-TFBGA-B3K-6x8-450mic-ILL.0 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 1mm
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 ©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • T elephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com