3977

3977 ALLEGRO

Document overview

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Technical content

at TA = +25°C Logic Input Voltage Range, V IN Package Power Dissipation, Operating Temperature Range, T A Storage Temperature Range, * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Data Sheet26184.22D 3977 The A3977xED and A3977xLP are complete microstepping motor drivers with built-in translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current- decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex µP is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3977 is supplied in a choice of two power packages, a 44-pin plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28- pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is available in a lead-free version (100% matte tin leadframe).

FEATURES

■ ±2.5 A, 35 V Output Rating ■ Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical ■ Automatic Current Decay Mode Detection/Selection ■ 3.0 V to 5.5 V Logic Supply Voltage Range ■ Mixed, Fast, and Slow Current Decay Modes ■ Home Output ■ Synchronous Rectification for Low Power Dissipation ■ Internal UVLO and Thermal Shutdown Circuitry ■ Crossover-Current Protection A3977xED (PLCC) 65 4321 44 43 42 41 40 17 29 2827262524232221201918 Dwg. PP-075-1 GND GND LOGIC SUPPLY NC GND GND REF RC NC NC STEP VREG GND GND V CP CP1 CP2 NC CHARGE PUMP VDD VBB1 VBB2 NC NC PFD RC1 ÷8 REG PWM TIMER TRANSLATOR & CONTROL LOGIC GND GND SENSE ENABLE LOAD SUPPLY GND SLEEP HOME DIR OUT OUT OUT2A SENSE GND GND GND LOAD SUPPLY OUT2B MS MS RESET SR Always order by complete part number: Part Number Package A3977KED 44-pin PLCC A3977KLP 28-pin TSSOP A3977SED 44-pin PLCC A3977SED-T 44-pin PLCC; Lead-free A3977SLP 28-pin TSSOP A3977SLP-T 28-pin TSSOP; Lead-free

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Copyright © 2002, 2003 Allegro MicroSystems, Inc. FUNCTIONAL BLOCK DIAGRAM DMOS H BRIDGE DMOS H BRIDGE GATE DRIVE TRANSLATOR CHARGE PUMP CP 2 CP 1 VCP LOAD SUPPLY VBB1 OUT 1A OUT 1B OUT 2A OUT 2B VBB2 SENSE 1 VCP Dwg. FP-050-2 VREG PWM TIMER PWM TIMER PWM LATCH BLANKING MIXED DECAY CONTROL LOGIC UVLO AND FAULT REGULATOR BANDGAP DAC DAC 2 V SENSE 1 PWM LATCH BLANKING MIXED DECAY SENSE 2 REF LOGIC SUPPLY VDD STEP DIR MS 1 SLEEP MS 2 HOME ENABLE RC 1 RESET SR PFD RC 2 REF. SUPPLY VPFD

Table 1. Microstep Resolution Truth Table

• Measured on JEDEC standard “High-K” four-layer board.

(1935 mm2) copper ground area.

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range V BB Operating 8.0 – 35 V During sleep mode 0 – 35 V Output Leakage Current I DSS VOUT = VBB – <1.0 20 µA VOUT = 0 V – <1.0 -20 µA Output On Resistance r DS(on) Source driver, IOUT = -2.5 A – 0.45 0.57 Ω Sink driver, IOUT = 2.5 A – 0.36 0.43 Ω Body Diode Forward Voltage V F Source diode, IF = -2.5 A – – 1.4 V Sink diode, IF = 2.5 A – – 1.4 V Motor Supply Current I BB fPWM < 50 kHz – – 8.0 mA Operating, outputs disabled – – 6.0 mA Sleep mode – – 20 µA Control Logic Logic Supply Voltage Range V DD Operating 3.0 5.0 5.5 V Logic Input Voltage V IN(1) 0.7VDD ––V VIN(0) – – 0.3V DD V Logic Input Current I IN(1) VIN = 0.7VDD -20 <1.0 20 µA IIN(0) VIN = 0.3VDD -20 <1.0 20 µA Maximum STEP Frequency f STEP 500* – – kHz HOME Output Voltage V OH IOH = -200 µA 0.7V DD – – V VOL IOL = 200 µA – – 0.3V DD V Blank Time t BLANK Rt = 56 kΩ , Ct = 680 pF 700 950 1200 ns Fixed Off Time t off Rt = 56 kΩ , Ct = 680 pF 30 38 46 µs continued next page …

MICROSTEPPPING DMOS DRIVER WITH TRANSLATOR www.allegromicro.com 5 ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Characteristic Symbol Test Conditions Limits Min. Typ. Max. Units Control Logic (cont’d) Mixed Decay Trip Point PFDH – 0.6V DD –V PFDL – 0.21V DD –V Ref. Input Voltage Range V REF Operating 0 – V DD V Reference Input Current I REF – 0 ±3.0 µA Gain (Gm) Error (note 3) EG VREF = 2 V, Phase Current = 38.27% – – ±10 % VREF = 2 V, Phase Current = 70.71% – – ±5.0 % VREF = 2 V, Phase Current = 100.00% – – ±5.0 % Crossover Dead Time t DT SR enabled 100 475 800 ns Thermal Shutdown Temp. T J – 165 – °C Thermal Shutdown Hysteresis ∆TJ –1 5 – ° C UVLO Enable Threshold V UVLO Increasing VDD 2.45 2.7 2.95 V UVLO Hysteresis ∆VUVLO 0.05 0.10 – V Logic Supply Current I DD fPWM < 50 kHz – – 12 mA Outputs off – – 10 mA Sleep mode – – 20 µA * Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8)

by the output of the translator. will be set by the PFD input (fast, slow or mixed decay). are ignored until the RESET input goes high. figures for home state conditions). table 1. Changes to these inputs do not take effect until the STEP command (see figure). input will determine the direction of rotation of the motor. (fast- or mixed-decay modes). all other modes VREF should not exceed 4 V.

www.allegromicro.com 7 Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, t off, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: toff = RTCT RC Blanking. In addition to the fixed off time of the PWM control circuit, the CT component sets the compara- tor blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time t BLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capaci- tor should be connected between CP1 and CP2 for pump- ing purposes. A 0.22 µF ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE). This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS 1, MS2) are all active independent of the ENABLE input state. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on VCP ) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low V DD , the under- voltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6V DD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 µF capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6V DD and 0.21VDD , the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: t FD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD , the device will switch to slow-decay mode for the remainder of the fixed off-time period. Functional Description (cont’d)

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Synchronous Rectification. When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low r DS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. The synchronous rectification can be set in either active mode or disabled mode. Functional Description (cont’d) Active Mode. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conduct- ing in the reverse direction. Disabled Mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes. Timing Requirements (TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground) A B C D 50%STEP MS1/MS2/ DIR/RESET Dwg. WP-042 SLEEP E A. Minimum Command Active Time B. Minimum Command Active Time

www.allegromicro.com 9 Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB , should be decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be con- nected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. Applications Information Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (R S) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in R S due to their contact resistance. Allegro MicroSystems recommends a value of RS given by R S = 0.5/ITRIP max Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shut- down has a hysteresis of approximately 15°C.

Table 2. Step Sequencing

www.allegromicro.com 11 Dwg. WK-004-15 PHASE 1 CURRENT PHASE 2 CURRENT SLOW DECAY STEP INPUT HOME OUTPUT 70.7% –70.7% 70.7% –70.7% SLOW DECAY Full-Step Operation MS1 = MS2 = L, DIR = H The vector addition of the output currents at any step is 100%.

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Dwg. WK-004-14 PHASE 1 CURRENT PHASE 2 CURRENT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY STEP INPUT HOME OUTPUT 100% –100% 100% –100% SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY 70.7% –70.7% 70.7% –70.7% Half-Step Operation MS1 = H, MS2 = L, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (V PFD ). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.

www.allegromicro.com 13 Dwg. WK-004-13 PHASE 1 CURRENT PHASE 2 CURRENT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY STEP INPUT HOME OUTPUT 100% –100% 100% –100% SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY 38.3% 70.7% –70.7% 70.7% –70.7% –38.3% 38.3% –38.3% Quarter-Step Operation MS1 = L, MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (V PFD ). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Dwg. WK-004-12 PHASE 2 CURRENT 100% –100% SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY PHASE 1 CURRENT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY STEP INPUT HOME OUTPUT 100% –100% 70.7% 38.3% –70.7% –38.3% 70.7% 38.3% –70.7% –38.3%

8 Microstep/Step Operation

MS1 = MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (V PFD ). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels.

www.allegromicro.com 15 Terminal List Terminal A3977xLP A3977xED Name Terminal Description (TSSOP) (PLCC) GND Analog and power ground – 44, 1, 2 SENSE

1 Sense resistor for bridge 1 1 3

1A DMOS H bridge 1 output A 4 6 NC No (internal) connection – 7, 8 PFD Mixed decay setting 5 9 RC

1 Analog Input for fixed offtime – bridge 1 6 10

GND Analog and power ground – 11, 12, 13 AGND Analog ground 7* – REF Gm reference input 8 14 RC

2 Analog input for fixed offtime – bridge 2 9 15

LOGIC SUPPLY V DD, the logic supply voltage 10 16 NC No (internal) connection – 17 OUT 2A DMOS H bridge 2 output A 11 18 MS2 Logic input 12 19 MS1 Logic input 13 20 SENSE2 Sense resistor for bridge 2 14 21 GND Analog and power ground – 22, 23, 24 LOAD SUPPLY

2 VBB2, the load supply for bridge 2 15 25

2B DMOS H bridge 2 output B 18 28 NC No (internal) connection – 29, 30 STEP Logic input 19 31 V REG Regulator decoupling 20 32 PGND Power ground 21* – GND Analog and power ground – 33, 34, 35 V CP Reservoir capacitor 22 36 CP1 Charge pump capacitor 23 37 CP2 Charge pump capacitor 24 38 NC No (internal) connection – 39 OUT 1B DMOS H bridge 1 output B 25 40 ENABLE Logic input 26 41 SLEEP Logic input 27 42 LOAD SUPPLY1 VBB1, the load supply for bridge 1 28 43 * AGND and PGND on the TSSOP package must be connected together externally.

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR A3977xED NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece. 4. Supplied in standard sticks/tubes of 27 devices or add “TR ” to part number for tape and reel. 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 16.662 16.510 8.10 7.39 8.10 7.39 Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only)

www.allegromicro.com 17 A3977xLP NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 49 devices or add “TR ” to part number for tape and reel. 28 15 1 2 3 0.386 0.378 0.012 0.0075 0.0472 MAX 0.0059 0.00 0.026 BSC 0.177 0.169 0.118 0.197 0.0079 0.0035 0.030 0.018 0° TO 8° GAUGE PLANE 0.0098 BSC SEATING PLANE 0.0394 REF Dwg. MA-008-30A in EXPOSED THERMAL PAD INDEX AREA 0.260 0.244 28 15 1 2 3 9.80 9.60 0.30 0.19 1.20 MAX 0.15 0.00 Dwg. MA-008-30A mm 0.65 BSC 4.50 4.30 3.0 5.0 0.20 0.09 6.60 6.20 0.75 0.45 0° TO 8° GAUGE PLANE 0.25 BSC SEATING PLANE 1.00 REF INDEX AREA EXPOSED THERMAL PAD Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions)

Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.