3974

3974_1 ALLEGRO

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5b3.91392 3974 DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER Designed for pulse-width modulated (PWM) current control of two dc motors, the A3974SED is capable of output currents to ±1.5 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. Independant ENABLE input terminals are provided for use in controlling the speed and torque of each dc motor with externally applied PWM control signals. Synchronous rectification circuitry allows the load current to flow through the low rDS(on) of the DMOS output driver during the current decay. This feature will eliminate the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of VDD and the charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3974SED is supplied in a 44-lead plastic PLCC with four copper batwing tabs for maximum heat dissipation. The power tabs are at ground potential and need no electrical isola- tion.

FEATURES

■ ±1.5 A, 50 V Continuous Output Rating ■ Low rDS(on) DMOS Output Drivers ■ Programmable Slow, Fast, and Mixed Current-Decay Modes ■ Serial-Interface Controls Chip Functions ■ Synchronous Rectification for Low Power Dissipation ■ Internal UVLO and Thermal Shutdown Circuitry ■ Crossover-Current Protection ■ Sleep and Idle Modes ABSOLUTE MAXIMUM RATINGS at TA = +25°C Logic Input Voltage Range, VIN Sense Voltage (dc), VS Operating Temperature Range, Storage Temperature Range, Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. SERIAL PORT 17 29 Dwg. PP-073 GND GND LOGIC SUPPLY GND GND SENSE1 OUT1A NC STROBE CLOCK DATA GND GND REF1 REF2 NC OUT2A NC SENSE2 GND GND GND LOAD SUPPLY2 ENABLE2 OUT2B NC VREG SLEEP OSC GND GND CP CP1 CP2 NC OUT1B NC ENABLE1 LOAD SUPPLY1 GND NC NC NC NC PROGRAM PWM TIMER CHARGE PUMP VDD VBB1 VBB2 LOGIC LOGIC PROGRAM PWM TIMER Selection Guide Part Number Pb-free* Package Packing A3974SED-T Yes 44-pin PLCC 27 per tube A3974SEDTR-T Yes 44-pin PLCC 450 per reel *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for LAST TIME BUY orders: April 27, 2007. These variants include: A3974SED and A3974SEDTR..

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-50002 FUNCTIONAL BLOCK DIAGRAM Copyright © 2001 Allegro MicroSystems, Inc. CHARGE PUMP BANDGAP VDD CREG TSD UNDER- VOLTAGE & FAULT DETECT CHARGE PUMP BANDGAP REGULATOR VDD VBB1 LOGIC SUPPLY VREG CP1 CP CP2 LOAD SUPPLY 1 GATE DRIVE SLEEP MODE CONTROL LOGIC PHASE SYNC RECT MODE SYNC RECT DISABLE MODE PROGRAMMABLE PWM TIMER SENSE 1 R S1 FIXED OFF BLANK DECAY ENABLE 1 OSC CLOCK DATA STROBE REFERENCE BUFFER & DIVIDER OUT 1A OUT 1B REF 1 VREF C S1 PROGRAMMABLE PWM TIMER FIXED OFF BLANK DECAY GATE DRIVE Dwg. FP-048-1 CONTROL LOGIC PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT SENSE 2 R S2 ENABLE 2 REFERENCE BUFFER & DIVIDER OUT 2A OUT 2B REF 2 VREF2 C S2 VBB2 LOAD SUPPLY SERIAL PORT CHARGE PUMP TO PWM TIMER ZERO CURRENT DETECT CURRENT SENSE ZERO CURRENT DETECT CURRENT SENSE

3www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range V BB Operating 15 — 50 V During sleep mode 0 — 50 V Output Leakage Current I DSS VOUT = VBB — <1.0 20 µA VOUT = 0 V — <-1.0 -20 µA Output ON Resistance r DS(on) Source driver, IOUT = -1.5 A — 0.5 0.55 Ω Sink driver, IOUT = 1.5 A — 0.315 0.35 Ω Body Diode Forward Voltage V F Source diode, IF = 1.5 A — — 1.2 V Sink diode, IF = 1.5 A — — 1.2 V Load Supply Current I BB fPWM < 50 kHz — 4.0 7.0 mA Charge pump on, outputs disabled — 2.0 5.0 mA Sleep or idle mode — — 20 µA Control Logic Logic Supply Voltage Range V DD Operating 4.5 5.0 5.5 V Logic Input Voltage V IN(1) 2.0 — — V VIN(0) — — 0.8 V Logic Input Current I IN(1) VIN = 2.0 V — <1.0 ±20 µA (except ENABLE) IIN(0) VIN = 0.8 V — <1.0 ±20 µA ENABLE Input Current I EN(1) VEN = 2.0 V — 40 100 µA IEN(0) VEN = 0.8 V — 16 30 µA OSC Input Frequency f OSC 2.9 — 6.1 MHz OSC Input Duty Cycle — 40 — 60 % OSC Input Hysterisis ∆VIN 200 — 400 mV Reference Input Voltage Range V REF Operating 0 — 2.6 V continued next page ...

Worcester, Massachusetts 01615-0036 (508) 853-50004 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Control Logic (continued) Reference Input Current I REF VREF = 2.6 V — — ±1.0 µA Reference Input Offset Voltage V IO — ±10 — mV Reference Divider Ratio V REF/VS D16 = 1 — 10 — — D16 = 0 — 5.0 — — Gain (Gm) Error (note 3) E G VREF = 2.6 V, D16 = 0 — 0 ±4.0 % VREF = 0.5 V, D16 = 0 — 0 ±14 % VREF = 2.6 V, D16 = 1 — 0 ±4.0 % VREF = 0.5 V, D16 = 1 — 0 ±10 % Propagation Delay Time t pd 50% TO 90%: PWM change to source on 600 750 1000 ns PWM change to source off 50 150 350 ns PWM change to sink on 600 750 1000 ns PWM change to sink off 50 150 350 ns Crossover Delay Time t COD SR enabled 300 600 1000 ns Thermal Shutdown Temperature T J — 165 — °C Thermal Shutdown Hysteresis ∆TJ —1 5— °C UVLO Enable Threshold V UVLO Increasing VDD 3.9 4.2 4.45 V UVLO Hysteresis ∆VUVLO 0.05 0.10 — V Logic Supply Current I DD fPWM < 50 kHz — — 10 mA Outputs off — — 8.0 mA Idle mode (D18 = 1, D19 = 0) — — 1.5 mA Sleep mode (inputs below 0.5 V) — — 100 µA NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. E G = [(VREF/Range) - VS]/(VREF/Range). ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless otherwise noted), continued.

5www.allegromicro.com Serial Interface. The A3974SED is controlled via a 3-wire (clock, data,strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is written as two 20- bit words: 1 bit to select the word and 19 bits of data. The data is clocked in starting with D19. Word 0 Bit Assignments Select Word 0 (D18 = 0) Bit Function D0 Bridge 1 blank time LSB D1 Bridge 1 blank time MSB D2 Bridge 1 off-time LSB D3 Bridge 1 off-time bit 1 D4 Bridge 1 off-time bit 2 D5 Bridge 1 off-time bit 3 D6 Bridge 1 off-time MSB D7 Bridge 1 fast-decay time bit LSB D8 Bridge 1 fast-decay time bit 1 D9 Bridge 1 fast-decay time bit 2 D10 Bridge 1 fast-decay time MSB D11 Bridge 1 sync. rect. control D12 Bridge 1 sync. rect. control D13 Bridge 1 external PWM mode D14 Bridge 1 enable D15 Bridge 1 phase D16 Bridge 1 reference range select D17 Bridge 1 internal PWM mode D18 Word select = 0 D19 Test mode D0 – D1 Blank Time. The current-sense comparator is blanked when any output driver is switched on, according to the table below. f osc is the oscillator input frequency. D1 D0 Blank Time 004 / f OSC 016 / f OSC 1 0 12/f OSC 1 1 24/f OSC D2 – D6 Fixed Off Time. This five-bit word sets the fixed off-time for the internal PWM control circuitry. The off-time is defined by t off =(8 [1 + N]/fOSC) - 1/fOSC where N = 0 .... 31 For example, with an oscillator frequency of 4 MHz, the fixed off-time will be adjustable from 1.75 µs to 63.75 µs in increments of 2 µs. D7 – D10 Fast Decay Time. This four-bit word sets the fast- decay portion of the fixed off-time for the internal PWM control circuitry. This will only have impact if mixed-decay mode is selected (via bit D17). For t fd > toff, the device will effectively operate in fast-decay mode. The fast-decay portion is defined by t fd = (8[1 + N]/fOSC] - 1/fOSC where N = 0 .... 15 For example, with an oscillator frequency of 4 MHz, the fast- decay time will be adjustable from 1.75 µs to 31.75 µs in increments of 2 µs. D11 – D12 Synchronous Rectification. D12 D11 Synchronous Rectifier 0 0 Disabled 0 1 Low side only 1 0 Active 1 1 Passive The different modes of operation are described in the synchro- nous rectification section of the functional description. D13 External PWM Decay Mode. This bit determines the current-decay mode when using ENABLE chopping for external PWM current control. D13 Mode

0 Fast

1 Slow

continued next page ...

Worcester, Massachusetts 01615-0036 (508) 853-50006 FUNCTIONAL DESCRIPTION (continued) continued next page ... D14 Enable Logic. This bit, in conjuction with ENABLE, determines if the output drivers are in the chopped or on state. ENABLE1 D14 Mode 0 0 Chopped 10O n 01O n 1 1 Chopped D15 Phase Logic. This bit determines if the device is operating in the forward or reverse state. D15 State OUT A OUTB

0 Reverse L H

1 Forward H L

D16 Gm Range Select. This bit determines if VREF is divided by 5 or 10. D16 Divider 0 ÷10 1 ÷5 D17 Bridge 2 Mode. This bit determines slow or mixed decay for internal current-control operation. D17 Decay Mode

0 Mixed

D19 Test Mode. This bit is reserved for testing and should never be changed by the user. Default (low) operates the device in normal mode. Word 1 Bit Assignments Select Word 1 (D18 = 1) Bit Function D0 Bridge 2 blank time LSB D1 Bridge 2 blank time MSB D2 Bridge 2 off-time LSB D3 Bridge 2 off-time bit 1 D4 Bridge 2 off-time bit 2 D5 Bridge 2 off-time bit 3 D6 Bridge 2 off-time MSB D7 Bridge 2 fast-decay time bit LSB D8 Bridge 2 fast-decay time bit 1 D9 Bridge 2 fast-decay time bit 2 D10 Bridge 2 fast-decay time bit MSB D11 Bridge 2 sync. rect. control D12 Bridge 2 sync. rect. control D13 Bridge 2 external PWM mode D14 Bridge 2 enable D15 Bridge 2 phase D16 Bridge 2 reference range select D17 Bridge 2 internal PWM mode D18 Word select = 1 D19 Idle mode D0 - D17. Identical definitions as Word 0, with Word 1 selected. Data is written to Full Bridge 2. D19 Idle Mode. The device can be placed in a low-power “idle” mode by writing a “0” to D19. The outputs will be disabled, the charge pump will be turned off, and the device will draw a lower load supply currrent. The undervoltage monitor circuit will remain active. D19 should be programmed high for 1 ms before attempting to enable any output driver.

7www.allegromicro.com VREG. This internally generated supply voltage is used to operate the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The V REG terminal should be decoupled with a 0.22 µF capacitor to ground. Charge Pump. The charge pump is used to generate a supply voltage greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The CP voltage is inter- nally monitored and in the case of a fault condition, the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on CP or V REG, the outputs of the device are disabled until the fault condition is removed. At power up, or in the event of low V DD, the UVLO circuit disables the drivers and resets the data in the serial port to all zeros. Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H-bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (R S), the applied analog reference voltage (VREF), and serial data bit D16: At the trip point, the sense comparator resets the source-enable latch, turning off the source driver (except in the case of low- side only mode where the sink driver is turned off). The load inductance then causes the current to recirculate for the serial- port programmed fixed off-time period. The current path during recirculation is determined by the configuration of slow/ mixed-decay mode (D17) and the synchronous rectification control bits (D11 and D12). FUNCTIONAL DESCRIPTION (continued) Sleep Mode. The input terminal SLEEP is dedicated to putting the device into a minimum current draw mode. When asserted low, the serial port will be reset to all zeros and all circuits will be disabled. PWM Timer Function. The PWM timer is programmable via the serial port (bits D2 – D10) to provide fixed off-time PWM signals to the control circuitry. In mixed current-decay mode, the first portion of the off time operates in fast decay, until the fast-decay time count is reached (serial bits D7 – D10), fol- lowed by slow decay for the rest of the off-time period (bits D2 – D6). If the fast-decay time is set longer than the off-time, the device effectively operates in fast-decay mode. Bit D17 selects mixed or slow decay. Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. After a short crossover delay, the A3974 synchronous rectification feature will turn on the appropriate MOSFET (or pair of MOSFETs for the mixed decay portion of the off-time) during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will lower power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification can be configured in active mode, passive mode, low side only, or disabled via the serial port (bits D11 and D12). The active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. Passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by V REF/10RS (when D16 = 0) or VREF/5RS(when D16 = 1). Low side only mode will switch the low-side MOSFETs on during the off time to short out the current path through the MOSFET body diode. With this setting, the high-side MOSFETs will not synchronously rectify so four external diodes from output to supply are recommended. This mode is intended for use with high-power applications where it is desired to save the expense of two external diodes per bridge. In this mode, the sink-side MOSFETs are chopped during the PWM off time. In all other cases, the source-side MOSFETs are chopped in response to a PWM OFF command.

Worcester, Massachusetts 01615-0036 (508) 853-50008 Current Sensing. To minimize inaccuracies in sensing the ITRIP current level caused by ground-trace IR drops, the sense resistor should have an independent ground return to a ground terminal of the device. For low-value sense resistors, the IR drops in the PCB sense traces of the resistor can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in R S due to their contact resistance. The maximum value of RS is given as RS = 0.5/ITRIPMAX. Braking. The braking function is implemented by driving the device in slow-decay mode via serial port bit D13, enabling synchronous rectification via bits D11 and D12, and applying an enable chop command with the combination of D14 and the ENABLE input terminal. Because it is possible to drive current in both directions through the DMOS switches, this configura- tion effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by V BEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst- case braking situations of high speed and high inertial loads. DATA CLOCK Dwg. WP-038 STROBE A F B GC D E D19 D0 D18 APPLICATIONS INFORMATION Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165°C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The ground side of R S should have an individual path to a ground terminal of the device. This path should be as short as is possible physically and should not have any other components con- nected to it. The load supply terminal, V BB, should be decoupled with an electrolytic capacitor (>47 µF is recom- mended) placed as close to the device as is possible. Serial Port Write Timing Operation. Data is clocked into shift register on the rising edge of CLOCK signal. Normally, STROBE will be held high, and only will be brought low to initiate a write cycle. Refer to diagram below and specification table for timing requirements.

9www.allegromicro.com Terminal List Terminal Name Terminal Description Terminal Number GND Power and logic ground terminals 1, 2 SENSE

1 Sense resistor terminal for bridge 1 3

NCNo (internal) connection 4, 5 OUT 1A DMOS H-bridge 1 – output A 6 NCNo (internal) connection 7 STROBE Logic input for serial Interface 8 CLOCK Logic input for serial Interface 9 DATA Logic input for serial Interface 10 GND Power and logic ground terminals 11, 12, 13 REF

1 Gm reference input voltage – bridge 1 14

REF2 Gm reference input voltage – bridge 2 15 LOGIC SUPPLY V DD, the low voltage (typically 5 V) supply 16 NCNo (internal) connection 17 OUT 2A DMOS H-bridge 2 – output A 18 NCNo (internal) connection 19, 20 SENSE

2 Sense resistor pin for bridge 2 21

GND Power and logic ground terminals 22, 23, 24 LOAD SUPPLY

2 VBB2, the high current, 20 V to 50 V,

ENABLE2 Logic input for bridge 2 – enable control 26 NCNo (internal) connection 27 OUT 2B DMOS H-bridge 2 – output B 28 NCNo (internal) connection 29 V REG Regulator decoupling capacitor (typ. 0.22 µF) 30 SLEEP Logic input for SLEEP mode 31 OSCLogic-level oscillator (square wave) input 32 GND Power and logic ground terminals 33, 34, 35 CP Reservoir capacitor (typically 0.22 µF) 36 CP1 & CP2 The charge pump capacitor (typically 0.22 µF) 37 & 38 NCNo (internal) connection 39 OUT 1B DMOS H-bridge 1 – output B 40 NCNo (internal) connection 41 ENABLE

1 Logic input for bridge 1 – enable control 42

LOAD SUPPLY1 VBB1, the high current, 20 V to 50 V, supply for bridge 1 43 GND Power and logic ground terminals 44

Worcester, Massachusetts 01615-0036 (508) 853-500010 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dimensions in Inches (controlling dimensions) NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Available in standard sticks/tubes of 28 devices or add “TR” to part number for tape and reel.

11www.allegromicro.com Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 16.662 16.510 8.10 7.398.10 7.39 Dimensions in Millimeters (for reference only) NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Available in standard sticks/tubes of 28 devices or add “TR ” to part number for tape and reel.

Worcester, Massachusetts 01615-0036 (508) 853-500012 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.