3971

3971 ALLEGRO

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

29319.32 3971 DUAL DMOS FULL-BRIDGE DRIVER Designed to interface between external PWM control logic and inductive loads such as relays, solenoids, dc motors, or stepper motors, each full bridge can operate with output currents to ±2.5 A and operating voltages to 50 V. Low r DS(on) DMOS output drivers provide low power dissipation during PWM operation. Internal charge pump circuitry is used to create a boosted voltage to fully enhance the high-side DMOS switches. Three TTL-compatible logic-input terminals per bridge allow flex- ibility in configuring PWM control. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power -up sequencing is not required. The A3971SLB is supplied in a 24-lead plastic SOIC with a copper batwing tab. The power tab is at ground potential and needs no electri- cal isolation.

FEATURES

I ±2.5 A Load Current Capability per Bridge I Parallel Outputs for 5 A Load-Current Capability I Low rDS(on) Outputs Typically 325 mΩ source, 175 mΩ sink I Synchronous Rectification via Control Logic I Internal Undervoltage Monitor I Crossover-Current Protection I Source Connections for External Current Sensing I Thermal Shutdown Circuitry ADVANCE INFORMATION (Subject to change without notice) May 2, 2000 ABSOLUTE MAXIMUM RATINGS at TA = +25°C Output Current, IOUT Logic Supply Voltage, Logic Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Output duty cycle, ambient temperature, and heat sinking may limit current rating. Under any set of conditions, do not exceed the specified current rating or a junction tempera- ture of 150 °C. Always order by complete part number: A3971SLB . LOGIC LOGIC CHARGE PUMP GROUND GROUND PWM S20 OUT2A LOAD SUPPLY2 SENSE2 OUT2B S21 VCP CP2 VDD Dwg. PP-069-2 GROUND GROUND NO CONNECTION LOGIC GROUND S10 OUT1A OUT1B S11 PWM1 CP1 SENSE1 LOAD SUPPLY1 NC LOGIC SUPPLY VBB2VBB1

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM Copyright © 2000, Allegro MicroSystems, Inc. BRIDGE 1 CONTROL LOGIC VOLTAGE REFERENCE UVLO & THERMAL SHUTDOWN OUT2A SENSE2 GATE DRIVE CHARGE PUMP CP1CP2 VCP VBB2 S20 S21 OUT2B 0.22 µF/100 V VDD DMOS H-BRIDGE 0.22 µF 50 V OUT1A VBB1 OUT1B DMOS H-BRIDGE SENSE1 VCP GROUND S10 S11 PWM1 PWM2 VREF LOW SIDE SUPPLY BRIDGE 2 CONTROL LOGIC LGND (OPTIONAL) (OPTIONAL) LOAD SUPPLY RS, CS RS, CS LOGIC SUPPLY Dwg. FP-050 1213 6 7 18 19

www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Load Supply Voltage Range V BB Operating 10 — 50 V Logic Supply Voltage Range V DD Operating 4.5 5.0 5.5 V Load Supply Current I BB Operating, each supply, no load — — 3.0 mA Logic Supply Current I DD Operating — — 5.0 mA Output Drivers Output Leakage Current I DSS VOUT = VBB — <1.0 20 µA VOUT = 0 V — <-1.0 -20 mA Output ON Resistance r DS(on) High-side switch, IOUT = -2.5 A — 325 375 m Ω Low-side switch, IOUT = 2.5 A — 175 200 m Ω Body Diode Forward Voltage V F Source diode, IF = 2.5 A — 1.2 — V Sink diode, IF = 2.5 A — 1.0 — V High-Side Gate Voltage V CP C = 0.22 µF, reference VBB 6.0 6.5 7.0 V Control Logic Logic Input Voltage V IN(0) ——0 . 8V VIN(1) 2.0 — — V Logic Input Current I IN(0) VIN = 0 V — <1.0 -5.0 µA IIN(1) VIN = 5.0 V — 20 50 µA Propagation Delay Time t PD 50% to 90%: PWM change to source off — 50 — ns PWM change to sink off — 60 — ns PWM change to source on — 565 — ns PWM change to sink on — 665 — ns Disable to source on — 150 — ns Disable to sink on — 250 — ns Thermal Shutdown Temperature T J — 165 — °C Thermal Shutdown Hysteresis ∆TJ —1 5— °C UVLO Threshold V UVLO Increasing VDD 3.9 4.15 4.4 V UVLO Hysteresis ∆VUVLO —0 . 1 5— V NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.

Worcester, Massachusetts 01615-0036 (508) 853-5000 Logic Truth Table PWMx Sx0 Sx1 OUTxA OUTxB Function X 0 0 Z Z Disable 001LH F o r w a r d 0 1 0 H L Reverse 011LLS ynchronous 101LLR e c tification/ 111LLS l o w D ecay 110LL C h o p Terminal List Terminal Name Description

1 NC No (Internal) connection

2 LGND Logic ground

10 Control input, bridge 1

4 OUT 1A Output A, bridge 1

5V BB1 Load supply voltage, bridge 1 6, 7 GND Ground

8 SENSE 1 Sense resistor, bridge 1

9 OUT 1B Output B, bridge 1

10 S 11 Control input, bridge 1

11 PWM 1 Control input, bridge 1

12 CP1 Charge-pump capacitor

13 CP2 Charge-pump capacitor

15 S 21 Control input, bridge 2

16 OUT 2B Output B, bridge 2

17 SENSE 2 Sense resistor, bridge 2

18, 19 GND Ground

20 V BB2 Load supply voltage, bridge 2

21 OUT 2A Output A, bridge 2

22 S 20 Control input, bridge 2

23 PWM 2 Control input, bridge 2

24 V DD Logic supply voltage

www.allegromicro.com Charge Pump. The DMOS output stage requires a charge pump to bring the high-side gate-source voltage approximately 8 V above the V BB supply. Two external components are required, a pumping capacitor connected between CP1 and CP2 and a reservoir capacitor connected between V BB and VCP. Ceramic 0.22 µF capacitors are recommended. Control Logic. Each bridge is controlled by three TTL- compatible inputs. The inputs are resistively pulled to ground (via 250 kΩ). A crossover-delay circuit protects the outputs from a shoot-thru condition when going from a forward or reverse on state to synchronous rectification/ slow decay chop (both sink drivers on). If the logic is in the DISABLE state and changes to an on state the 415 ns crossover delay does not occur. Protection Circuitry. In the event of a fault due to excessive junction temperature, or low voltage on V CP or VDD, the outputs of the device are disabled until the fault condition is removed. Current Sensing. If external current-sensing circuitry is used, the sense resistor should have an independent ground return to the ground terminal of the device. Due to current transients during switching, a 0.1 µF capacitor should be connected from the sense terminal to the batwing tab connection of the package. This capacitor reduces voltage swings at the terminal due to the fast di/dt, which in turn ensures that the sink driver gate-source voltage stays within the safe operating area. Allegro MicroSystems recommends a value of R S given by: RS = 0.5/ITRIP max. Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shut- down has a hysteresis of approximately 15°C. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal perfor- mance, the driver should be soldered directly onto the board. If external current sensing is used, the ground side of R S should have an individual path to the ground terminal(s) of the device. This path should be as short as is possible physically and should not have any other components connected to it. The load supply terminal should be decoupled with an electrolytic capacitor ( >47 µF is recommended) placed as close to the device as is possible. Parallel Operation. For high-power applications, the two DMOS full bridges in the A3971 may be connected in parallel as shown below. The current will be shared equally in each full bridge due to the positive temperature coefficient of the DMOS rDS(on). Functional Description Dwg. EP-069 PWM CONTROL +5 V 15–50 V 47 µF 0.22 µF 0.22 µF 47 µF 15–50 V LOGIC LOGIC VDD1 NC CHARGE PUMP VBB2VBB1

Worcester, Massachusetts 01615-0036 (508) 853-5000 Dimensions in Inches (for reference only) 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-24A in 0.050 BSC 24 13 0.2992 0.2914 0.419 0.394 0.6141 0.59850.0926 0.1043 NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.

www.allegromicro.com Dimensions in Millimeters (controlling dimensions) 0° TO 8° 2 30.51 0.33 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-24A mm 1.27 BSC 7.60 7.40 10.65 10.00 15.60 15.202.65 2.35 NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.

Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.