3966

3966_03 ALLEGRO

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Data Sheet29319.25G 3966 DUAL FULL-BRIDGE PWM MOTOR DRIVER The A3966SA and A3966SLB are designed to drive both windings of a two- phase bipolar stepper motor. Each device includes two H-bridges capable of continuous output currents of ±650 mA and operating voltages to 30 V. Motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (PWM), current-control circuitry. The peak load current limit is set by the user’s selection of a reference voltage and current-sensing resistors. Except for package style and pinout, the two devices are identical. The fixed-frequency pulse duration is set by a user-selected external RC timing network. The capacitor in the RC timing network also determines a user- selectable blanking window that prevents false triggering of the PWM current- control circuitry during switching transitions. To reduce on-chip power dissipation, the H-bridge power outputs have been optimized for low saturation voltages. The sink drivers feature the Allegro ® patented Satlington® output structure. The Satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a Darlington. For each bridge, a PHASE input controls load-current polarity by selecting the appropriate source and sink driver pair. For each bridge, an ENABLE input, when held high, disables the output drivers. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, ground-clamp and flyback diodes, and crossover-current protection. The A3966SA is supplied in a 16-pin dual in-line plastic package. The A3966SLB is supplied in a 16-lead plastic SOIC with copper heat sink tabs. The power tab is at ground potential and needs no electrical isolation. The A3966SLB is also available in a lead (Pb) free version, with 100% matte tin leadframe plating. A3966SLB (SOIC)

FEATURES

■ ±650 mA Continuous Output Current ■ 30 V Output Voltage Rating ■ Internal Fixed-Frequency PWM Current Control ■ Satlington Sink Drivers ■ User-Selectable Blanking Window ■ Internal Ground-Clamp & Flyback Diodes ■ Internal Thermal-Shutdown Circuitry ■ Crossover-Current Protection and UVLO Protection ABSOLUTE MAXIMUM RATINGS Package Power Dissipation (T A = 25°C), PD Operating Temperature Range, Junction Temperature, Storage Temperature Range, Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. * Per SEMI G42-88 Specification, Thermal Test Board Standardization for Measuring Junction-to-Ambient Thermal Resistance of Semiconductor Packages . OUT1B GROUND Dwg. PP-066-1 GROUND OUT1A PHASE 1 OUT2A SENSE1 ENABLE1 LOAD SUPPLY REFERENCE PHASE 2 ENABLE 2 SENSE 2 OUT 2B LOGIC SUPPLY RC LOGICLOGIC 3 14 71 0 89 RC V REF VBB VCC VBB Part Number Pb-free* Package Packing A3966SLB-T Y es 16-Lead SOI C 47 per tube A3966SLBTR-T Y es 16-Lead SOI C 1000 per ree l *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007. These variants include: A3966SA, A3966SLB, and A3966SLBTR.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-50002 Copyright © 1998, 2003 Allegro MicroSystems, Inc. FUNCTIONAL BLOCK DIAGRAM 8 9 OUT GROUND Dwg. PP-066-2 OUT 1A PHASE 1 OUT 2A SENSE 1 ENABLE 1 LOAD SUPPLY REFERENCE PHASE 2 ENABLE 2SENSE 2 OUT 2B LOGIC SUPPLY RC RC V REF VCC V BB GROUND LOGICLOGIC A3966SA (DIP) TRUTH TABLE PHASE ENABLE OUT A OUTB XH O f fO f f HL H L LL L H X = Irrelevant R 2S R 1S REFERENCE V CC LOGIC SUPPLY PHASE 1 LOAD SUPPLY OUT 1A OUT 1B V BB RC R T C T Dwg. FP-036-6 SENSE UVLO & TSD BLANKING GATE Q R S PWM LATCH + CURRENT-SENSE COMPARATOR ENABLE 1 OSC PHASE 2 GROUND SENSE UVLO & TSD BLANKING GATE Q R S PWM LATCH+ CURRENT-SENSE COMPARATOR ENABLE 2 CONTROL LOGICSOURCE ENABLE OUT 2A OUT 2B 21 2 2 2 1 1 CONTROL LOGIC 1 SOURCE ENABLE 1

www.allegromicro.com 3 Load Supply Voltage Range VBB Operating, IOUT = ±650 mA, L = 3 mH VCC — 30 V Output Leakage Current ICEX VOUT 050.1<—V 03 = µA VOUT 05-0.1-<—V 0 = µA Output Saturation Voltage VCE(SAT) Source Driver, IOUT = -400 mA — 1.7 2.0 V Source Driver, IOUT = -650 mA — 1.8 2.1 V Sink Driver, IOUT = +400 mA, VS = 0.5 V — 0.3 0.5 V Sink Driver, IOUT = +650 mA, VS = 0.5 V — 0.7 1.3 V Clamp Diode Forward Voltage VF IF V4.11.1—Am 004 = IF V6.14.1—Am 056 = Motor Supply Current IBB(ON) VENABLE1 = VENABLE2 = 0.8 V — 3.0 5.0 mA (No Load) IBB(OFF) VENABLE1 = VENABLE2 = 2.4 V — <1.0 200 µA ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise) Limits stinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC Output Drivers Logic Supply Voltage Range VCC V05.5—57.4gnitarepO Logic Input Voltage VIN(1) 2.4 — — V VIN(0) — — 0.8 V Logic Input Current IIN(1) VIN 020.1<—V 4.2 = µA IIN(0) VIN 002-02-<—V 8.0 = µA Reference Input Volt. Range VREF V0.2–1.0gnitarepO Reference Input Current IREF -2.5 0 1.0 µA Reference Divider Ratio VREF/VTRIP 3.8 4.0 4.2 — Current-Sense Comparator VIO VREF Vm0.600.6-V 0 = Input Offset Voltage Current-Sense Comparator VS V0.1—3.0-gnitarepO Input Voltage Range Sense-Current Offset ISO IS – IOUT, 50 mA ≤ IOUT ≤ 650 mA 12 18 24 mA Control Logic NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.

Worcester, Massachusetts 01615-0036 (508) 853-50004 PWM RC Frequency fosc CT = 680 pF, RT = 56 kΩ 22.9 25.4 27.9 kHz PWM Propagation Delay Time tPWM Comparator Trip to Source OFF — 1.0 1.4 µs Cycle Reset to Source ON — 0.8 1.2 µs Cross-Over Dead Time tcodt 1 kΩ 0.38.12.0V 52 ot daoL µs Propagation Delay Times tpd IOUT = ±650 mA, 50% to 90%: ENABLE ON to Source ON — 100 — ns ENABLE OFF to Source OFF — 500 — ns ENABLE ON to Sink ON — 200 — ns ENABLE OFF to Sink OFF — 200 — ns PHASE Change to Sink ON — 2200 — ns PHASE Change to Sink OFF — 200 — ns PHASE Change to Source ON — 2200 — ns PHASE Change to Source OFF — 200 — ns Thermal Shutdown Temp. TJ — 165 — °C Thermal Shutdown Hysteresis ∆TJ — 15 — °C UVLO Enable Threshold VT(UVLO)+ Increasing VCC — 4.1 4.6 V UVLO Hysteresis VT(UVLO)hys 0.1 0.6 — V Logic Supply Current ICC(ON) VENABLE 1 = VENABLE 2 = 0.8 V — — 50 mA ICC(OFF) VENABLE 1 = VENABLE 2 = 2.4 V — — 9.0 mA Limits stinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise) (cont.) Control Logic (continued) NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.

www.allegromicro.com 5 Internal PWM Current Control. The A3966SA and A3966SLB dual H-bridges are designed to drive both windings of a bipolar stepper motor. Load current can be controlled in each motor winding by an internal fixed- frequency PWM control circuit. The current-control circuitry works as follows: when the outputs of the H- bridge are turned on, current increases in the motor wind- ing. The load current is sensed by the current-control comparator via an external sense resistor (R S). Load current continues to increase until it reaches the predeter- mined value, set by the selection of external current- sensing resistors and reference input voltage (V REF) according to the equation: ITRIP = IOUT + ISO = VREF/(4 RS) where ISO is the sense-current error (typically 18 mA) due to the base-drive current of the sink driver transistor. At the trip point, the comparator resets the source- enable latch, turning off the source driver of that H-bridge. The source turn off of one H-bridge is independent of the other H-bridge. Load inductance causes the current to recirculate through the sink driver and ground-clamp diode. The current decreases until the internal clock oscillator sets the source-enable latches of both H-bridges, turning on the source drivers of both bridges. Load current increases again, and the cycle is repeated. FUNCTIONAL DESCRIPTION The frequency of the internal clock oscillator is set by the external timing components RTCT. The frequency can be approximately calculated as: fosc = 1/(RT CT + tblank) where tblank is defined below. The range of recommended values for RT and CT are 20 kΩ to 100 kΩ and 470 pF to 1000 pF respectively. Nominal values of 56 kΩ and 680 pF result in a clock frequency of 25 kHz. Current-Sense Comparator Blanking. When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. The blanking time is set by the timing component C T according to the equa- tion: tblank = 1900 CT (µs). A nominal CT value of 680 pF will give a blanking time of 1.3 µs. The current-control comparator is also blanked when the H-bridge outputs are switched by the PHASE or ENABLE inputs. This internally generated blank time is approximately 1 µs. Dwg. WM-003-2 VPHASE IOUT td I TRIP tblank INTERNAL OSCILLATOR BRIDGE ON SOURCE OFF BRIDGE ON R CT T ALL OFF Enlargement A See Enlargement A Dwg. EP-006-16 RS BBV BRIDGE ON SOURCE OFF ALL OFF

Worcester, Massachusetts 01615-0036 (508) 853-50006 Load Current Regulation. Due to internal logic and switching delays (td), the actual load current peak will be slightly higher than the ITRIP value. These delays, plus the blanking time, limit the minimum value the current control circuitry can regulate. To produce zero current in a winding, the ENABLE terminal should be held high, turning off all output drivers for that H-bridge. Logic Inputs. A logic high on the PHASE input results in current flowing from OUTA to OUTB of that H-bridge. A logic low on the PHASE input results in current flowing from OUTB to OUTA. An internally generated dead time (tcodt) of approximately 1 µs prevents cross-over current spikes that can occur when switching the PHASE input. A logic high on the ENABLE input turns off all four output drivers of that H-bridge. This results in a fast current decay through the internal ground clamp and flyback diodes. A logic low on the ENABLE input turns on the selected source and sink driver of that H-bridge. The ENABLE inputs can be pulse-width modulated for applications that require a fast current-decay PWM. If external current-sensing circuitry is used, the internal current-control logic can be disabled by connecting the R TCT terminal to ground. The REFERENCE input voltage is typically set with a resistor divider from VCC. This reference voltage is internally divided down by 4 to set up the current-com- parator trip-voltage threshold. The reference input voltage range is 0 to 2 V. Output Drivers. To minimize on-chip power dissipation, the sink drivers incorporate a Satlington structure. The Satlington output combines the low V CE(sat) features of a saturated transistor and the high peak-current capability of a Darlington (connected) transistor. A graph showing typical output saturation voltages as a function of output current is on the next page. Miscellaneous Information. Thermal protection circuitry turns off all output drivers should the junction temperature reach +165 °C (typical). This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Normal operation is resumed when the junction temperature has decreased about 15°C. The A3966 current control employs a fixed-fre- quency, variable duty cycle PWM technique. As a result, the current-control regulation may become unstable if the duty cycle exceeds 50%. To minimize current-sensing inaccuracies caused by ground trace I R drops, each current-sensing resistor should have a separate return to the ground terminal of the device. For low-value sense resistors, the I x R drops in the printed-wiring board can be significant and should be taken into account. The use of sockets should be avoided as their contact resistance can cause variations in the effective value of R The LOAD SUPPLY terminal, VBB, should be decoupled with an electrolytic capacitor (47 µF recom- mended) placed as close to the device as physically practical. To minimize the effect of system ground I x R drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. The frequency of the clock oscillator will determine the amount of ripple current. A lower frequency will result in higher current ripple, but reduced heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. A higher frequency will reduce ripple current, but will increase switching losses and EMI. FUNCTIONAL DESCRIPTION (continued)

www.allegromicro.com 7 TYPICAL APPLICATION (A3966SLB) Typical output saturation voltages showing Satlington sink-driver operation. The products described here are manufactured under one or more trademark of Allegro MicroSystems, Inc. (Allegro), and Satlington devices are manufactured under U. S. Patent No. 5,684,427. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Dwg. EP-047-4A PHASE 2 ENABLE2 47 μF +24 V 56 kΩ 680 pF PHASE1 ENABLE1 +5 V 39 kΩ10 kΩ 0.5 Ω +5 V 0.5 Ω LOGICLOGIC 3 14 017 98 RC VREF VBB VCC VBB 200 Dwg. GP-064-1A 007004300 OUTPUT CURRENT IN MILLIAMPERES 2.0 OUTPUT SATURATION VOLTAGE IN VOLTS 1.0 0.5 1.5 2.5 500 600 TA = +25°C SOURCE DRIVER SINK DRIVER

Worcester, Massachusetts 01615-0036 (508) 853-50008 A3966SA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 25 devices. 0.014 0.008 0.300 BSC Dwg. MA-001-16A in 0.430 MAX 1 8 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.775 0.735 0.355 0.204 7.62 BSC Dwg. MA-001-16A mm 10.92 MAX 1 8 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 19.68 18.67

www.allegromicro.com 9 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.3940.020 0.0130.0926 0.1043 0.0040 MIN. 0.0125 0.0091 0.050 0.016 0° TO 8° Dwg. MA-008-16A in 0.050 BSC 16 9 A3966SLB Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) N OTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Webbed lead frame. Leads 4 and 13 are internally one piece. 4. Supplied in standard sticks/tubes of 47 devices or add “TR” to part number for tape and reel. 916 1 2 3 7.60 7.40 10.50 10.10 10.65 10.000.51 0.332.65 2.35 0.10 MIN. 0.32 0.23 1.27 0.40 0° TO 8° Dwg. MA-008-16A mm 1.27 BSC