3955

3955 ALLEGRO

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29319.41 Note the A3955SB (DIP) and the A3955SLB (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS Output Current, IOUT Logic/Reference Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150˚C. † Fault conditions that produce excessive junction temperature will activate the device’s thermal shutdown circuitry. These conditions can be tolerated but should be avoided. 8 9 GROUND GROUND LOGIC SUPPLY PHASE GROUND GROUND RC SENSE D Dwg. PP-056-2 REF LOAD SUPPLY VCC OUT B OUT A VBB LOGIC PFD D 0 D 2 The A3955SB and A3955SLB are designed for driving one winding of a bipolar stepper motor in a microstepping mode. The outputs are rated for continuous output currents to ±1.5 A and operating voltages to 50 V. Internal pulse-width modulated (PWM) current control com- bined with an internal three-bit nonlinear digital-to-analog converter allows the motor current to be controlled in full-, half-, quarter-, or eighth-step (microstepping) modes. Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides for increased step resolution, and reduces torque variations and resonance problems at low speed. Internal circuitry determines whether the PWM current-control circuitry operates in a slow (recirculating) current-decay mode, fast (regenerative) current-decay mode, or in a mixed current-decay mode in which the off time is divided into a period of fast current decay with the remainder of the fixed off time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, digitally selected output current ratio; and slow, fast, or mixed current-decay modes provides users with a broad, variable range of motor control. Internal circuit protection includes thermal shutdown with hyster- esis, transient-suppression diodes, and crossover current protection. Special power-up sequencing is not required. The A3955S— is supplied in a choice of two power packages; a 16-pin dual-in-line plastic package with copper heat-sink tabs (suffix ‘B’), and a 16-lead plastic SOIC with copper heat-sink tabs (suffix ‘LB’). For both package styles, the power tab is at ground potential and needs no electrical isolation.

FEATURES

n ±1.5 A Continuous Output Current n 50 V Output Voltage Rating n Internal PWM Current Control n 3-Bit Non-Linear DAC n Fast, Mixed Fast/Slow, and Slow Current-Decay Modes n Internal Transient-Suppression Diodes n Internal Thermal-Shutdown Circuitry n Crossover-Current and UVLO Protection FULL-BRIDGE PWM MICROSTEPPING MOTOR DRIVER Part Number Package A3955SB 16-Pin DIP A3955SLB 16-Lead SOIC Always order by complete part number: 3955

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM REF D D D 2 8 14 D/A2 VCC LOGIC SUPPLY PHASE LOAD SUPPLY OUT A OUT B 10 15 PFD 1 + VBB RC GROUND R S Dwg. FP-042 SENSE VCC BLANKING UVLO & TSD Q R S PWM LATCH + – V TH R T C T MIXED-DECAY COMPARATOR + ‚3 DISABLE CURRENT-SENSE COMPARATOR BLANKING GATE W Copyright © 1997 Allegro MicroSystems, Inc. Table 1 Ñ PHASE Truth Table PHASE OUT A OUT B HH L LL H Table 2 Ñ PFD Truth Table V PFD Description ≥3.5 V Slow Current-Decay Mode 1.1 V to 3.1 V Mixed Current-Decay Mode ≤0.8 V Fast Current-Decay Mode

ELECTRICAL CHARACTERISTICS at TA = 25ßC, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted.) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Load Supply Voltage Range V BB Operating, IOUT = ±1.5 A, L = 3 mH V CC —5 0 V Output Leakage Current I CEX VOUT = VBB — <1.0 50 µA VOUT = 0 V — <-1.0 -50 µA Output Saturation Voltage V CE(SAT) VS = 1.0 V: (Forward or Reverse Mode) Source Driver, IOUT = -0.85 A — 1.0 1.2 V Source Driver, IOUT = -1.5 A — 1.3 1.5 V Sink Driver, IOUT = 0.85 A — 0.5 0.6 V Sink Driver, IOUT = 1.5 A — 1.3 1.5 V Sense Current Offset I SO IS - IOUT , IOUT = 850 mA, 20 33 40 mA VS = 0 V, VCC = 5 V Clamp Diode Forward Voltage V F IF = 0.85 A — 1.2 1.4 V (Sink or Source) IF = 1.5 A — 1.4 1.7 V Motor Supply Current I BB(ON) — 2.0 4.0 mA (No Load) IBB(OFF) D 0 = D1 = D2 = 0.8 V — 1.0 50 µA Continued next page… Power Outputs 50 75 100 125 150 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTSTEMPERATURE IN °C Dwg. GP-049-2A R = 6.0°C/WqJT SUFFIX 'B', R = 43°C/WqJA SUFFIX 'LB', R = 63°C/WqJA Table 3 Ñ DAC Truth Table DAC DATA Current D 2 D 1 D 0 Ratio, % V REF /VS H H H 100 3.00 H H L 92.4 3.25 H L H 83.1 3.61 H L L 70.7 4.24 L H H 55.5 5.41 L H L 38.2 7.85 L L H 19.5 15.38 L L L All Outputs Disabled where VS = ITRIP•RS. See Applications section.

Worcester, Massachusetts 01615-0036 (508) 853-5000 * The total error for the VREF /VS function is the sum of the D/A error and the current-sense comparator input offset voltage. Logic Supply Voltage Range V CC Operating 4.5 5.0 5.5 V Reference Voltage Range V REF Operating 0.5 — 2.5 V UVLO Enable Threshold V CC = 0 Õ 5 V 3.35 3.70 4.05 V UVLO Hysteresis 0.30 0.45 0.60 V Logic Supply Current I CC(ON) —4 25 0 m A ICC(OFF) D 0 = D1 = D2 = 0.8 V — 12 16 mA Logic Input Voltage V IN(1) 2.0 — — V VIN(0) — — 0.8 V Logic Input Current I IN(1) VIN = 2.0 V — <1.0 20 µA IIN(0) VIN = 0.8 V — <-2.0 -200 µA Mixed-Decay Comparator V PFD Slow Current-Decay Mode 3.5 — — V Trip Points Mixed Current-Decay Mode 1.1 — 3.1 V Fast Current-Decay Mode — — 0.8 V Mixed-Decay Comparator V IO(PFD) —0 ±20 mV Input Offset Voltage Mixed-Decay Comparator ΔVIO(PFD) 5.0 25 55 mV Hysteresis Reference Input Current I REF VREF = 0 V to 2.5 V — — ±5.0 µA Reference Divider Ratio V REF /VS at trip, D0 = D1 = D2 = 2 V — 3.0 — — Digital-to-Analog Converter — 1.0 V < V REF ≤ 2.5 V — — ±3.0 % Accuracy* 0.5 V < VREF ≤ 1.0 V — — ±4.0 % Current-Sense Comparator V IO(S) VREF = 0 V — — ±5.0 mV Input Offset Voltage* Step Reference SRCR D 0 = D1 = D2 = 0.8 V — 0 — % Current Ratio D 0 = 2 V, D1 = D2 = 0.8 V — 19.5 — % D 0 = 0.8 V, D1 = 2 V, D2 = 0.8 V — 38.2 — % D 0 = D1 = 2 V, D2 = 0.8 V — 55.5 — % D 0 = D1 = 0.8 V, D2 = 2 V — 70.7 — % D 0 = 2 V, D1 = 0.8 V, D2 = 2 V — 83.1 — % D 0 = 0.8 V, D1 = D2 = 2 V — 92.4 — % D 0 = D1 = D2 = 2 V — 100 — % ELECTRICAL CHARACTERISTICS at TA = 25ßC, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted. ) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Control Circuitry Continued next page…

ELECTRICAL CHARACTERISTICS at TA = 25ßC, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V (unless otherwise noted.) Control Circuitry (contÕd) Thermal Shutdown Temp. T J — 165 — °C Thermal Shutdown Hysteresis ΔTJ —1 5— °C AC Timing PWM RC Fixed Off-time t OFF RC C T = 470 pF, RT= 43 kΩ 18.2 20.2 22.3 µs PWM Turn-Off Time t PWM(OFF) Current-Sense Comparator Trip — 1.0 1.5 µs to Source OFF, IOUT = 100 mA Current-Sense Comparator Trip — 1.4 2.5 µs to Source OFF, IOUT = 1.5 A PWM Turn-On Time t PWM(ON) IRC Charge ON to Source ON, — 0.4 0.7 µs IOUT = 100 mA IRC Charge ON to Source ON, — 0.55 0.85 µs IOUT = 1.5 A PWM Minimum On Time t ON(min) VCC = 5.0 V, RT ≥ 43 kΩ , CT = 470 pF 1.0 1.6 2.2 µs IOUT = 100 mA Crossover Dead Time t CODT 1 kΩ Load to 25 V 0.3 1.5 3.0 µs Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units

Worcester, Massachusetts 01615-0036 (508) 853-5000 Terminal Functions Terminal Name Description 1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode.

2 REF (V REF ) The voltage at this input (along with the value of RS and the states of DAC inputs

D 0, D1, and D2) set the peak output current.

3 RC The parallel combination of external resistor R T and capacitor CT set the off time for the

PWM current regulator. CT also sets the blanking time. 4-5 GROUND Return for the logic supply (V CC ) and load supply (VBB ); the reference for all voltage measurements. 6 LOGIC SUPPLY (V CC ) Supply voltage for the logic circuitry. Typically = 5 V. 7 PHASE The PHASE input determines the direction of current in the load. 8D 2 (DATA 2) One-of-three (MSB) control bits for the internal digital-to-analog converter. 9D 1 (DATA 1) One-of-three control bits for the internal digital-to-analog converter. 10 OUT A One-of-two output load connections. 11 SENSE Connection to the sink-transistor emitters. Sense resistor RS is connected between this point and ground. 12-13 GROUND Return for the logic supply (V CC ) and load supply (VBB ); the reference for all voltage measurements. 14 D 0 (DATA 0) One-of-three (LSB) control bits for the internal digital-to-analog converter. 15 OUT B One-of-two output load connections. 16 LOAD SUPPLY (V BB ) Supply voltage for the load.

Two A3955S— full-bridge PWM microstepping motor drivers are needed to drive the windings of a bipolar stepper motor. Internal pulse-width modulated (PWM) control circuitry regulates each motor winding’s current. The peak motor current is set by the value of an external current-sense resistor (R S ), a reference voltage (VREF ), and the digital-to-analog converter (DAC) data inputs (D0, D 1, and D2). To improve motor performance, especially when using sinusoidal current profiles necessary for microstepping, the A3955S— has three distinct current-decay modes: slow decay, fast decay, and mixed decay. PHASE Input. The PHASE input controls the direction of current flow in the load (table 1). An internally generated dead time of approximately 1 µs prevents crossover currents that could occur when switching the PHASE input. DAC Data Inputs (D 0, D1, D2). A non-linear DAC is used to digitally control the output current. The output of the DAC is used to set the trip point of the current-sense comparator. Table 3 shows DAC output voltages for each input condition. When D 0, D1, and D2 are all logic low, all of the power output transistors are turned off. Internal PWM Current Control. Each motor driver contains an internal fixed off-time PWM current-control circuit that limits the load current to a desired value (I TRIP). Initially, a diagonal pair of source and sink transistors are enabled and current flows through the motor winding and R S (figure 1). When the voltage across the sense resistor equals the DAC output voltage the current-sense com- parator resets the PWM latch, which turns off the source drivers (slow-decay mode) or the sink and source drivers (fast- or mixed-decay mode). With the DATA input lines tied to V CC , the maximum value of current limiting is set by the selection of RS and VREF with a transconductance function approximated by: ITRIP ≈ VREF /3RS . The actual peak load current (IPEAK ) will be slightly higher than ITRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected external resistor-capacitor combination TC T). At the end of the fixed off time, the driver(s) are re-enabled, allowing the load current to increase to ITRIP again, maintaining an average load current. The DAC data input lines are used to provide up to eight levels of output current. The internal 3-bit digital-to- analog converter reduces the reference input to the current-sense comparator in precise steps (the step reference current ratio or SRCR) to provide half-step, quarter-step, or “microstepping” load-current levels. I TRIP ≈ SRCR x VREF /3RS Slow Current-Decay Mode. When V PFD ≥ 3.5 V, the device is in slow current-decay mode (the source drivers are disabled when the load current reaches I TRIP). During the fixed off time, the load inductance causes the current to recirculate through the motor winding, sink driver, ground clamp diode, and sense resistor (see figure 1). Slow-decay mode produces low ripple current for a given fixed off time (see figure 2). Low ripple current is desir- able because the average current in the motor winding is more nearly equal to the desired reference value, result- ing in increased motor performance in microstepping applications. For a given level of ripple current, slow decay affords the lowest PWM frequency, which reduces heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. Slow decay also has the advantage that the PWM load current regulation can follow a more rapidly increasing reference before the PWM frequency drops into the audible range. For these reasons slow-decay mode is typically used as long as good current regulation can be maintained. Figure 1 Ñ Load-Current Paths Dwg. EP-006-15 R S BBV DRIVE CURRENT RECIRCULATION (SLOW-DECAY MODE) RECIRCULATION (FAST-DECAY MODE)

Worcester, Massachusetts 01615-0036 (508) 853-5000 A Ñ Slow-Decay B Ñ Fast-Decay C Ñ Mixed-Decay Figure 3 Ñ Sinusoidal Drive Currents Under some circumstances slow-decay mode PWM can fail to maintain good current regulation: 1) The load current will fail to regulate in slow-decay mode due to a sufficiently negative back-EMF voltage in conjunction with the low voltage drop across the load during slow decay recirculation. The negative back-EMF voltage can cause the load current to actually increase during the slow decay off time. A negative back-EMF voltage condition commonly occurs when driving stepping motors because the phase lead of the rotor typically causes the back-EMF voltage to be negative towards the end of each step (see figure 3A). 2) When the desired load current is decreased rapidly, the slow rate of load current decay can prevent the current from following the desired reference value. 3) When the desired load current is set to a very low value, the current-control loop can fail to regulate due to its minimum duty cycle, which is a function of the user-selected value of t OFF and the minimum on-time pulse width ton(min) that occurs each time the PWM latch is reset. Fast Current-Decay Mode. When V PFD ≤ 0.8 V, the device is in fast current-decay mode (both the sink and source drivers are disabled when the load current reaches I TRIP). During the fixed off time, the load inductance causes the current to flow from ground to the load supply via the motor winding, ground-clamp and flyback diodes (see figure 1). Because the full motor supply voltage is across the load during fast-decay recirculation, the rate of load current decay is rapid, producing a high ripple current for a given fixed off time (see figure 2). This rapid rate of decay allows good current regulation to be maintained at Figure 2 Ñ Current-Decay Waveforms PFD ITRIP Dwg. WP-031-1 t IPEAK OFF SLOW (V ‡ 3.5 V)PFD MIXED (1.1 V £ V £ 3.1 V) FAST (V £ 0.8 V)PFD PFD

the cost of decreased average current accuracy or increased driver and motor losses. Mixed Current-Decay Mode. If VPFD is between 1.1 V and 3.1 V, the device will be in a mixed current-decay mode. Mixed-decay mode allows the user to achieve good current regulation with a minimum amount of ripple current and motor/driver losses by selecting the minimum percentage of fast decay required for their application (see also Stepper Motor Applications). As in fast current-decay mode, mixed-decay starts with the sink and source drivers disabled after the load current reaches I TRIP. When the voltage at the RC terminal decays to a value below VPFD , the sink drivers are re- enabled, placing the device in slow current-decay mode for the remainder of the fixed off time (figure 2). The percentage of fast decay (PFD) is user determined by V PFD or two external resistors. PFD = 100 ln (0.6[R1+R 2]/R2) where With increasing values of tOFF, switching losses will decrease, low-level load-current regulation will improve, EMI will be reduced, the PWM frequency will decrease, and ripple current will increase. A value of t OFF can be chosen for optimization of these parameters. For applica- tions where audible noise is a concern, typical values of t OFF are chosen to be in the range of 15 µs to 35 µs. RC Blanking. In addition to determining the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry (or by the PHASE input, or when the device is enabled with the DAC data inputs). The comparator output is blanked to prevent false over-current detections due to reverse recovery currents of the clamp diodes, and/or switching transients related to distributed capacitance in the load. During internal PWM operation, at the end of the t OFF time, the comparator’s output is blanked and CT begins to be charged from approximately 0.22VCC by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on C T reaches approximately 0.6VCC . The blanking time, tBLANK , can be calculated as: tBLANK = RTC T ln (RT/[RT - 3 kΩ ]). When a transition of the PHASE input occurs, CT is discharged to near ground during the crossover delay time (the crossover delay time is present to prevent simulta- neous conduction of the source and sink drivers). After the crossover delay, C T is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on C T reaches approxi- mately 0.6VCC . Similarly, when the device is disabled, via the DAC data inputs, CT is discharged to near ground. When the device is re-enabled, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on C T reaches approxi- mately 0.6VCC . The blanking time, tBLANK , can be calcu- lated as: tBLANK = RTC T ln ([RT - 1.1 kΩ ]/RT - 3 kΩ ). The minimum recommended value for CT is 470 pF ± 5 %. This value ensures that the blanking time is sufficient to avoid false trips of the comparator under Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one-shot off-time, t OFF , is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off- time, over a range of values of C T = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ , is approximated by: tOFF ≈ RTC T. When the load current is increasing, but has not yet reached the sense-current comparator threshold (ITRIP), the voltage on the RC terminal is approximately 0.6VCC . When ITRIP is reached, the PWM latch is reset by the current-sense comparator and the voltage on the RC terminal will decay until it reaches approximately 0.22V CC . The PWM latch is then set, thereby re-enabling the driver(s) and allowing load current to increase again. The PWM cycle repeats, maintaining the peak load current at the desired value. Dwg. EP-062-1 PFD VCC R 2 R 1

Worcester, Massachusetts 01615-0036 (508) 853-5000 normal operating conditions. For optimal regulation of the load current, this value for CT is recommended and the value of RT can be sized to determine tOFF . Thermal Considerations. Thermal-protection circuitry turns off all output transistors when the junction tempera- ture reaches approximately +165°C. This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. The output transistors are re- enabled when the junction temperature cools to approxi- mately +150°C. Stepper Motor Applications. The A3955SB or A3955SLB are used to optimize performance in microstepping/sinusoidal stepper-motor drive applications (see figures 4 and 5). When the load current is increas- ing, the slow current-decay mode is used to limit the switching losses in the driver and iron losses in the motor. This also improves the maximum rate at which the load current can increase (as compared to fast decay) due to the slow rate of decay during t OFF . When the load current is decreasing, the mixed current-decay mode is used to regulate the load current to the desired level. This pre- vents tailing of the current profile caused by the back-EMF voltage of the stepper motor (see figure 3A). Figure 5 Ñ Microstepping/Sinusoidal Drive Current Dwg. WK-004-3 MIXED DECAY MIXED DECAYSLOW DECAY SLOW DECAY Dwg. EP-047-3 D 1B 47 mF 30 kW 0.5 W VBB PHASE 470 pF +5 V REF PFD D 2B D 0B BRIDGE B D 1A 47 mF 30 kW 0.5 W VBB PHASE 470 pF +5 V REF PFD D 2A D 0A BRIDGE A A B V V V V 8 9 LOGIC LOGIC Figure 4 Ñ Typical Application

Step Step Step Step PHASE A D 2A D 1A D 0A ILOADA PHASE B D 2B D 1B D 0B ILOADB 1111 H H L L 70.7% H H L L 70.7% 2 H L H H 55.5% H H L H 83.1% 23 H L H L 38.2% H H H L 92.4% 4 H L L H 19.5% HHHH 100%

235 XLLL 0 % HHHH 100%

6 L L L H -19.5% HHHH 100% 4 7 L L H L -38.2% H H H L 92.4% 8 L L H H -55.5% H H L H 83.1% 2359 LHLL -70.7% H H L L 70.7% 10 L H L H -83.1% H L H H 55.5% 6 11 L H H L -92.4% H L H L 38.2% 12 L H H H -100% H L L H 19.5% 4 7 13 L H H H -100% X L L L 0% 14 L H H H -100% L L L H -19.5% 8 15 L H H L -92.4% L L H L -38.2% 16 L H L H -83.1% L L H H -55.5% 3 5 9 17 L H L L -70.7% L H L L -70.7% 18 L L H H -55.5% L H L H -83.1% 10 19 L L H L -38.2% L H H L -92.4% 20 L L L H -19.5% L H H H -100% 6 11 21 X L L L 0% L H H H -100% 22 H L L H 19.5% L H H H -100% 12 23 H L H L 38.2% L H H L -92.4% 24 H L H H 55.5% L H L H -83.1% 4 7 13 25 H H L L 70.7% L H L L -70.7% 26 H H L H 83.1% L L H H -55.5% 14 27 H H H L 92.4% L L H L -38.2% 28 H H H H 100% L L L H -19.5% 81 5 2 9 H H H H 100% XLLL0 % 30 H H H H 100% H L L H 19.5% 16 31 H H H L 92.4% H L H L 38.2% 32 H H L H 83.1% H L H H 55.5% Table 4 Ñ Step Sequencing

Worcester, Massachusetts 01615-0036 (508) 853-5000 Figure 5 Ñ Current and Displacement Vectors Dwg. GK-020-1 A A B B 100 92.4 83.1 70.7 55.5 38.2 19.5 100% CONSTANT TORQUE MAXIMUM FULL-STEP TORQUE (141%) CURRENT IN PER CENT CURRENT IN PER CENT 7/8 STEP 3/4 STEP 5/8 STEP 1/2 STEP 3/8 STEP 1/4 STEP 1/8 STEP FULL STEP

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Worcester, Massachusetts 01615-0036 (508) 853-5000 A3955SB Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 4. Webbed lead frame. Leads 4, 5, 12, and 13 are internally one piece. 0.508 0.204 7.62 BSC Dwg. MA-001-17A mm 10.92 MAX 1 8 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 19.68 18.67 NOTE 4 0.020 0.008 0.300 BSC Dwg. MA-001-17A in 0.430 MAX 1 8 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.775 0.735 NOTE 4

(for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.394 0.020 0.013 0.0926 0.1043 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-17A in 0.050 BSC 16 9 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Webbed lead frame. Leads 4, 5, 12, and 13 are internally one piece. 0° TO 8° 2 3 7.60 7.40 10.50 10.10 10.65 10.00 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-17A mm 1.27 BSC

Worcester, Massachusetts 01615-0036 (508) 853-5000 Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringe- ments of patents or other rights of third parties which may result from its use.