3935

3935_03 ALLEGRO

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Always order by complete part number, e.g., A3935KLQ . Data Sheet26301.102d 3-PHASE POWER MOSFET CONTROLLER — For Automotive Applications 3935 The A3935 is designed specifically for automotive applications that require high-power motors. Each provides six high-current gate drive outputs capable of driving a wide range of n-channel power MOSFETs. A requirement of automotive systems is steady operation over a varying battery input range. The A3935 integrates a pulse-frequency modulated boost converter to create a constant supply voltage for driving the external MOSFETs. Bootstrap capacitors are utilized to provide the above battery supply voltage required for n-channel FETs. Direct control of each gate output is possible via six TTL-compat- ible inputs. A differential amplifier is integrated to allow accurate measurement of the current in the three-phase bridge. Diagnostic outputs can be continuously monitored to protect the driver from short-to-battery, short-to-supply, bridge-open, and battery under/overvoltage conditions. Additional protection features include dead-time, VDD undervoltage, and thermal shutdown. The A3935 is supplied in a choice of two packages, a 48-lead low profile QFP with exposed thermal pad (suffix JP) and a 36-lead 0.8 mm pitch SOIC (suffix LQ).

FEATURES

„„„„„ Drives wide range of n-channel MOSFETs in 3-phase bridges „„„„„ PFM boost converter for use with low-voltage battery supplies „„„„„ Internal LDO regulator for gate-driver supply „„„„„ Bootstrap circuits for high-side gate drivers „„„„„ Current monitor output „„„„„ Adjustable battery overvoltage detection „ Motor lead short-to-battery, short-to-ground, and bridge-open protection „ Undervoltage protection „„„„„ -40 °C to +150 °C, TJ operation ABSOLUTE MAXIMUM RATINGS Load Supply Voltages, VBAT, VDRAIN, VBOOST, BOOSTD ... -0.6 V to 40 V Output Voltage Ranges, GHA/GHB/GHC, VGHX .. -4 V to 55 V GLA/GLB/GLC, VGLX .... -4 V to 16 V Sense Circuit Voltages, Logic Supply Voltage, Logic Input/Outputs and OVSET, BOOSTS, Operating Temperature Range, Storage Temperature Range, * Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Package JP, 48-Pin LQFP Package LQ, 36-Pin SOIC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-50002 Functional Block Diagram Copyright © 2003 Allegro MicroSystems, Inc. See pages 8 and 9 for terminal assignments and descriptions. VREG High-Side Driver Low-Side Driver Turn ON Delay CA GHA SA GLA LSS CSN To Phase B CBOOT To Phase C Turn ON Delay RS VBOOSTVBAT Control Logic CSP BOOSTSBOOSTD IHA ILA IHB ILB IHC ILC ENABLE GND cs Drain-Source Fault Monitor VBAT Overvoltage VBAT Undervoltage VREG Undervoltage Short to Ground Short to Battery Bridge Open VDD Undervoltage Thermal Shutdown VDSTH SA SB SC CSOUTVDRAIN Low Drop Out Linear Regulator VREG REFi REFv LSS VDRAIN (KELVIN) FAULT Motor Supply Voltage UVFLT OVFLT OVSET VDD Phase A VBAT VIGN VBAT VREG VDD VDD External +5V OS (blank) OS (off) Dwg. FP-053

www.allegromicro.com 3 50 75 100 125 15025 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 5.0 1.0 2.0 3.0 4.0 R θJA = 23°C/W* * Measured on 4-layer PCB. Additional information available on Allegro Web site. A3935KJP (LQFP with Exposed Thermal Pad) A3935KLQ (SOIC) 50 75 100 125 15025 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 5.0 1.0 2.0 3.0 4.0 RθJA = 44°C/W*

Worcester, Massachusetts 01615-0036 (508) 853-50004 ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Power Supply VDD Supply Current I DD All logic inputs = 0 V – – 7.0 mA VBAT Supply Current I BAT All logic inputs = 0 V – – 3.0 mA Battery Voltage Operating Range V BAT 7.0 – 40 V Bootstrap Diode Forward Voltage V DBOOT IDBOOT = -Icx = 10 mA, VDBOOT = VREG – VCX 0.8 – 2.0 V IDBOOT = -Icx = 100 mA 1.5 – 2.3 V Bootstrap Diode Resistance r DBOOT rD(100 mA) = [VD(150 mA) – VD(50 mA)]/100 mA 2.5 – 7.5 Ω Bootstrap Diode Current Limit I DM 3 V < [VREG – VCX] < 12 V -150 – -1150 mA Bootstrap Quiescent Current I CX VCX = 40 V, GHx = ON 10 – 30 µA Bootstrap Refresh Time t refresh VSX = low to guarantee ∆V = +0.5 V refresh of – – 2.0 µs 0.47 µF Boot Cap at Vcx – Vsx = +10 V VREG Output Voltage 1 VREG VBAT = 7 V to 40 V, VBOOST from Boost Reg 12.7 – 14 V VREG Dropout Voltage 2 VREGDO VREGDO = Vboost – Vreg, Ireg = 40 mA – 0.9 – V Gate Drive Avg. Supply Current I REG No external dc load at VREG, CREG = 10 µF – – 40 mA VREG Input Bias Current I REGBIAS Current into VBOOST, ENABLE = 0 – – 4.0 mA Boost Supply VBOOST Output Voltage Limit V BOOSTM VBAT = 7 V 14.9 – 16.3 V VBOOST Output Volt. Limit Hyst. ∆VBOOSTM 35 – 180 mV Boost Switch ON Resistance r DS(on) IBOOSTD < 300 mA – 1.4 3.3 Ω Max. Boost Switch Current I BOOSTSW – – 300 mA Boost Current Limit Threshold Volt. VBI(th) Increasing VBOOSTS 0.45 – 0.55 V OFF Time t off 3.0 – 8.0 µs Blanking Time t blank 100 – 220 ns NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. 1. For V BOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150 °C limit. 2. With V BOOST decreasing Dropout Voltage measured at VREG = VREGref – 200 mV where VREG(ref) = VREG at VBOOST = 16 V. Continued next page …

www.allegromicro.com 5 Characteristics Symbol Conditions Limits Min Typ Max Units Control Logic Logic Input Voltages V I(1) Minimum high level input for logical “one” 2.0 – – V VI(0) Maximum low level input for logical “zero” – – 0.8 V Logic Input Currents I I(1) VI = VDD – – 500 µA II(0) VI = 0.8 V 50 – – µA Input Hysteresis V hys 100 – 300 mV Logic Output High Voltage V O(H) IO(H) = -800 µA V DD – 0.8 – – V Logic Output Low Voltage V I(L) IO(L) = 1.6 mA – – 0.4 V Gate Drives, GHx ( internal SOURCE or upper switch stages) Output High Voltage V DSL(H) GHx: IxU = –10 mA, Vsx = 0 V REG – 2.26 – V REG V GLx: IxU = –10 mA, Vlss = 0 V REG – 0.26 – V REG V Source Current (pulsed) I xU VSDU = 10 V, TJ = 25 °C – 800 – mA VSDU = 10 V, TJ = 135 °C 400 – – mA Source ON Resistance r SDU(on) IxU = –150 mA, TJ = 25 °C 4.0 – 10 Ω IxU = –150 mA, TJ = 35 °C 7.0 – 15 Ω Gate Drives, GLx ( internal SINK or lower switch stages) Sink Current (pulsed) I xL VDSL = 10 V, TJ = 25 °C – 850 – mA VDSL = 10 V, TJ = 135 °C 550 – – mA Sink ON Resistance r DSL(on) IxL = +150 mA, TJ = 25 °C 1.8 – 6.0 Ω IxL = +150 mA, TJ = 135 °C 3.0 – 7.5 Ω Gate Drives, GHx, GLx (General) Phase Leakage (Source) I Sx ENABLE = 0, VSx = 1.7 V 0 – 100 µA Propagation Delay, Logic only t pd Logic input to unloaded GHx, GLx – – 150 ns Output Skew Time t sk(o) Grouped by edge, phase-to-phase – – 50 ns Dead Time (Shoot-Through Prevention) tdead Between GHx, GLx transitions of same phase 75 – 180 ns NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is de fi ned as coming out of (sourcing) the specifi ed device terminal. For GH X: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX. For GL X: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS. ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.

Worcester, Massachusetts 01615-0036 (508) 853-50006 ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Sense Amplifier Input Bias Current I bias CSP = CSN = 0 V -180 – -360 µA Input Offset Current I IO CSP = CSN = 0 V – – ±35 µA Input Resistance r i CSP with respect to GND – 80 – k Ω CSN with respect to GND – 4.0 – k Ω Diff. Input Operating Voltage V ID VID = CSP – CSN, -1.3V < CSP,N < 4V – – ±200 mV Output Offset Voltage V OO CSP = CSN = 0 V 77 250 450 mV Output Offset Voltage Drift ∆VOO CSP = CSN = 0 V – 100 – µV/°C Input Com-Mode Oper. Range V IC CSP = CSN -1.5 – 4.0 V Voltage Gain A V VID = 40 mV to 200 mV 18.6 19.2 19.8 V/V Low Output Voltage Error E v Vid = 0 to 40 mV, Vo = (19.2 x VID) + Vo + Ev – – ±25 mV DC Common-Mode Attenuation A VC CSP = CSN = 200 mV 28 – – dB Output Resistance r o VCSOUT = 2.0 V – 8.0 – Ω Output Dynamic Range V CSOUT ICSOUT = -100 µA at top rail, 100 µA at bottom rail 0.075 – V DD-0.25 V Output Current, Sink I sink VCSOUT = 2.5 V 20 – – mA Output Current, Source I source VCSOUT = 2.5 V -1.0 – – mA VDD Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 1 MHz 20 – – dB VREG Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 300 kHz 45 – – dB Small Signal 3-dB Bandwidth f 3db 10 mV input – 1.6 – MHz AC Common-Mode Attenuation A vc Vcm = 250 mV/pp, freq. = 0 to 800 kHz 26 – – dB Output Slew Rate SR 200 mV step input, meas. 10/90% points 10 – – V/µs (positive or negative) NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal.

www.allegromicro.com 7 ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Fault Logic VDD Undervoltage V DD(uv) Decreasing VDD 3.8 – 4.3 V VDD Undervoltage Hysteresis ∆VDD(uv) VDD(recovery) - VDD(uv) 100 – 300 mV OVSET Operating Volt. Range V SET(ov) 0– V DD V OVSET Calibrated Volt. Range V SET(ov) 0 – 2.5 V OVSET Input Current Range I SET(ov) -1.0 – +1.0 µA VBAT Overvoltage Range V BAT(ov) 0 V < VSET(ov) < 2.5 V 19.4 – 40 V VBAT Overvoltage V BAT(ov) Increasing VBAT, VSET(ov) = 0 V 19.4 22.4 25.4 V VBAT Overvoltage Hysteresis ∆VBAT(ov) Percent of VBAT(ov) value set by VSET(ov) 9.0 – 15 % VBAT Overvoltage Gain Constant KBAT(ov) VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov) [0] – 12 – V/V VBAT Undervoltage V BAT(uv) Decreasing VBAT 5.0 5.25 5.5 V VBAT Undervoltage Hysteresis ∆VBAT(uv) Percent of VBAT(uv) 8.0 – 12 % VREG Undervoltage V REG(uv) Decreasing VREG 9.9 – 11.1 V VDSTH Input Range V DSTH 0.5 – 3.0 V VDSTH Input Current I DSTH VDSTH > 0.8 V 40 – 100 µA Short-to-Ground Threshold V STG(th) With a high-side driver “on”, as VSX decreases, V DSTH-0.3 – V DSTH+0.2 V VDRAIN - VSX > VSTG causes a fault Short-to-Battery Threshold V STB(th) With a low-side driver “on”, as VSX increases, V DSTH-0.3 – V DSTH+0.2 V VSX - VLSS > VSTB causes a fault VDRAIN /Open Bridge Oper. Range V DRAIN 7 V < VBAT < 40 V -0.3 – V BAT+2.0 V VDRAIN /Open Bridge Current I VDRAIN 7 V < VBAT < 40 V 0 – 1.0 mA VDRAIN /Open Bridge Threshold Volt. VBDGO(th) If VDRAIN < VBDGOTH then a bridge fault occurs 1.0 – 3.0 V Thermal Shutdown Temp. T J 160 170 180 °C Thermal Shutdown Hysteresis ∆TJ 7.0 10 13 °C NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal.

Worcester, Massachusetts 01615-0036 (508) 853-50008 Terminal Functions A3935KJP A3935KLQ Terminal Name Function (QLFP) (SOIC) CSP Current-sense input, positive-side 19 1 VDSTH DC input, drain-to-source monitor threshold voltage 20 2 LSS Gate-drive source return, low-side 21 3 GLC Gate-drive C output, low-side 22 4 SC Load phase C input 26 5 GHC Gate-drive C output, high-side 27 6 CC Bootstrap capacitor C 28 7 GLB Gate-drive B output, low-side 29 8 SB Load phase B input 30 9 GHB Gate-drive B output, high-side 31 10 CB Bootstrap capacitor B 32 11 GLA Gate-drive A output, low-side 33 12 SA Load phase A input 34 13 GHA Gate-drive A output, high-side 38 14 CA Bootstrap capacitor A 39 15 VREG Gate drive supply, positive 40 16 VDRAIN Kelvin connection to MOSFET high-side drains 41 17 VBOOST Boost supply output 42 18 BOOSTS Boost switch, source 43 19 BOOSTD Boost switch, drain 44 20 VBAT Battery supply, positive 46 22 UVFLT VBAT undervoltage fault output 3 23 OVFLT VBAT overvoltage fault output 4 24 FAULT Active-low fault output, primary 5 25 ALO Gate control input A, low-side 6 26 AHI Gate control input A, high-side 7 27 BHI Gate control input B, high-side 8 28 BLO Gate control input B, low-side 9 29 CLO Gate control input C, low-side 10 30 CHI Gate control input C, high-side 11 31 ENABLE Gate output enable 12 32 OVSET DC input, overvoltage threshold setting for VBAT 15 33 NC Not connected, no external connection allowed 1,2,13,14,23,24, – 25,35,36,37,47,48 CSOUT Current-sense amplifier output 16 34 VDD Logic supply, nominally +5 V 17 35 CSN Current-sense input, negative-side 18 36 GND Ground, dc supply returns, negative, and (for ED package) 45 21 heat sink tab

www.allegromicro.com 9 Terminal Descriptions AHI/BHI/CHI. Direct control of high-side gate outputs GHA/ GHB/GHC. Logic “1” drives the gate “on”. Logic ”0” pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. ALO/BLO/CLO. Direct control of low-side gate outputs GLA/ GLB/GLC. Logic “1” drives the gate “on”. Logic ”0” pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. BOOSTD. Boost converter switch drain connection. BOOSTS. Boost converter switch source connection. CA/CB/CC. High-side connection for bootstrap capacitor, positive supply for high-side gate drive. The bootstrap capacitor is charged to VREG when the output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for n- channel power MOSFETs. CSN. Input for current-sense, differential amplifier, inverting, negative side. Kelvin connection for ground side of current- sense resistor. CSOUT. Amplifier output voltage proportional to current sensed across an external low-value resistor placed in the ground-side of the power FET bridge. CSP. Input for current-sense differential amplifier, non- inverting, positive side. Connected to positive side of sense resistor. ENABLE. Logic “0” disables the gate control signals and switches off all the gate drivers “low” causing a “coast”. Can be used in conjunction with the gate inputs to PWM the load current. Internally pulled down when terminal is open. FAULT. Diagnostic logic output signal, when “low” indicates that one or more fault condition have occurred. GHA/GHB/GHC. High-side gate-drive outputs for n-channel MOSFET drivers. External series gate resistors can control slew rate seen at the power driver gate; thereby, controlling the di/dt and dv/dt of Sx outputs. GLA/GLB/GLC. Low-side gate drive outputs for external, n- channel MOSFET drivers. External series gate resistors can control slew rate. GND. Ground or negative side of VDD and VBAT supplies. LSS. Low-side gate driver returns. Connects to the common sources in the low-side of the power MOSFET bridge. OVFLT. Logic “1” means that the VBAT exceeded the VBAT overvoltage trip point set by OVSET level. It will recover after a hysteresis below that maximum value. Normally has a high- impedance state. OVSET. A positive, dc level that controls the VBAT overvolt- age trip point. Usually, provided from precision resistor divider network between V DD and GND, but can be held grounded for a preset value. When terminal is open, sets unspecified but high overvoltage trip point. SA/SB/SC. Directly connected to the motor terminals, these terminals sense the voltages switched across the load and are connected to the negative side of the bootstrap capacitors. Also, are the negative supply connection for the floating, high-side drivers. UVFLT. Logic “1” means that VBAT is below its minimum value and will recover after a hysteresis above that minimum value. Has a high-impedance state. [If UVFLT and OVFLT are both in high-impedance state; then, at least, a thermal shutdown or VDD undervoltage has occurred.] VBAT. Battery voltage, positive input and is usually connected to the motor voltage supply. VBOOST. Boost converter output, nominally 16 V, is also input to regulator for VREG. Has internal boost current and boost voltage control loops. In high-voltage systems is approxi- mately one diode drop below V BAT. VDD. Logic supply, nominally +5 V. VDRAIN. Kelvin connection for drain-to-source voltage monitor and is connected to high-side drains of MOSFET bridge. High impedance when terminal is open and registers as a short-to-ground fault on all motor phases. VDSTH. A positive, dc level that sets the drain-to-source monitor threshold voltage. Internally pulled down when terminal is open. VREG. High-side, gate-driver supply, nominally, 13.5 V. Has low-voltage dropout (LDO) feature.

Worcester, Massachusetts 01615-0036 (508) 853-500010 Functional Description Motor Lead Protection. A fault detection circuit monitors the voltage across the drain to source of the external MOSFETs. A fault is asserted “low” on the output terminal, FAULT, if the drain-to-source voltage of any MOSFET that is instructed to turn on is greater than the voltage applied to the V DSTH input terminal. When a high-side switch is turned on, the voltage from VDRAIN to the appropriate motor phase output, VSX, is examined. If the motor lead is shorted to ground before the high side is turned on, the measured voltage will exceed the threshold and the FAULT terminal will go “low”. Similarly, when a low-side MOSFET is turned on, the differential voltage between the motor phase (drain) and the LSS terminal (source) is monitored. V DSTH is set by a resistor divider to VDD. The VDRAIN is intended to be a Kelvin connection for the high- side, drain-source monitor circuit. Voltage drops across the power bus are eliminated by connecting an isolated PCB trace from the V DRAIN terminal to the drain of the MOSFET bridge. This allows improved accuracy in setting the VDSTH threshold voltage. The low-side, drain-source monitor uses the LSS terminal, rather than V DRAIN, in comparing against VDSTH. The A3935 merely reports these motor faults. Fault Outputs. Transient faults on any of the fault outputs are to be expected during switching and will not disable the gate drive outputs. External circuitry or controller logic must determine if the faults represent a hazardous condition. FAULT. This terminal will go active “low” when any of the following conditions occur: V BAT overvoltage, VBAT undervoltage, VREG undervoltage, Motor lead short-to-ground, Motor lead short-to-supply (or battery), Bridge (or V DRAIN) open, VDD undervoltage, or Thermal shutdown. OVFLT. Asserts “high” when a VBAT overvoltage fault occurs and resets “low” after a recovery hysteresis. It has a high- impedance state when a thermal shutdown or V DD undervoltage occurs. The voltage at the OVSET terminal, VOVSET, controls the VBAT overvoltage set point VBAT(ov), i.e., VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0), where KBAT(ov) is the gain (12) and VBAT(ov)(0) is the value of VBAT(ov) when VSET(ov) is zero (~22.4). For valid formula, all variables must be in range and below maximum operating specification. UVFLT. Asserts “high” when a V BAT undervoltage fault occurs and resets “low” after a recovery hysteresis. It has a high- impedance state when a thermal shutdown or VDD undervoltage occurs. OVFLT and UVFLT are mutually exclusive by defini- tion. Current Sensing. A current-sense amplifier is provided to allow system monitoring of the load current. The differential amplifier inputs are intended to be Kelvin connected across a low-value sense resistor or current shunt. The output voltage is represented by: V CSOUT = ( ILOAD x AV x RS) + VOS where VOS is the output voltage calibrated at zero load current and AV is the differential amplifier gain of about 19.2. If either the CSP or CSN pin is open, the CSOUT pin will go to its maximum positive level. Shutdown. If a fault occurs because of excessive junction temperature or undervoltage on V DD or VBAT, all gate driver outputs are driven “low” until the fault condition is removed. In addition, the boost supply switch and the VREG are turned “off” until those undervoltages and junction temperatures recover. Boost Supply. V BOOST is controlled by an inner current- control loop, and by an outer voltage-feedback loop. The current-control loop turns “off” the boost switch for 5 µs whenever the voltage across the boost current-sense resistor exceeds 500 mV. A diode reverse-recovery current flows through the sense resistor whenever the boost switch turns “on”, which could turn it “off” again if not for the “blanking time” circuit. Adjustment of this external sense resistor determines the maximum current in the inductor. Whenever V BOOST exceeds the predefined threshold, nominally 16 V, the boost switch is inhibited.

www.allegromicro.com 11 Functional Description (cont’d) Input Logic ENABLE xLO xHI GLx GHx Mode of Operation

0 X X 0 0 All gate drive outputs low

1 0000 Both gate drive outputs low 1 0101 High side on 1 1010 Low side on 1 1100 XOR circuitry prevents shoot-through Fault Responses ENABLE Boost V REG Fault Mode Input FAULT OVFLT UVFLT Reg. Reg. GHx GLx No Fault X 1 0 0 ON ON "" Short-to-Battery 1 # 0 0 0 ON ON "" Short-to-Ground 1 $ 0 0 0 ON ON "" Bridge (VDRAIN) Fault 1 % 0 0 0 ON ON "" VREG Undervoltage X 0 0 0 ON ON "" VBAT Overvoltage X 0 1 0 OFF & ON "" VBAT Undervoltage' X 0 0 1 OFF OFF 0 0 VDD Undervoltage' X 0 Z Z OFF OFF 0 0 Thermal Shutdown' X 0 Z Z OFF OFF 0 0 NOTES: x = “Little x ”indicates A, B, or C phase. X = “Capital X “ indicates a “don’t care”. Z = High-impedance state. " = Depends on xLO input, xHI input, and ENABLE. See Input Logic table. # = Short-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0. $ = Short-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0. % = Bridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0. & = Off, only because VBOOST ≈ VBAT is above the voltage threshold of the regulator’s voltage control loop. ' = These faults are not only reported but action is taken by the internal logic to protect the A3935 and the system.

Worcester, Massachusetts 01615-0036 (508) 853-500012 NC NC 48 CA VREG VDRAIN VBOOST BOOSTS BOOSTD GND VBAT 37NC GHA NC

22 GLC

33 GLA

Package JP, 48-Pin LQFP Package LQ, 36-Pin SOIC CB GLA SA GHA CA VREG VDRAIN VBOOST ALO FAULT OVFLT UVFLT VBAT GND BOOSTD BOOSTS 34LSS GLC SC GHC CC GLB SB GHB CSOUT1 OVSET ENABLE CHI CLO BLO BHI CSP VDSTH CSN VDD AHI

Worcester, Massachusetts 01615-0036 (508) 853-500013 Exposed thermal pad (bottom surface)A A .20 .09 0.008 0.004 .75 .45 0.030 0.018.15 .05 0.006 0.002 .27 .17 0.011 0.007 REF 0.039 BSC 0.197 .50 BSC .020 .25 BSC 0.010 BSC 0.276 BSC 0.354 1.60 1.40 0.063 0.055 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Gauge Plane Seating Plane A3935KJP (LQFP)

www.allegromicro.com 14 A3935KLQ (SOIC) Dimensions in Millimeters (controlling dimensions) Dimensions in Inches (for reference only) NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.

Worcester, Massachusetts 01615-0036 (508) 853-500015 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.