3822

3822 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 59

Technical content

DESCRIPTION

The 3822 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 3822 group (A version) has the LCD drive control circuit, an 8- channel A-D converter, and a serial I/O as additional functions. The various microcomputers in the 3822 group (A version) include variations of internal memory size and packaging. For details, re- fer to the section on part numbering.

FEATURES

(at f(XIN) = 10 MHz, High-speed mode)

• Memory size
• Software pull-up/pull-down resistors (Ports P0-P7 except port P40) (includes key input interrupt)
• LCD drive control circuit
• 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage In high-speed mode
• Power dissipation (at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C) (at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 3 V, Ta = 25 °C)

APPLICATIONS

Camera, household appliances, consumer electronics, etc. Fig. 1 M3822XMXA-XXXFP pin configuration PIN CONFIGURATION (TOP VIEW) Package type : 80P6N-A (80-pin plastic-molded QFP) S E G 8 S E G P S E G 1 P S E G 1 P S E G 1 P S E G 1 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 3 P S E G 3 V P 67/ A N 7 M X M X A X X X F P P 57/ A D T P 50/ I N P 46/ SC L K P 45/ TXD P 43/ I N P 42/ I N A V S S VR E F VC C S E G 0 P 41/φ P XI N XO U T VS S P P P P P P P P R E S E T P 51/ I N P 55/ C N T R 1 P 54/ C N T R 0 P 53/ R T P 52/ R T P 56/ TO U T P S E G 2 P S E G 1 P S E G 1 P 47/ SR D Y S E G S E G P S E G 1 P S E G 1 P 70/ XC O U T P 71/ XC I N C O M 0 V L P 66/ A N 6 P 65/ A N 5 P 64/ A N 4 P 63/ A N 3 P 62/ A N 2 P 61/ A N 1 P 60/ A N 0 V C O M 1 C O M 2 C O M 3 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 P 44/ R XD 1 2 3 4 5 6 7 8 9 1 3822 Group (A ver.) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0076-0120Z Rev.1.20 2003.12.24 Rev.1.20 Dec 24, 2003 page 1 of 57

Rev.1.20 Dec 24, 2003 page 2 of 57 3822 Group (A ver.) Package type : 80P6Q-A (80-pin plastic-molded QFP) PIN CONFIGURATION (TOP VIEW) Fig. 2 M3822XMXA-XXXHP pin configuration P S E G 2 P S E G 2 P 16/ S E G 3 P 17/ S E G 3 P 42/ I N VC C XI N XO U T VS S P P P P P P P P R E S E T P 70/ XC O U T P 71/ XC I N P 41/φ P P 43/ I N S E G P S E G 1 P S E G 1 P S E G 1 P S E G 1 P S E G 1 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 1 P S E G 1 P S E G 2 C O M 3 P 60/ A N 0 P 57/ A D T P 56/ TO U T P 54/ C N T R 0 P 53/ R T P 52/ R T P 51/ I N P 55/ C N T R 1 P 46/ SC L K P 45/ TXD P 50/ I N P 47/ SR D Y P 44/ R XD S E G 1 S E G 2 S E G 3 S E G 4 S E G 6 S E G 5 S E G 7 S E G 0 S E G 8 S E G 9 C O M 2 C O M 1 C O M 0 VL VL VL VR E F A VS S P 61/ A N 1 P 62/ A N 2 P 63/ A N 3 P 64/ A N 4 P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 S E G P S E G 1 M X M X A X X X H P

Rev.1.20 Dec 24, 2003 page 3 of 57 3822 Group (A ver.) FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A) Fig. 3 Functional block diagram K e y o n w a k e u p R e a l t i m e p o r t f u n c t i o n I N T 2, I N T3 C N T R 0, C N T R 1 TO U T A D T I N T 0, I N T1 φ R T P 0, R T P1 D a t a b u s C P U A X Y S P C H P C L P S R E S E TV C C VS S R e s e t I n p u t( 5 V ) (

0 V )

L C D d i s p l a y R A M b y t e s 2 5 7 13 0 I / O P o r t P 5 P 4 ( 8 ) I / O P o r t P 4 I / O P o r t P 2 P 2 ( 8 ) I / O P o r t P 0 P 0 ( 8 ) I / O P o r t P 1 P 1 ( 8 )P 6 ( 8 ) I n p u t P o r t P 3 P 3 ( 4 ) I / O P o r t P 6 P 5 ( 8 ) I / O P o r t P 7 P 7 ( 2 ) 8 0 7 4 8 4 9 5 0 5 1 5 25 35 43 94 04 14 24 34 44 54 63 13 23 33 43 53 63 73 85 55 65 75 81 92 02 12 22 32 41 71 82 62 7 123 456 78 7 37 2 1 01 11 21 31 41 51 69 C l o c k g e n e r a t i n g c i r c u i t M a i n C l o c k I n p u t XI N M a i n C l o c k O u t p u t XO U T XC O U T S u b C l o c k O u t p u t X C I N S u b C l o c k I n p u t S I / O ( 8 ) VR E F A VS S V A - D c o n v e r t e r T i m e r X ( 1 6 ) T i m e r Y ( 1 6 ) T i m e r 1 ( 8 )T i m e r 2 ( 8 ) T i m e r 3 ( 8 ) L C D d r i v e c o n t r o l c i r c u i t VL VL VL C O M 0 C O M C O M C O M S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G φ XC I N XC O U T 2 8 2

Rev.1.20 Dec 24, 2003 page 4 of 57 3822 Group (A ver.) PIN DESCRIPTION Table 1 Pin description (1) VCC , VSS FunctionPin Name Function except a port function

• LCD segment output pins Power source • Apply voltage of power source to VCC , and 0 V to VSS . (For the limits of VCC , refer to “Recom- mended operating conditions”). VREF AV SS RESET XIN XOUT VL1–VL3 COM 0–COM 3 SEG 0–SEG 11 P00/SEG 16– P07/SEG 23 P10/SEG 24– P17/SEG 31 P20 – P27 P34/SEG 12 – P37/SEG 15 Analog refer- ence voltage Analog power source Reset input Clock input Clock output LCD power source Common output Segment output I/O port P0 I/O port P1 I/O port P2
• Reference voltage input pin for A-D converter.
• GND input pin for A-D converter.
• Connect to VSS .
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This clock is used as the oscillating source of system clock.
• Input 0 ≤ V L1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – VL3 voltage to LCD.
• LCD common output pins.
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each port to be individually programmed as either input or output.
• Pull-down control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 4-bit input port.
• CMOS compatible input level.
• Pull-down control is enabled.
• Key input (key-on wake-up) interrupt input pins
• LCD segment output pinsInput port P3

Rev.1.20 Dec 24, 2003 page 5 of 57 3822 Group (A ver.) Table 2 Pin description (2) FunctionPin Name Function except a port function P40 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK , P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR 0, P55/CNTR 1 P56/TOUT P57/ADT P60/AN0– P67/AN7 P70/XCOUT, P71/XCIN I/O port P4 I/O port P5 I/O port P6 I/O port P7

• 1-bit Input port.
• CMOS compatible input level.
• 7-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• φ clock output pin
• Interrupt input pins
• Interrupt input pins
• Real time port function pins
• Timer X, Y function pins
• Timer 2 output pins
• A-D conversion input pins
• Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.) Input port P4 P41/φ
• Serial I/O function pins
• A-D trigger input pins

Rev.1.20 Dec 24, 2003 page 6 of 57 3822 Group (A ver.) PART NUMBERING Fig. 4 Part numbering Package type FP : 80P6N-A package HP : 80P6Q-A package ROM number Omitted in One Time PROM version shipped in blank and EPROM version. When electrical characteristic, or division of identification code using Product M3822 4 M 6 A- XXX FP alaphanumeric character A– : A version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bites and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes

Rev.1.20 Dec 24, 2003 page 7 of 57 3822 Group (A ver.) GROUP EXPANSION (A VERSION) Mitsubishi plans to expand the 3822 group (A version) as follows: Memory Type Support for Mask ROM version. Memory Size Package Currently products are listed below. Memory Expansion Plan RemarksPackagePart number As of Sep. 2002 RAM size (bytes) 16384 (16254) ROM size (bytes) ROM size for User in ( ) 24576 (24446) Fig. 5 Memory expansion plan for A version Table 3 List of products for H version M38223M4A-XXXFP M38223M4A-XXXHP M38224M6A-XXXFP M38224M6A-XXXHP M38227M8A-XXXFP M38227M8A-XXXHP M38227MCA-XXXFP M38227MCA-XXXHP 512 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version 640 32768 (32638) 49152 (49022) 1024 32K 28K 24K 20K 16K 12K 256 384 512 640 768 896 1024192 M38223M4A RAM size (bytes) R OM size (bytes) 48K M38224M6A M38227M8A M38227MCA

Rev.1.20 Dec 24, 2003 page 8 of 57 3822 Group (A ver.) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3822 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 7 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 6 740 Family CPU register structure A Accumulator b7 b0 b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Rev.1.20 Dec 24, 2003 page 9 of 57 3822 Group (A ver.) Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ” E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C L) E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C L) S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

Rev.1.20 Dec 24, 2003 page 10 of 57 3822 Group (A ver.) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.1.20 Dec 24, 2003 page 11 of 57 3822 Group (A ver.) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. Fig. 8 Structure of CPU mode register Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Port X C switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(X IN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) CPU mode register (CPUM (CM) : address 003B16) b7 b0

Rev.1.20 Dec 24, 2003 page 12 of 57 3822 Group (A ver.) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ter (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 1 9 2 0 0 F F1 B B B R A M a r e a R A M s i z e b y t e s A d d r e s s X X X 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A R O M a r e a R O M s i z e b y t e s A d d r e s s Y Y Y A d d r e s s Z Z Z 0 1 0 01 0 0 0 01 0 0 4 01 0 8 4 01 F F 0 01 F F D C 1 F F F E1 F F F F1 X X X X1 Y Y Y Y1 Z Z Z Z1 R A M R O M R e s e r v e d a r e a S F R a r e a N o t u s e d I n t e r r u p t v e c t o r a r e a R e s e r v e d R O M a r e a b y t e s Z e r o p a g e S p e c i a l p a g e R e s e r v e d R O M a r e a 0 0 5 01 L C D d i s p l a y R A M a r e a

Rev.1.20 Dec 24, 2003 page 13 of 57 3822 Group (A ver.) Fig. 10 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Port P0 (P0) Port P1 (P1) Port P1 output control register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Serial I/O status register (SIOSTS) Serial I/O control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Interrupt control register 2(ICON2) Timer 3 (T3) Timer X mode register (TXM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X (low) (TXL) Timer Y (low) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high) (TXH) Timer Y (high) (TYH) PULL register A (PULLA) PULL register B (PULLB) Timer Y mode register (TYM) Timer 123 mode register (T123M) φ output control register (CKOUT) Segment output enable register (SEG) LCD mode register (LM) A-D control register (ADCON) A-D conversion register (AD) Transmit/Receive buffer register(TB/RB) Port P0 direction register (P0D)

Rev.1.20 Dec 24, 2003 page 14 of 57 3822 Group (A ver.) I/O PORTS Direction Registers (ports P2, P41-P47, and P5-P7) The 3822 group has 49 programmable I/O pins arranged in seven I/O ports (ports P0–P2, P41–P4 7 and P5-P7). The I/O ports P2, P4 1–P4 7 and P5-P7 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be in- put port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the in- put/output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports except for port P40 can control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Fig. 11 Structure of PULL register A and PULL register B P 00– P 07 p u l l - d o w n P 10– P p u l l d o w n P 20– P p u l l u p P 34– P p u l l d o w n P 70, P p u l l u p N o t u s e d r e t u r n w h e n r e a d P U L L r e g i s t e r A P U L L A a d d r e s s b 7 b 0 P 41– P 43 p u l l - u p P 44– P p u l l u p P 50– P p u l l u p P 54– P p u l l u p P 60– P p u l l u p P 64– P p u l l u p N o t u s e d r e t u r n w h e n r e a d 0 : D i s a b l e E n a b l e P U L L r e g i s t e r B P U L L B a d d r e s s b 7 b 0 N o t e: T h e c o n t e n t s o f P U L L r e g i s t e r A a n d P U L L r e g i s t e r B d o n o t a f f e c t p o r t s p r o g r a m m e d a s t h e o u t p u t p o r t

Rev.1.20 Dec 24, 2003 page 15 of 57 3822 Group (A ver.) Real time port function output A-D conversion input A-D trigger input Diagram No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 6 List of I/O port function P00/SEG 16– P07/SEG 23 P10/SEG 24– P17/SEG 31 P20–P2 7 P34/SEG 12– P37/SEG 15 P40 P41/φ P42/INT0, P43/INT1 P44/RXD P45/TXD P46/SCLK P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR 0 Port P0 Port P1 Port P2 Port P3 Port P4 Input/output, individual ports Input/output, individual bits Input Input Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD segment output Key input (key-on wake-up) interrupt input LCD segment output φ clock output External interrupt input Serial I/O function I/O External interrupt input Timer X function I/O Timer Y function input Timer 2 function output PULL register A Segment output enable register PULL register A Interrupt control register 2 PULL register A Segment output enable register PULL register B φ output control register PULL register B Interrupt edge selection register PULL register B Serial I/O control register Serial I/O status register UART control register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register PULL register A CPU mode register (1) (2) (3) (4) (6) (5) (2) (8) (7) Port P5 (9) (2)Input/output, individual bits (10) P55/CNTR 1 (11) (12) (13) (12) (14) P56/TOUT P57/ADT P60/AN0– P67/AN7 (15)P70/XCOUT P71/XCIN COM 0–COM 3 SEG 0–SEG 11 (16) (17) (18) Input/output, individual bits Input/output, individual bits Output Output Sub-clock generating circuit I/O LCD common output LCD segment output Port P6 Port P7 Common Segment LCD mode register Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections. 2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Especially, power source current may increase during execution of the STP and WIT instructions. Fix the unused input pins to “H” or “L” through a resistor.

Rev.1.20 Dec 24, 2003 page 16 of 57 3822 Group (A ver.) Fig. 12 Port block diagram (1) ( 3 ) P o r t s P 34– P 37 VL 2/ VL VL 1/ VS S S e g m e n t o u t p u t e n a b l e b i t VL 2/ VL VL 1/ VS S ( N o t e ) ( 2 ) P o r t s P 2 , P 42, P 43, P 50, P 51 D i r e c t i o n r e g i s t e r ( 5 ) P o r t P 41 D i r e c t i o n r e g i s t e r ( 6 ) P o r t P 44 R e c e i v e e n a b l e b i t D i r e c t i o n r e g i s t e r ( 4 ) P o r t P 40 D a t a b u s P u l l - d o w n c o n t r o l S e g m e n t o u t p u t e n a b l e b i t D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l l - d o w n c o n t r o l S e g m e n t o u t p u t e n a b l e b i t D a t a b u s P o r t l a t c h P u l l - u p c o n t r o l K e y i n p u t ( K e y - o n w a k e - u p ) i n t e r r u p t i n p u t I N T0– I N i n t e r r u p t i n p u t φ φ o u t p u t c o n t r o l b i t P u l l - u p c o n t r o l D a t a b u s P o r t l a t c h P u l l - u p c o n t r o l S e r i a l I / O e n a b l e b i t S e r i a l I / O i n p u t D a t a b u s P o r t l a t c h D a t a b u s ( 1 ) P o r t s P 0 , P 1 N o t e : B i t 0 o f d i r e c t i o n r e g i s t e r .

Rev.1.20 Dec 24, 2003 page 17 of 57 3822 Group (A ver.) Fig. 13 Port block diagram (2) D i r e c t i o n r e g i s t e r P o r t l a t c h S e r i a l I / O e n a b l e b i t T r a n s m i t e n a b l e b i t P 45/ TxD P - c h a n n e l o u t p u t d i s a b l e b i t P u l l - u p c o n t r o l ( 7 ) P o r t P 45 S e r i a l I / O o u t p u t D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s S e r i a l I / O r e a d y o u t p u t S e r i a l I / O m o d e s e l e c t i o n b i t P u l l - u p c o n t r o l ( 9 ) P o r t P 47 ( 8 ) P o r t P 46 S e r i a l I / O c l o c k - s y n c h r o n i z e d s e l e c t i o n b i t S e r i a l I O e n a b l e b i t S e r i a l I / O m o d e s e l e c t i o n b i t S e r i a l I O e n a b l e b i t D i r e c t i o n r e g i s t e r P o r t l a t c h S e r i a l I / O c l o c k o u t p u t D a t a b u s S e r i a l I / O c l o c k i n p u t P u l l - u p c o n t r o l ( 1 0 ) P o r t s P 52 P 53 D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s P u l l - u p c o n t r o l R e a l t i m e p o r t c o n t r o l b i t D a t a f o r r e a l t i m e p o r t D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s P u l l - u p c o n t r o l ( 1 2 ) P o r t s P 55 P 57 C N T R 1 i n t e r r u p t i n p u t A D t r i g g e r i n t e r r u p t i n p u t ( 1 1 ) P o r t P 54 D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s P u l l - u p c o n t r o l T i m e r X o p e r a t i n g m o d e b i t T i m e r o u t p u t C N T R 0 i n t e r r u p t i n p u t S e r i a l I / O e n a b l e b i t SR D Y o u t p u t e n a b l e b i t ( P u l s e o u t p u t m o d e s e l e c t i o n )

Rev.1.20 Dec 24, 2003 page 18 of 57 3822 Group (A ver.) Fig. 14 Port block diagram (3) VL 2/ VL VL 1/ VS S ( 1 3 ) P o r t P 56 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l - u p c o n t r o l TO U T o u t p u t c o n t r o l b i t T i m e r o u t p u t ( 1 4 ) P o r t P 6 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l l - u p c o n t r o l A - D c o n v e r s i o n i n p u t A n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 5 ) P o r t P 70 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P o r t XC s w i t c h b i t + P u l l - u p c o n t r o l P o r t XC s w i t c h b i t O s c i l l a t i o n c i r c u i t P o r t P 71 P o r t XC s w i t c h b i t ( 1 6 ) P o r t P 71 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P o r t XC s w i t c h b i t P o r t XC s w i t c h b i t + P u l l - u p c o n t r o l S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t VL VL VL ( 1 7 ) C O M 0– C O M 3 ( 1 8 ) S E G 0– S E G 1 T h e g a t e i n p u t s i g n a l o f e a c h t r a n s i s t o r i s c o n t r o l l e d b y t h e L C D d u t y r a t i o a n d t h e b i a s v a l u e T h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f P c h a n n e l a n d N c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e

Rev.1.20 Dec 24, 2003 page 19 of 57 3822 Group (A ver.) INTERRUPTS Interrupts occur by seventeen sources: eight external, eight inter- nal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the cor- responding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation Upon acceptance of an interrupt the following operations are auto- matically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vec- tor table into the program counter. ■ Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”.

• When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control regsiter (address 34 16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit or the interrupt source select bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Table 7 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT 1 input At completion of serial I/O data reception At completion of serial I/O trans- mit shift or when transmission buffer is empty Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR CNTR 1 Timer 1 INT2 INT3 Key input (Key-on wake-up) ADT A-D conversion BRK instruction FFFD FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT 3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input At completion of A-D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (Valid at falling) Valid when ADT interrupt is se- lected, External interrupt (Valid at falling) Valid when A-D interrupt is se- lected Non-maskable software interrupt

Rev.1.20 Dec 24, 2003 page 20 of 57 3822 Group (A ver.) Fig. 15 Interrupt control Fig. 16 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request b7 b0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit Not used (return “0” when read) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : Falling edge active 1 : Rising edge active b7 b0 b7 b0 b7 b0 b7 b0

Rev.1.20 Dec 24, 2003 page 21 of 57 3822 Group (A ver.) Key Input Interrupt (Key-on wake-up) A Key-on wake-up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is gener1ated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P2 0–P2 3. Fig. 17 Connection example when using key input interrupt and port P2 block diagram P o r t P XX L l e v e l o u t p u t P o r t P 27 d i r e c t i o n r e g i s t e r P 27 o u t p u t P 26 o u t p u t P U L L r e g i s t e r A b i t 2 = “ 1 ” P 25 o u t p u t P 24 o u t p u t P 23 i n p u t P o r t P 26 l a t c h P o r t P 25 l a t c h P o r t P 24 l a t c h P o r t P 23 l a t c h P o r t P 27 l a t c h P o r t P 25 d i r e c t i o n r e g i s t e r P o r t P 24 d i r e c t i o n r e g i s t e r P o r t P 23 d i r e c t i o n r e g i s t e r P 22 i n p u t P 21 i n p u t P 20 i n p u t P o r t P 22 l a t c h P o r t P 21 l a t c h P o r t P 20 l a t c h P o r t P 22 d i r e c t i o n r e g i s t e r P o r t P 21 d i r e c t i o n r e g i s t e r P o r t P 20 d i r e c t i o n r e g i s t e r P o r t P 2 I n p u t r e a d i n g c i r c u i t P c h a n n e l t r a n s i s t o r f o r p u l l u p C M O S o u t p u t b u f f e r K e y i n p u t i n t e r r u p t r e q u e s t P o r t P 26 d i r e c t i o n r e g i s t e r ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽ ✽ ✽ ✽ ✽

Rev.1.20 Dec 24, 2003 page 22 of 57 3822 Group (A ver.) TIMERS The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Fig. 18 Timer block diagram C N T R 0 a c t i v e e d g e s w i t c h b i t T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t R e a l t i m e p o r t c o n t r o l b i t “ 1 ” P 55/ C N T R 1 “ 0 ” f XI N ) f XC I N ) i n l o w s p e e d m o d e✽) C N T R 1 a c t i v e e d g e s w i t c h b i t “ 1 0 ” T i m e r Y s t o p c o n t r o l b i t F a l l i n g e d g e d e t e c t i o n P e r i o d m e a s u r e m e n t m o d e T i m e r Y i n t e r r u p t r e q u e s t P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e R i s i n g e d g e d e t e c t i o n T i m e r Y o p e r a t i n g m o d e b i t s T i m e r X i n t e r r u p t r e q u e s t T i m e r X m o d e r e g i s t e r w r i t e s i g n a l P 54/ C N T R 0 Q Q T S P 54 d i r e c t i o n r e g i s t e r P u l s e o u t p u t m o d e P 54 l a t c h T i m e r X s t o p c o n t r o l b i t “ 0 ” “ 1 ” T i m e r X w r i t e c o n t r o l b i t Q D L a t c h Q D L a t c h “ 1 ” “ 0 ” “ 1 ” “ 1 0 ” T i m e r X o p e r a t i n g m o d e b i t s f ( XI N ) / 1 6 f XI N ) i n l o w s p e e d m o d e✽) P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t P u l s e o u t p u t m o d e Q Q T S “ 0 ” P 56 d i r e c t i o n r e g i s t e r P 56 l a t c h“ 1 ” TO U T o u t p u t a c t i v e e d g e s w i t c h b i t T i m e r 2 w r i t e c o n t r o l b i t “ 0 ” “ 1 ” TO U T o u t p u t c o n t r o l b i t “ 1 ” P 56/ TO U T XC I N T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t “ 0 ” “ 1 ” T i m e r 2 i n t e r r u p t r e q u e s t T i m e r 3 i n t e r r u p t r e q u e s t T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 1 i n t e r r u p t r e q u e s t D a t a b u s f ( XI N ) / 1 6 f XC I N ) i n l o w s p e e d m o d e]) f XI N ) f XC I N ) i n l o w s p e e d m o d e✽) f XI N ) f XC I N ) i n l o w s p e e d m o d e✽) C N T R 0 i n t e r r u p t r e q u e s t C N T R 1 i n t e r r u p t r e q u e s t T i m e r Y o p e r a t i n g m o d e b i t s “ 1 1 ” R e a l t i m e p o r t c o n t r o l b i t P 52 l a t c h R e a l t i m e p o r t c o n t r o l b i t P 53 l a t c h T i m e r Y l o w ) T i m e r Y h i g h T i m e r 3 l a t c h ( 8 ) T i m e r 3 ( 8 ) T i m e r 1 l a t c h ( 8 ) T i m e r 1 ( 8 ) T i m e r 2 l a t c h ( 8 ) T i m e r 2 ( 8 ) T i m e r X l o w ) T i m e r X h i g h T i m e r X l o w l a t c h ) T i m e r X h i g h l a t c h T i m e r Y l o w l a t c h ) T i m e r Y h i g h l a t c h TO U T o u t p u t c o n t r o l b i t “ 0 ” “ 0 ” “ 0 ” P 52 P 53 P 52 d i r e c t i o n r e g i s t e r P 53 d i r e c t i o n r e g i s t e r P 52 d a t a f o r r e a l t i m e p o r t P 53 d a t a f o r r e a l t i m e p o r t ✽ I n t e r n a l c l o c k φ = XC I N

Rev.1.20 Dec 24, 2003 page 23 of 57 3822 Group (A ver.) Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P54 direction register to input mode. (4) Pulse Width Measurement Mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode. G Timer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, when writing in the timer latch at the timer underflow, the value is set in the timer and the latch at one time. Additionally, unexpected value may be set in the high-or- der counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. G Real time port control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from “0” to “1”, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. I Note on CNTR 0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. Fig. 19 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d c o u n t e r W r i t e v a l u e i n l a t c h o n l y R e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t f u n c t i o n i n v a l i d R e a l t i m e p o r t f u n c t i o n v a l i d P d a t a f o r r e a l t i m e p o r t P d a t a f o r r e a l t i m e p o r t T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b 7 b 0

Rev.1.20 Dec 24, 2003 page 24 of 57 3822 Group (A ver.) Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period Measurement Mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Ex- cept for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. (4) Pulse Width HL Continuously Measurement Mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 5 direction register to input mode. I Note on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 20 Structure of timer Y mode register T i m e r Y m o d e r e g i s t e r T Y M a d d r e s s b 7 b 0 N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) T i m e r Y o p e r a t i n g m o d e b i t s b b T i m e r m o d e P e r i o d m e a s u r e m e n t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e C N T R 1 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t T i m e r Y s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p

Rev.1.20 Dec 24, 2003 page 25 of 57 3822 Group (A ver.) Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvertent count down of the timer, rewrite the value of timer whenever the count source is changed. G Timer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. G Timer 2 output control When the timer 2 (T OUT ) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output mode. I Notes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 21 Structure of timer 123 mode register TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T o u t p u t c o n t r o l b i t TO U T o u t p u t d i s a b l e d TO U T o u t p u t e n a b l e d T i m e r w r i t e c o n t r o l b i t W r i t e d a t a i n l a t c h a n d c o u n t e r W r i t e d a t a i n l a t c h o n l y T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e f XC I N ) N o t u s e d r e t u r n w h e n r e a d T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s N o t e : I n t e r n a l c l o c k φ i s f ( XC I N ) / 2 i n t h e l o w - s p e e d m o d e . b 7 b 0

Rev.1.20 Dec 24, 2003 page 26 of 57 3822 Group (A ver.) SERIAL I/O Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Fig. 22 Block diagram of clock synchronous serial I/O Fig. 23 Operation of clock synchronous serial I/O function P 46/ SC L K P 47/ SR D Y P 44/ R XD P 45/ TXD f ( XI N ) 1 / 4 F / F S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) C l o c k c o n t r o l c i r c u i t S h i f t c l o c k S e r i a l I / O c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n B a u d r a t e g e n e r a t o r A d d r e s s 0 0 1 C 1 B R G c o u n t s o u r c e s e l e c t i o n b i t C l o c k c o n t r o l c i r c u i tF a l l i n g e d g e d e t e c t o r D a t a b u s A d d r e s s 0 0 1 81 S h i f t c l o c k T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t A d d r e s s 0 0 1 91 D a t a b u s A d d r e s s 0 0 1 A1 T r a n s m i t b u f f e r r e g i s t e r T r a n s m i t s h i f t r e g i s t e r ( f ( XC I N ) i n l o w - s p e e d m o d e ) R e c e i v e e n a b l e s i g n a l SR D Y D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 R B F = 1 T S C T B E = 0 T B E = 1 T S C T r a n s f e r s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k S e r i a l o u t p u t TXD S e r i a l i n p u t R XD W r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s O v e r r u n e r r o r ( O E ) d e t e c t i o n N o t e s 1 : T h e t r a n s m i t i n t e r r u p t ( T I ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( T B E = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e TXD p i n T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6

Rev.1.20 Dec 24, 2003 page 27 of 57 3822 Group (A ver.) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 24 Block diagram of UART serial I/O Fig. 25 Operation of UART serial I/O function f ( XI N ) O E P E F E 1 / 1 6 1 / 1 6 D a t a b u s R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) B a u d r a t e g e n e r a t o r F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) A d d r e s s 0 0 1 C 1 S T S P P A g e n e r a t o r T r a n s m i t b u f f e r r e g i s t e r D a t a b u s T r a n s m i t s h i f t r e g i s t e r A d d r e s s 0 0 1 81 T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) A d d r e s s 0 0 1 91 S T d e t e c t o r S P d e t e c t o r U A R T c o n t r o l r e g i s t e r A d d r e s s 0 0 1 B1 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t S e r i a l I / O s y n c h r o n o u s c l o c k s e l e c t i o n b i t C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s S e r i a l I O c o n t r o l r e g i s t e r P 46/ SC L K S e r i a l I / O s t a t u s r e g i s t e r P 44/ R XD P 45/ TXD ( f ( XC I N ) i n l o w - s p e e d m o d e ) T S C = 0 T B E R B F = 0 T B E = 0 T B E = 0 R B F = 1 R B F = 1 S TD 0 D 1 S P D 0 D 1S T S P T B E = 1 T S C S TD 0 D 1 S P D 0 D 1S T S P T r a n s m i t b u f f e r w r i t e s i g n a l ✽ G e n e r a t e d a t n d b i t i n s t o p b i t m o d e 1 s t a r t b i t o r d a t a b i t s o r p a r i t y b i t o r s t o p b i t s 1 :E r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e R B F f l a g b e c o m e s “ 1 ” ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . h e t r a n s m i t i n t e r r u p t T I c a n b e s e l e c t e d t o o c c u r w h e n e i t h e r t h e T B E o r T S C f l a g b e c o m e s b y t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r : T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e R B F f l a g b e c o m e s : A f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t o c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o T S C N o t e s S e r i a l o u t p u t TXD S e r i a l i n p u t R XD R e c e i v e b u f f e r r e a d s i g n a l T r a n s m i t o r r e c e i v e c l o c k

Rev.1.20 Dec 24, 2003 page 28 of 57 3822 Group (A ver.) [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a charac- ter bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O Status Register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE. Writ- ing “0” to the serial I/O enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIOCON)] 001A16 The serial I/O control register contains eight control bits for the se- rial I/O function. [UART Control Register (UARTCON) ]001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. I Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

Rev.1.20 Dec 24, 2003 page 29 of 57 3822 Group (A ver.) Fig. 26 Structure of serial I/O control registers B R G c o u n t s o u r c e s e l e c t i o n b i t ( C S S ) f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e S e r i a l I O s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n i z e d s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n i z e d s e r i a l I O i s s e l e c t e d E x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s o r d i n a r y I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M A s y n c h r o n o u s s e r i a l I O U A R T C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P 44– P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P 44– P o p e r a t e a s s e r i a l I O p i n s S e r i a l I / O c o n t r o l r e g i s t e r S I O C O N a d d r e s s b 7 b T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I / O s t a t u s r e g i s t e r S I O S T S a d d r e s s b 7 b U A R T c o n t r o l r e g i s t e r U A R T C O N a d d r e s s C h a r a c t e r l e n g t h s e l e c t i o n b i t ( C H A S ) b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 45/ TXD P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d r e t u r n w h e n r e a d b 7 b

Rev.1.20 Dec 24, 2003 page 30 of 57 3822 Group (A ver.) A-D CONVERTER [A-D Conversion Register (AD)] 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AV SS and VREF by 256, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P67/AN7–P6 0/ AN 0, and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to at least 500 kHz during A-D conversion. Use the clock divided from the main clock XIN as the internal clock φ. Fig. 28 A-D converter block diagram Fig. 27 Structure of A-D control register A - D c o n t r o l r e g i s t e r A D C O N a d d r e s s A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d A n a l o g i n p u t p i n s e l e c t i o n b i t s P 60/ A N 0 P 61/ A N 1 P 62/ A N 2 P 63/ A N 3 P 64/ A N 4 P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 VR E F i n p u t s w i t c h b i t O N d u r i n g c o n v e r s i o n A l w a y s O N A D e x t e r n a l t r i g g e r v a l i d b i t A D e x t e r n a l t r i g g e r i n v a l i d A D e x t e r n a l t r i g g e r v a l i d b 7 b 0 I n t e r r u p t s o u r c e s e l e c t i o n b i t I n t e r r u p t r e q u e s t a t A D c o n v e r s i o n c o m p l e t e d I n t e r r u p t r e q u e s t a t A D T i n p u t f a l l i n g N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) C o m p a r a t o r A - D c o n t r o l c i r c u i t A D T / A - D i n t e r r u p t r e q u e s t A VS S VR E F P 60/ A N 0 D a t a b u s A - D c o n t r o l r e g i s t e r b 7 b 0 A - D c o n v e r s i o n r e g i s t e r R e s i s t o r l a d d e r C h a n n e l s e l e c t o r P 67/ A N 7 P 66/ A N 6 P 65/ A N 5 P 64/ A N 4 P 63/ A N 3 P 62/ A N 2 P 61/ A N 1 P 57/ A D T

Rev.1.20 Dec 24, 2003 page 31 of 57 3822 Group (A ver.) LCD DRIVE CONTROL CIRCUIT The 3822 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. G LCD display RAM G Segment output enable register G LCD mode register G Selector G Timing controller G Common driver G Segment driver G Bias control circuit A maximum of 32 segment output pins and 4 common output pins can be used. Up to 128 pixels can be controlled for LCD display. When the LCD Fig. 29 Structure of segment output enable register and LCD mode register enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 8 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixel 64 dots or 8 segment LCD 8 digits 96 dots or 8 segment LCD 12 digits 128 dots or 8 segment LCD 16 digits L C D m o d e r e g i s t e r L M a d d r e s s S e g m e n t o u t p u t e n a b l e r e g i s t e r S E G a d d r e s s D u t y r a t i o s e l e c t i o n b i t s N o t u s e d u s e C O M 0, C O M 1) u s e C O M 0– C O M 2) u s e C O M 0– C O M 3) B i a s c o n t r o l b i t b i a s b i a s L C D e n a b l e b i t L C D O F F L C D O N N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s C l o c k i n p u t d i v i s i o n o f c l o c k i n p u t d i v i s i o n o f c l o c k i n p u t d i v i s i o n o f c l o c k i n p u t L C D C K c o u n t s o u r c e s e l e c t i o n b i t N o t e f XC I N ) f XI N ) o r f XC I N ) i n l o w s p e e d m o d e N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r . S e g m e n t o u t p u t e n a b l e b i t 0 I n p u t p o r t P 34– P S e g m e n t o u t p u t S E G 1 S E G 1 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P 00, P S e g m e n t o u t p u t S E G 1 S E G 1 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P 02– P S e g m e n t o u t p u t S E G 1 S E G 2 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P 10, P S e g m e n t o u t p u t S E G 2 S E G 2 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P S e g m e n t o u t p u t S E G 2 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P 13– P S e g m e n t o u t p u t S E G 2 S E G 3 N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t b 7 b 0 b 7 b 0

Rev.1.20 Dec 24, 2003 page 32 of 57 3822 Group (A ver.) Fig. 30 Block diagram of LCD controller/driver C O M C O M C O M C O M V S S V L V L V L S E G S E G S E G S E G L C D C K P 17/ S E G P 16/ S E G P 34/ S E G f ( X C I f ( X I o r f X C I i n l o w s p e e d m o d e D a t a b u s A d d r e s s 0 0 A d d r e s s 0 0 A d d r e s s 0 0 F S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l L C D d i v i d e r T i m i n g c o n t r o l l e r C o m m o n d r i v e r D u t y r a t i o s e l e c t i o n b i t s C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r B i a s c o n t r o l b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D d i s p l a y R A M L C D e n a b l e b i t

Rev.1.20 Dec 24, 2003 page 33 of 57 3822 Group (A ver.) Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–V L3), apply the voltage shown in Table 9 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Common Pin and Duty Ratio Control The common pins (COM 0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). Fig. 31 Example of circuit at each bias Table 10 Duty ratio control and common pins used Duty ratio Common pins used Notes1: COM 2 and COM 3 are open. 2: COM 3 is open. Bit 1 Bit 0 COM 0, COM 1 (Note 1) Duty ratio selection bit COM 0–COM 2 (Note 2) COM 0–COM 3 Table 9 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias Voltage value VL3=V LCD VL2=2/3 VLCD VL1=1/3 VLCD Note 1: V LCD is the maximum value of supplied voltage for the LCD panel. 1/2 bias VL3=V LCD VL2=V L1=1/2 VLCD C o n t r a s t c o n t r o l b i a b i a s C o n t r a s t c o n t r o l VL R R R R R R R R R R VL VL VL VL VL

Rev.1.20 Dec 24, 2003 page 34 of 57 3822 Group (A ver.) LCD Display RAM Address 004016 to 004F16 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. Fig. 32 LCD display RAM map LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the following equation; f(LCDCK) = Frame frequency = (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) B i t A d d r e s s C 1 D 1 C O M 3 0123456 C O M 0C O M 1 C O M 2 C O M 3 C O M 0C O M 1C O M 2 S E G 1 S E G 3 S E G 5 S E G 7 S E G 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 0 S E G 2 S E G 4 S E G 6 S E G 8 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3

Rev.1.20 Dec 24, 2003 page 35 of 57 3822 Group (A ver.) Fig. 33 LCD drive waveform (1/2 bias) I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VL 2= VL VS S VL VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F F O N O F F O N C O M 3 C O M 2 C O M 1 C O M 0 C O M 3 C O M 2 C O M 1 C O M 0 1 / 3 d u t y VL VL 2= VL VS S VL VS S O F FO N O N O F F O N O F F 1 / 2 d u t y C O M 0 C O M 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 VL VL 2= VL VS S VL VS S O F FO N O F FO N O F FO N O F FO N C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.1.20 Dec 24, 2003 page 36 of 57 3822 Group (A ver.) Fig. 34 LCD drive waveform (1/3 bias) I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F F O N O F F O N C O M 3 C O M 2 C O M 1 C O M 0 C O M 3 C O M 2 C O M 1 C O M 0 1 / 3 d u t y O F FO N O N O F F O N O F F 1 / 2 d u t y C O M 0 C O M 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 O F FO N O F FO N O F FO N O F FO N VL VL VS S VL VL VL VS S VL VL VS S VL VL VS S VL VL VS S C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.1.20 Dec 24, 2003 page 37 of 57 3822 Group (A ver.) φφφφφ CLOCK SYSTEM OUTPUT FUNCTION The internal system clock φ can be output from port P41 by setting the φ output control register. Set bit 1 of the port P4 direction reg- ister to “1” when outputting φ clock. Fig. 35 Structure of φφφφφ output control register φ o u t p u t c o n t r o l r e g i s t e r C K O U T a d d r e s s φ o u t p u t c o n t r o l b i t p o r t f u n c t i o n φ c l o c k o u t p u t N o t u s e d r e t u r n w h e n r e a d b 7 b 0

Rev.1.20 Dec 24, 2003 page 38 of 57 3822 Group (A ver.) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between V CC (min.) and

5.5 V, and the quartz-crystal oscillator should be stable), reset is

released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and ad- dress FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). Fig. 36 Reset Circuit Example Fig. 37 Reset Sequence P o w e r o n P o w e r s o u r c e v o l t a g e R e s e t i n p u t v o l t a g e P o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t VI L s p e c . 0 V 0 V VC CR E S E T VC CR E S E T R E S E T I n t e r n a l r e s e t A d d r e s s D a t a S Y N C φ XI N XI N a b o u t 8 0 0 0 c y c l e s R e s e t a d d r e s s f r o m v e c t o r t a b l e N o t e s 1 : T h e f r e q u e n c y r e l a t i o n o f f ( XI N ) a n d f (φ) i s f ( XI N ) = 8 • f (φ) T h e q u e s t i o n m a r k s i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e F F F C F F F D A D H A D L A D L A D H ? ? ? ?

Rev.1.20 Dec 24, 2003 page 39 of 57 3822 Group (A ver.) Fig. 38 Initial status of microcomputer after reset P o r t P 0 d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P U L L r e g i s t e r A P U L L r e g i s t e r B S i r i a l I O s t a t u s r e g i s t e r S i r i a l I O c o n t r o l r e g i s t e r U A R T c o n t r o l r e g i s t e r T i m e r X L o w T i m e r X H i g h T i m e r Y L o w T i m e r Y H i g h T i m e r T i m e r T i m e r T i m e r X m o d e r e g i s t e r T i m e r Y m o d e r e g i s t e r T i m e r m o d e r e g i s t e r φ o u t p u t c o n t r o l r e g i s t e r A D c o n t r o l r e g i s t e r S e g m e n t o u t p u t e n a b l e r e g i s t e r L C D m o d e r e g i s t e r I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r C P U m o d e r e g i s t e r I n t e r r u p t r e q u e s t r e g i s t e r I n t e r r u p t r e q u e s t r e g i s t e r I n t e r r u p t c o n t r o l r e g i s t e r I n t e r r u p t c o n t r o l r e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r P r o g r a m c o u n t e r N o t e : T h e c o n t e n t s o f a l l o t h e r r e g i s t e r s a n d R A M a r e u n d e f i n e d a f t e r r e s e t , s o t h e y m u s t b e i n i t i a l i z e d b y s o f t w a r e ✕ : u n d e f i n e d R e g i s t e r C o n t e n t sA d d r e s s 0 01 F F F F F F C o n t e n t s o f a d d r e s s F F F D 1 C o n t e n t s o f a d d r e s s F F F C 1 ( 1 ) 0 0 0 11 D 1 C 1 D 1 P S P C H ) P C L) 0 1 0 0 1 0 00 0 0 0 0 1 0 00 1 1 1 0 0 0 00 1 0 0 0 0 0 00 0 0 0 0 1 1 10

Rev.1.20 Dec 24, 2003 page 40 of 57 3822 Group (A ver.) CLOCK GENERATING CIRCUIT The 3822 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No exter- nal resistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed Mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed Mode The internal clock φ is half the frequency of XIN. (3) Low-speed Mode G The internal clock φ is half the frequency of XCIN. G A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscil- lation to stabilize by programming. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, es- pecially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(X IN) > 3f(XCIN). Fig. 39 Ceramic resonator circuit example Fig. 40 External clock input circuit Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be- fore executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows timer for the clock circuit oscillation to stabilize. (2) Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state be- fore the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XI N E x t e r n a l o s c i l l a t i o n c i r c u i t O p e n VC C VS S C C I N C C O U T R f R d XC I N XC O U T XO U T XCIN XCOUT XIN XOUT C IN C OU TC CIN C COUT Rf Rd

Rev.1.20 Dec 24, 2003 page 41 of 57 3822 Group (A ver.) Fig.41 Clock generating circuit block diagram W I T i n s t r u c t i o n S T P i n s t r u c t i o n T i m i n g φ I n t e r n a l s y s t e m c l o c k S R Q S T P i n s t r u c t i o n S R Q M a i n c l o c k s t o p b i t S R Q T i m e r 2T i m e r 1 1 / 2 1 / 4 XI N XO U T XC O U TXC I N I n t e r r u p t r e q u e s t R e s e t P o r t XC s w i t c h b i t “ 1 ” “ 0 ” T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t L o w - s p e e d m o d e M i d d l e - / H i g h - s p e e d m o d e I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t N o t e M i d d l e - s p e e d m o d e H i g h - s p e e d m o d e o r L o w s p e e d m o d e N o t e : W h e n u s i n g t h e l o w - s p e e d m o d e , s e t t h e p o r t XC s w i t c h b i t t o “ 1 ” . M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t “ 1 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” “ 0 ” I n t e r r u p t d i s a b l e f l a g I “ 1 ” “ 0 ”

Rev.1.20 Dec 24, 2003 page 42 of 57 3822 Group (A ver.) Fig. 42 State transitions of system clock N o t e s 1 : S w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( D o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) T h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d T i m e r a n d L C D o p e r a t e i n t h e w a i t m o d e W h e n t h e s t o p m o d e i s e n d e d a d e l a y o f a p p r o x i m a t e l y m s o c c u r s a u t o m a t i c a l l y b y t i m e r a n d t i m e r i n m i d d l e h i g h s p e e d m o d e W h e n t h e s t o p m o d e i s e n d e d a d e l a y o f a p p r o x i m a t e l y s o c c u r s a u t o m a t i c a l l y b y t i m e r a n d t i m e r i n l o w s p e e d m o d e W a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k XI N b e f o r e t h e s w i t c h i n g f r o m t h e l o w s p e e d m o d e t o m i d d l e h i g h s p e e d m o d e T h e e x a m p l e a s s u m e s t h a t M H z i s b e i n g a p p l i e d t o t h e XI N p i n a n d k H z t o t h e XC I N p i n φ i n d i c a t e s t h e i n t e r n a l c l o c k C M 4 : P o r t X c s w i t c h b i t I O p o r t XC I N , XC O U T C M 5 M a i n c l o c k XI N – XO U s t o p b i t O s c i l l a t i n g S t o p p e d C M 6 M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t f XI N ) h i g h s p e e d m o d e f XI N ) m i d d l e s p e e d m o d e C M 7 I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t XI N – XO U T s e l e c t e d m i d d l e h i g h s p e e d m o d e XC I N – XC O U T s e l e c t e d l o w s p e e d m o d e C P U m o d e r e g i s t e r C P U M a d d r e s s b 7 b 4 R e s e t C M 6 “ 0 ”“ 1 ” C M 4 0 ”“ 1 ” C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d M i d d l e - s p e e d m o d e ( f (φ) = 1 M H z ) C M 7 M H z s e l e c t e d C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g M i d d l e s p e e d m o d e f (φ) M H z C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d H i g h - s p e e d m o d e ( f (φ) = 4 M H z ) C M 7 M H z s e l e c t e d C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g H i g h s p e e d m o d e f (φ) M H z C M 7 k H z s e l e c t e d C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g L o w s p e e d m o d e f (φ) k H z C M 7 k H z s e l e c t e d C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g L o w s p e e d m o d e f (φ) k H z C M 7 k H z s e l e c t e d C M 6 M i d d l e s p e e d C M 5 M H z s t o p p e d C M 4 k H z o s c i l l a t i n g L o w s p e e d m o d e f (φ) k H z C M 7= k H z s e l e c t e d C M 6= H i g h s p e e d C M 5= M H z s t o p p e d C M 4= k H z o s c i l l a t i n g L o w s p e e d m o d e f (φ) k H z C M 0 ” 1 ” C M 0 ” 1 ” C M 0 ” 1 ” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M C M6 “ 0 ” 1 ” 0 ” 1 ” C M C M “ 0 C M C M6 “ 0 ” 1 ” 0 ” 1 ” C M C M “ 0

Rev.1.20 Dec 24, 2003 page 43 of 57 3822 Group (A ver.) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the T XD pin after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conver- sion. Do not execute the STP or WIT instruction during an A-D conver- sion. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

Rev.1.20 Dec 24, 2003 page 44 of 57 3822 Group (A ver.) NOTES ON USE Countermeasures against noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). G Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. (2) Connection of bypass capacitor across V SS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. ➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns. G Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscil- lator, the correct clock will not be input in the microcomputer. RESETReset circuit Noise VSSVSS Reset circuit V SS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K. Fig. 44 Wiring for clock I/O pins Fig. 43 Wiring for the RESET pin Fig. 45 Bypass capacitor across the VSS line and the VCC line

Rev.1.20 Dec 24, 2003 page 45 of 57 3822 Group (A ver.) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe- cially when range of votage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. G Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. G Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 47 Wiring for the VPP pin of One Time PROM Fig. 46 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently P40/VPP VSS About 5kΩ (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua- tion for each product of every after confirming product specification. (6) Wiring to V PP pin of One Time PROM version Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the VSS pin. Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM version, the microcomputer operates correctly. G Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the built-in PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal in- struction codes or data are read from the built-in PROM, which may cause a program runaway. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufac- turing processes. When manufacturing an application system with the One TIme PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. XIN XOUT VSS Microcomputer M utual inductance Large current GND M XIN XOUT VSS CNTRDo not cross N.G.

Rev.1.20 Dec 24, 2003 page 46 of 57 3822 Group (A ver.) DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1.Mask ROM Order Confirmation Form 2.Mark Specification Form✽ 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk ✽For the mask ROM confirmation and the mark specifications, re- fer to the “Renesas Technology” Homepage (http:// www.renesas.com/en/rom/).

Rev.1.20 Dec 24, 2003 page 47 of 57 3822 Group (A ver.) VO VO Pd Topr Tstg –0.3 to 6.5 VPower source voltage Input voltage P0 0–P07, P10–P17, P20–P27, P34–P37, P40–P47, P50–P57 P60–P67, P70, P71 VCC VI Symbol Parameter Conditions Ratings Unit All voltages are based on V SS. Output transistors are cut off. VI VI VI VI VO VO VO Input voltage V L1 Input voltage V L2 Input voltage V L3 Input voltage RESET, X IN Output voltage P0 0–P07, P10–P17 Output voltage P3 4–P37 Output voltage P2 0–P27, P41–P47,P50–P57, P60–P67, P70, P71 Output voltage SEG 0–SEG11 Output voltage X OUT Power dissipation Operating temperature Storage temperature At output port At segment output At segment output –0.3 to V CC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 V V V V V V V V V V V mW Ta = 25°C (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V CC VCC VCC Symbol Parameter Limits Min. V V V V V V V V V V V V V Unit 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ✕ f + 1.3 2.0 AV SS 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Typ. Max. Power source voltage (Note 1) High-speed mode f(X IN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz Middle-speed mode f(X IN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Low-speed mode When oscillation starts ( Note 2) Table 11 Absolute maximum ratings (A version) Table 12 Recommended operating conditions (A version) Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D converter. 2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especiall y high-frequency oscillator will require some conditions of oscillation. f : Means an oscillation frequency (MHz) of an oscillator. If it is 8, substitute 8 for “f”. VSS VREF AVSS VIA Power source voltage A-D conversion reference voltage Analog power source voltage Analog input voltage AN 0–AN7

Rev.1.20 Dec 24, 2003 page 48 of 57 3822 Group (A ver.) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) “H” input voltage P0 0–P0 7, P10–P1 7,P34–P3 7, P40, P41, P45, P47, P52, P53,P56,P60–P6 7,P70,P71 (CM4= 0) “H” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 “H” input voltage RESET “H” input voltage XIN “L” input voltage P00–P07, P10–P17,P34–P3 7, P40, P41, P45, P47, P52, P53, P56,P60–P6 7,P70,P71 (CM4= 0) “L” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 “L” input voltage RESET “L” input voltage X IN VCC VCC VCC VCC

0.3 VCC

0.2 VCC

Min. V V V V V V V V Unit 0.7VCC 0.8VCC 0.8VCC 0.8VCC Typ. Max. Table 13 Recommended operating conditions (A version)

Rev.1.20 Dec 24, 2003 page 49 of 57 3822 Group (A ver.) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7 (Note 2) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 2) P00–P0 7, P10–P1 7 (Note 2) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 2) 0–P0 7, P10–P1 7 (Note 3) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 3) 0–P0 7, P10–P1 7 (Note 3) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 3) –40 –40 –20 –20 CC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the A-D converter is used, refer to the recommended operating condition for A-D converter. 5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 6: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator will require some conditions of oscillation. “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “H” peak output current “H” peak output current ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA Unit Typ. Max. IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) –1.0 –2.5 mA mA mA mA mA mA “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current Input frequency for timers X and Y (duty cycle 50%) I OL(avg) f(CNTR0) f(CNTR1) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz (VCC ≤ 2.0 V) High-speed mode High-speed mode (4.0 V ≤ V CC ≤ 4.5 V) High-speed mode (2.0 V ≤ V CC ≤ 4.0 V) Middle-speed mode (Note 6) Middle-speed mode (Note 6) Middle-speed mode (Note 6) 32.768 Main clock input oscillation frequency (duty cycle 50%) (Note 4) Sub-clock input oscillation frequency (duty cycle 50%) (Notes 5, 6) f(X IN) 2.5 5.0 5.0 2 ✕ VCC – 4 VCC 5 ✕ VCC – 8 10.0 4 ✕ VCC – 8 2 ✕ VCC 10.0 8.0 6.0 Table 14 Recommended operating conditions (A version) f(X CIN)

Rev.1.20 Dec 24, 2003 page 50 of 57 3822 Group (A ver.) IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V VOL IOH = –2.5 mA IOH = –0.6 mA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V VVCC –2.0“H” output voltage P00–P0 7, P10–P1 7 Symbol Parameter Limits Min. Unit 0.5 Typ. Max.Test conditions VOH 2.0 0.5 (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) RESET : VCC = 2.2 V to 5.5 V VI = VCC Pull-downs “off” V CC = 5 V, VI = VCC Pull-downs “on” V CC = 3 V, VI = VCC Pull-downs “on” VI = VCC “H” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P7 “L” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) Hysteresis INT0–INT3, ADT, CNTR0, CNTR 1, P20–P2 7 Hysteresis S CLK , RXD Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P34–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) VOH VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH VCC –2.0 VCC –0.5 6.0 –30 –6.0 0.5 0.5 2.0 0.5 140 5.0 5.0 –5.0 –5.0 –140 –45 V V V V V V V V V IIH IIL VCC –1.0 VCC –1.0 V V V1.0 V1.0 5.0 µA VI = VCC VI = VCC VI = VSS VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” V CC = 3 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS “H” input current RESET “H” input current X IN “L” input current P00–P0 7, P10–P1 7, P34–P3 7,P40 “L” input current 0–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) “L” input current RESET “L” input current X IN 4.0 –5.0 –70 µA µA µA µA µA µA µA µA µA µA µA IIL IIL IIL –25 –4.0 Note:When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. Table 15 Electrical characteristics (A version)

Rev.1.20 Dec 24, 2003 page 51 of 57 3822 Group (A ver.) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) V5.5

• High-speed mode, VCC = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, V CC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC Power source current 5.0 VRAM RAM retention voltage At clock stop mode 1.8 3.0 0.8 5.5 8.0 0.1 6.0 1.6 1.0 mA mA µA µA µA µA µA mA10 Table 16 Electrical characteristics (A version) 4.0 8.0 µA

Rev.1.20 Dec 24, 2003 page 52 of 57 3822 Group (A ver.) (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 10 MHz, in middle/high-speed mode unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.2 V to 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz VCC = VREF < 2.2 V f(XIN) ≤ 12 ✕ VCC – 22 MHz Bits LSB Note:When an internal trigger is used in middle-speed mode, it is 14 µs. µsf(XIN) = 8 MHzConversion time Ladder resistor Reference power source input current tCONV R LADDER IVREF kΩ µA Analog port input currentIIA µA 150VREF = 5 V 12.5 (Note) 100 200 5.0 Table 17 A-D converter characteristics (A version) ±3 LSB

Rev.1.20 Dec 24, 2003 page 53 of 57 3822 Group (A ver.) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Note:When bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). Table 18 Timing requirements 1 (A version) Note:When bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Table 19 Timing requirements 2 (A version) 1000/(4 ✕ VCC –8) 100 1000/(2 ✕ V CC –4) 200 105 105 800 370 370 220 100 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK ) twH(S CLK ) twL(SCLK ) tsu(RX D–S CLK ) th(SCLK –R XD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 125 1000/V CC 1000/(5 ✕ VCC –8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK ) twH(S CLK ) twL(SCLK ) tsu(RX D–S CLK ) th(SCLK –R XD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V

Rev.1.20 Dec 24, 2003 page 54 of 57 3822 Group (A ver.) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time 140 Symbol Parameter Limits Min. ns ns ns ns ns ns Unit tC (SCLK )/2–30 tC (SCLK )/2–30 –30 Typ. Max. twH(S CLK ) twL(SCLK ) td(SCLK –TXD) tv(SCLK –TXD) tr(SCLK ) tf(SCLK ) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) ns ns ns ns ns ns Unit Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time 350 100 100 Symbol Parameter Limits Min. tC (SCLK )/2–100 tC (SCLK )/2–100 –30 Max. twH(S CLK ) twL(SCLK ) td(SCLK –TXD) tv(SCLK –TXD) tr(SCLK ) tf(SCLK ) Typ. Fig. 48 Circuit for measuring output switching characteristics Table 20 Switching characteristics 1 (A version) Table 21 Switching characteristics 2 (A version) M e a s u r e m e n t o u t p u t p i n 1 0 0 p F C M O S o u t p u t N o t e : W h e n b i t 4 o f t h e U A R T c o n t r o l r e g i s t e r a d d r e s s i s N c h a n n e l o p e n d r a i n o u t p u t m o d e N - c h a n n e l o p e n - d r a i n o u t p u t ( N o t e ) 1 kΩ 1 0 0 p F M e a s u r e m e n t o u t p u t p i n

Rev.1.20 Dec 24, 2003 page 55 of 57 3822 Group (A ver.) Fig. 49 Timing diagram tW R E S E T 0 . 8 VC C 0 . 2 VC CR E S E T tC XI N ) tC C N T R tW H C N T R ) tW L C N T R 0 . 8 VC C 0 . 2 VC C C N T R 0, C N T R 1 tW H I N T ) tW L I N T 0 . 8 VC C 0 . 2 VC C I N T0– I N T3 tW H XI N ) tW L XI N ) 0 . 8 VC C 0 . 2 VC C XI N tC SC L tW L SC L K) tW H SC L 0 . 2 VC C 0 . 8 VC CSC L K trtf td SC L TXD ) tv SC L TXD TXD R XD 0 . 2 VC C 0 . 8 VC C ts u R XD SC L K) th SC L R XD

Rev.1.20 Dec 24, 2003 page 56 of 57 3822 Group (A ver.) PACKAGE OUTLINE QFP80-P-1420-0.80 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 80P6N-A Plastic 80pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E HE L y Dimension in Millimeters HD 0.5 ––I2 1.3 ––MD 14.6 ––ME 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.8 20.220.019.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c HE 80 65 HD D MD ME A F A1 A2 L y Recommended Mount Pad Detail F x– – 0 . 2 b x M MMP

Rev.1.20 Dec 24, 2003 page 57 of 57 3822 Group (A ver.) LQFP80-P-1212-0.5 Weight(g) – 0.47 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 80P6Q-A Plastic 80pin 12✕12mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E HE L y Dimension in Millimeters HD 0.225 ––I2 0.9 ––MD 12.4 ––ME 12.4 10°0° 0.1 1.0 0.70.50.3 14.214.013.8 14.214.013.8 0.5 12.112.011.9 12.112.011.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e A F e HD E HE D 21 40 6180 y Lp 0.45 0.6 0.25 0.75 0.08x MD l2 b2 ME e Recommended Mount Pad b x M A1 A2 L Detail F Lp c MMP

REVISION HISTORY 3822 GROUP (A ver.) DATA SHEET Rev. Date Description Page Summary (1/X) 1.0 09/26/02 First edition 1.1 10/10/02 [FEATURES] Power source voltage: f(X IN) = → f(XIN) ≤ Table 1 P0 and P1 Function: 8-bit output port → 8-bit I/O port Fig. 4: M 6 A → M 6 A- Table 6: [Notes] are revised. Fig. 27: The explanation of VREF input switch bit is revised. Table 16: VRAM Limits (Min.) is revised. Table 17: Test conditions of Absolute accuracy are revised. Tables 18, 19: Some parameters are added. 1.20 12/24/03 Fig. 5: “Under development” eliminated. Fig. 39: a resistor is added to X OUT pin and Fig. title is revised. DATA REQUIRED FOR MASK ORDERS: URL is revised. Table 11: Input voltage V L3 is revised Table 17: Test conditions of Absolute accuracy is revised.

Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.