3820

3820_03 RENESAS

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER

740 FAMIL Y / 38000 SERIES

User’s Manual

Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Rev. Rev. No. date

1.0 First Edition 970901

REVISION DESCRIPTION LIST 3820 GROUP USER’S MANUAL (1/1) Revision Description

This user’s manual describes Mitsubishi’s CMOS 8- bit microcomputers 3820 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3820 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “SERIES 740 <SOFTWARE> USER’S MANUAL.” Preface

BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization l CHAPTER 1 HARDWARE This chapter describes features of the microcomputer, operation of each peripheral function and electric characteristics. l CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer, a list of control registers, the masking confirmation forms (mask ROM version), ROM programming confirmation forms (One Time PROM version) and mark specification forms which are to be submitted when ordering. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : 10 : f(XIN)/2 (high-speed mode) 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : : Bit in which nothing is allocated Name Functions At reset RWB b0b1b2b3b4b5b6b7 Values immediately after reset release Bit attributes (Note 1) Processor mode bits Stack page selection bit Fix this bit to “1.” Internal system clock selection bit 00: Single-chip mode 01:10: 11: Not available b1b0 0 : 0 page1 : 1 page 0 : XIN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) : Bit that is not used for control of the corresponding function Notes 1: Values immediately after reset release (Note 2) CPU mode register (CPUM) [Address:3B16] Bits 1 : f(XIN)/8 (middle-speed mode) Main clock division ratio selection bit 1 : StoppedMain clock (XIN–XOUT ) stop bit 0 5 0 : Oscillating Port XC switch bit 0 : I/O port 1 : XCIN, XCOUT 0 : f(XIN)/2 (high-speed mode)

3820 GROUP USER’S MANUALi

CHAPTER 1. HARDWARE Direction Registers (ports P2, P4 Ports P3 and P4 Note on CNTR Note on CNTR Serial I/O1 Control Register (SIO1CON) 001A

3820 GROUP USER’S MANUAL ii

3820 GROUP USER’S MANUALiii

CHAPTER 2. APPLICATION

3820 GROUP USER’S MANUAL

2.10 Reset

2.11.2 Internal clock

φ CHAPTER 3. APPENDIX

3.1 Built-in PROM version

3.2.2 Connection of a bypass capacitor across the V

3.2.4 3-14

3.2.5 Oscillator protection using V

3.4 List of instruction codes

3.6 Mask ROM ordering method

3.7 Mark specification form

3.9 SFR allocation

CHAPTER 1. HARDWARE Fig. 49 I

Fig. 56 IOH –VOH characteristic example of CMOS output port at P-channel drive (P2, P5, P6, P7) ...1-70 CHAPTER 2. APPLICATION Fig. 2.2.15

Fig. 2.3.31

3820 GROUP USER’S MANUAL iv

Fig. 2.6.7 Transmit/receive timing example of serial I/O2 (P5 Fig. 2.9.2 Execution sequence example at restoration by occurrence of INT 0 interrupt request ..2-179 Fig. 2.11.7 Oscillation stabilizing time at reoscillation of X

3820 GROUP USER’S MANUALv

CHAPTER 3. APPENDIX Fig. 3.2.3 Wiring for the V Fig. 3.2.8 V

3820 GROUP USER’S MANUAL i

CHAPTER 1. HARDWARE Table 8 Bias control and applied voltage to V CHAPTER 2. APPLICATION

3820 GROUP USER’S MANUALii

Table 2.6.1 Table 2.7.2 Pin functions by setting the corresponding registers when they are not used as segment output pins ..2-157 CHAPTER 3. APPENDIX

DESCRIPTION

FEATURES

APPLICATIONS

3820 GROUP USER’S MANUAL1-2

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Fig. 1 Pin configuration of M38203M4-XXXFP Package type : 80P6N-A 80-pin plastic-molded QFP The 3820 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3820 group has the LCD drive control circuit and the serial I/ O as additional functions. The various microcomputers in the 3820 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3820 group, re- fer to the section on group expansion. (at 8MHz oscillation frequency)

• Memory size
• Software pull-up/pull-down resistors (Ports P0-P7 except Port P40) (includes key input interrupt)
• LCD drive control circuit
• 2 Clock generating circuit Clock (X (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (at 8MHz oscillation frequency and high-speed selected) (at 8MHz oscillation frequency and middle-speed selected) (Extended operating temperature version: 3.0 V to 5.5 V)
• Power dissipation (at 8 MHz oscillation frequency) (at 32 kHz oscillation frequency, at 3 V power source voltage) (Extended operating temperature version: –40 to 85°C)

Household appliances, consumer electronics, etc. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/φ P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN M38203M4-XXXFP 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 414243444546474849505152535455565758596061626364 M38203M4-XXXFP

1-33820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Fig. 2 Pin configuration of M38203M4-XXXGP/ HP Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/f P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN 11 12 13 14 15 16 17 18 19 20 4142434445464748495051525354555657585960 M38203M4-XXXGP M38203M4-XXXHP 123456789 1 0

3820 GROUP USER’S MANUAL1-4

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 3 Functional block diagram FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A) FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A) INT2 CNTR 0,CNTR 1 TOUT CPU A X Y S PC H PC L PS ROM P0(8)P7(2) 27 73 32 28 29 9 10 28 29 SI/O1(8) VL1 VL2 VL3 COM 0 COM 1 COM 2 COM 3 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 XCIN XCOUT 30 31 49 50 51 52 53 54 55 56 P1(8) 41 42 43 44 45 46 47 48 P2(8) 33 34 35 36 37 38 39 40 P4(8) 21 22 23 24 25 2619 20 P5(8) 12 13 14 15 16 17 1811 f LCD drive control circuit RAM LCD display RAM (20 bytes) Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8) Data bus Clock generating circuit Clock input X IN Clock output X OUT XCOUT Sub- clock output X CIN Sub- clock input V CC VSS Reset input (5V) (0V) RESET I/O port P7 P6(2) I/O port P6 Watchdog timer P3(8) 57 58 59 60 61 62 63 64 P0(8) I/O port P0I/O port P1 Key-on wake up I/O port P2 Real time port function Input port P3 f I/O port P4 INT0,INT1 SI/O2(8) I/O port P5 SEG 12 SEG 13 SEG 14 SEG 15 RESET RTP 0,RTP1

• Apply voltage of 2.5 V to 5.5 V to VCC , and 0 V to VSS . (Extended operating temperature version : 3.0 V to 5.5 V)
• Reset input pin for active “L ”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This clock is used as the oscillating source of system clock.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
• Input 0 – VL3 voltage to LCD
• LCD common output pins
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each port to be individually programmed as either input or output.
• Pull-down control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each port to be individually programmed as either input or output.
• Pull-down control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit Input port
• CMOS compatible input level
• Pull-down control is enabled.
• 1-bit input pin
• CMOS compatible input level
• 7-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled. Pin V CC VSS RESET XIN XOUT VL1 – VL3 COM 0 – COM 3 SEG 0 – SEG15 P00/SEG 24 – P07/SEG 31 P10/SEG 32 – P17/SEG 39 P20 – P27 P30/SEG 16 – P37/SEG 23 P40 P41/ φ P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1

Table 1. Pin description (1)

• LCD segment pins
• Key input (key-on wake up) interrupt input pins
• LCD segment pins
• φ clock output pin
• Interrupt input pins
• Serial I/O1 function pins

3820 GROUP USER’S MANUAL1-6

• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled. Pin 0/SIN2, P51/SOUT2 , P52/SCLK2 , P53/SRDY2 P54/CNTR 0, P55/CNTR 1 P56/TOUT P57/INT2 P60/INT3/RTP0 P61/RTP1 P70/XCOUT, P71/XCIN

Table 2. Pin description (2)

• Serial I/O2 function pins
• Timer function pins
• Timer output pin
• Interrupt input pin
• Interrupt input pins(P6
• Real time port function pin
• Sub-clock generating circuit input pins (Connect a resonator. External clock cannot be used.)

1-73820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 4 Part numbering PART NUMBERING M3820 3 M 4 - XXX FPProduct ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M E : Mask ROM version : EPROM or One Time PROM version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes Package type FP GP HP FS ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character – : standard D : Extended operating temperature version : 80P6N-A package : 80P6S-A package : 80P6D-A package : 80D0 package

3820 GROUP USER’S MANUAL1-8

Currently supported products are listed below. Table 3. List of supported products (1) As of April 1995 Products under development: the development schedule and specification may be revised without notice.

Currently supported products are listed below. Table 4. List of supported products (2) Products under development: the development schedule and specification may be revised without notice.

3820 GROUP USER’S MANUAL1-10

Currently supported products are listed below. Table 5. List of supported products (3) Products under development: the development schedule and specification may be revised without notice.

1-113820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3820 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP , WIT, MUL, and DIV instruction can be used. CPU Mode Register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. Fig. 8 Structure of CPU mode register CPU mode register (CPUM (CM) : address 003B16) 7 0 Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Port X C switch bit 0 : I/O port 1 : XCIN, XCOUT Main clock ( XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(X IN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : X IN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)

3820 GROUP USER’S MANUAL1-12

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 4096 8192 12288 16384 20480 24576 28672 32768 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 YYYY 16 ZZZZ 16 RAM ROM 005416 Reserved area SFR area Not used Interrupt vector area ROM area Reserved ROM area (128 bytes) Zero page Special page RAM area RAM size (bytes) Address XXXX 16 ROM size (bytes) Address YYYY 16 LCD display RAM area Address ZZZZ 16 Reserved ROM area

1-133820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 10 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) Timer 3 (T3) Timer X mode register (TXM) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X (low-order) (TXL) Timer Y (low-order) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high-order) (TXH) Timer Y (high-order) (TYH) PULL register A (PULLA) PULL register B (PULLB) Timer Y mode register (TYM) Timer 123 mode register (T123M) f output control register (CKOUT) Segment output enable register (SEG) LCD mode register (LM)

3820 GROUP USER’S MANUAL1-14

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers (ports P2, P41–P4 7, and P5–P7) The 3820 group has 43 programmable I/O pins arranged in seven I/O ports (ports P0–P2 and P4–P7). The I/O ports P2, P41–P4 7, and P5–P7 have direction registers which determine the input/out- put direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the in- put /output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port be- comes an input port. When “1” is written to that port, that port be- comes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports except for port P40 can control ei- ther pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Fig. 11 Structure of PULL register A and PULL register B PULL register A (PULLA : address 001616) 0 : No pull-up (no pull-down) 1 : Pull-up (pull-down) Note : For ports set for the output mode, pull-up or pull-down is impossible. PULL register B (PULLB : address 001716) P00–P07 pull-down P10–P17 pull-down P20–P27 pull-up P30–P37 pull-down P70, P71 pull-up Not used (return "0" when read) P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60, P61 pull-up Not used (return "0" when read)

Table 6. I/O ports functions Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

3820 GROUP USER’S MANUAL1-16

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER Fig. 12 Port block diagram (1) (3)Ports P30–P37 VL2/VL3 VL1/VSS (1)Ports P0,P1 Segment output enable bit VL2/VL3 VL1/VSS (Note) (5)Port P41 Data bus Pull-down control Segment output enable bit Data bus Direction register Port latch Pull-down control Segment output enable bit Note. Bit 0 of port P0 direction register and port P1 direction register. output control bit Direction register Pull-up control Data bus Port latch Direction register Pull-up control Data bus Port latch Direction register Pull-up control Data bus Port latch (7)Port P45 Serial I/O1 output Serial I/O1 enable bit Transmission enable bit VL2/VL3 P45/TXD P-channel output disable bit (6)Port P44 (4)Port P40 (2)Ports P2,P42,P43,P57 Direction register Direction register Data bus Port latch Pull-up control Key input (Key-on wake up) interrupt input INT0–INT2 interrupt input Pull-up control Reception enable bit Serial I/O1 enable bit Serial I/O1 input Data bus Port latch Data bus (8)Port P46 Serial I/O1 clock input Direction register Pull-up control Data bus Port latch Serial I/O1 clock output Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 synchronization clock selection bit Serial I/O1 enable bit

1-173820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 output Direction register Port latchData bus Pull-up control Serial I/O1 ready output (11) Port P51 (9) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Port latchData bus Pull-up control SRDY1 output enable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Port latchData bus Pull-up control SRDY2 output enable bit Direction register Port latchData bus Pull-up control Timer output TOUT output control bit Serial I/O2 ready output (10) Ports P50,P55 (12) Port P52 Direction register Port latchData bus Pull-up control Serial I/O2 input CNTR 1 interrupt input Serial I/O2 clock output Serial I/O2 clock input Direction register Port latchData bus Pull-up controlInternal synchronization clock select bits Serial I/O2 port selection bit Timer X operating mode bit Timer output CNTR 0 interrupt input (Pulse output mode selection) Direction register Port latchData bus Pull-up control Real time port control bit INT3 interrupt input Except P61 Data for real time port Direction register Port latchData bus Pull-up control (14) Port P54 (16) Ports P60, P61(15) Port P56 (13) Port P53 Fig. 13 Port block diagram (2)

3820 GROUP USER’S MANUAL1-18

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 14 Port block diagram (3) (17) Port P70 Data bus Direction register Port latch Port selection/Pull-up control Port XC switch bit Oscillation circuit Port P71 Port XC switch bit VL3 VL2 VL1 (19) COM0 –COM 3 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS (18) Port P71 Data bus Direction register Port latch Port XC switch bit Port selection/Pull-up control Sub-clock generating circuit input (20) SEG0 – SEG 15 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. VL2/VL3 VL1/VSS

Interrupt enable bits can be set or cleared by software. table into the program counter. (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. Table 7. Interrupt vector addresses and priority Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.

3820 GROUP USER’S MANUAL1-20

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 15 Interrupt control Fig. 16 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request 7 0 7 0 7 0 7 0 7 0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit Not used (return “0” when read) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT 2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit Serial I/O2 interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT 2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit Serial I/O2 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F 16) 0 : Falling edge active 1 : Rising edge active

1-213820 GROUP USER’S MANUAL MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER K ey Input Interrupt (Key-on W ake Up) A Key input interrupt request is generated by applying “L” level to any pin of port P3 that have been set to input mode. In other w ords, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 9, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P2 3. Fig. 17 Connection example when using key input interrupt and port P2 block diagram ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] Port P20 latch Port P20 direction register = "0" Port P21 latch Port P21 direction register = "0" Port P22 latch Port P22 direction register = "0" Port P23 latch Port P23 direction register = "0" Port P24 latch Port P24 direction register = "1" Port P25 latch Port P25 direction register = "1" Port P26 latch Port P2 direction register = "1" Port P27 latch Port P27 direction register = "1" P20 input P21 input P22 input P23 input P24 output P25 output P26 output P27 output PULL register A Bit 2 = "1" Port P2 Input reading circuit Port PXx "L" level output –] P-channel transistor for pull-up ] ] CMOS output buffer Key input interrupt request

3820 GROUP USER’S MANUAL1-22

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER TIMERS The 3820 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. When a timer underflows , the interrupt request bit corre- sponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When wr iting to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. Fig. 18 Timer block diagram Timer 1 count source selection bit Real time port control bit "0" "1" P55/CNTR 1 "0" f(XIN)/16 (f(XCIN)/16 in low-speed mode*) CNTR 1 active edge switch bit "10" Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection Timer Y operating mode bit Timer X interrupt request Timer X mode register write signal P54/CNTR 0 Timer X (low) (8) Timer X (high) (8) Timer X (low) latch (8)Timer X (high) latch (8) Q Q T S P54 direction register Pulse output mode P54 latch Timer X stop control bit "0" "1" Timer X write control bit Q D Latch Q D Latch "1" "0" "1" "10" Timer X operat- ing mode bit f(XIN)/16 (f(XCIN)/16 in low-speed mode*) Pulse width measurement mode CNTR 0 active edge switch bit CNTR 0 active edge switch bit Pulse output mode Timer 2 latch (8) Timer 2 (8) Q Q T S "0" P56 direction register P56 latch "1" TOUT output active edge switch bit "0" Timer 2 write control bit "0" "1" TOUT output control bit "1" P56/TOUT XCIN Timer 3 count source selection bit "0" "1" Timer 2 interrupt request Timer 3 interrupt request TOUT output control bit Timer 2 count source selection bit Timer 1 latch (8) Timer 1 (8) Timer 1 interrupt request Data bus f(XIN)/16 (f(XCIN)/16 in low-speed mode*) f(XIN)/16 (f(XCIN)/16 in low-speed mode*) f(XIN)/16(f(XCIN)/16 in low-speed mode*) * Internal clock f = XCIN/2. CNTR 0 interrupt request CNTR 1 interrupt request Timer Y operating mode bit "11" P60 direction register "0" Real time port control bit "1" P60 P60 latch P61 direction register "0" Real time port control bit "1" P61 P61 latch P60 data for real time port P61 data for real time port Timer Y (low) (8) Timer Y (high) (8) Timer Y (low) latch (8)Timer Y (high) latch (8) Timer 3 latch (8) Timer 3 (8)

1-233820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16 in low-speed mode). Pulse output mode Each time the timer underflows, a signal output from the CNTR pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P5 4 direction register to output mode. Event counter mode The timer counts signals input through the CNTR 0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P5 4 direction register to input mode. Pulse width measurement mode The count source is f(X IN)/16 (or f(XCIN)/16 in low-speed mode. If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode. Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Note on CNTR 0 Interrupt Active Edge Selec- tion CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P6 0 and P6 1 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from “0” to “1”, data is output without the timer X.) If the data for the real time port is changed while the real time port function is valid, the changed data are out- put at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. Fig. 19 Structure of timer X mode register Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid 0 data for real time port 0 : "L" level output 1 : "H" level output P61 data for real time port 0 : "L" level output 1 : "H" level output Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR 0 active edge switch bit

• CNTR0 interrupt 0 : Falling edge active 1 : Rising edge active
• Pulse output mode 0 : Start at initial level "H" output 1 : Start at initial level "L" output
• Event counter mode 0 : Rising edge active 1 : Falling edge active
• Pulse width measurement mode 0 : Measure "H" level width 1 : Measure "L" level width Timer X stop control bit 0 : Count start 1 : Count stop

3820 GROUP USER’S MANUAL1-24

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down/Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. Event counter mode The timer counts signals input through the CNTR 1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. Pulse width HL continuously measurement mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 5 direction register to input mode. Note on CNTR 1 Interrupt Active Edge Selec- tion CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 20 Structure of timer Y mode register Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit CNTR 1 interrupt 0 : Falling edge active 1 : Rising edge active Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge Event counter mode 0 : Rising edge active 1 : Falling edge active Timer Y stop control bit 0 : Count start 1 : Count stop

1-253820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvert- ent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Timer 2 Output Control When the timer 2 (TOUT ) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the out- put mode. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 21 Structure of timer 123 mode register TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Timer 2 count source selection bit 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer 3 count source selection bit 0 : Timer 1 underflow 1 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer 1 count source selection bit 0 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) 1 : f(XCIN) Not used (return "0" when read) Timer 123 mode register (T123M :address 002916) 7 0 Note : Internal clock f is f (XCIN)/2 in the low-speed mode.

3820 GROUP USER’S MANUAL1-26

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O1. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 0018 16). Fig. 22 Block diagram of clock synchronous serial I/O1 Fig. 23 Operation of clock synchronous serial I/O1 function 1/4XIN F/F P46/SCLK1 Serial I/O1 status register Serial I/O1 control register P47/SRDY1 P44/RXD P45/TXD f(XIN) Receive buffer register (RB) Address 001816 Receive shift register Receive buffer full flag (RBF) Serial I/O receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronization clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Data bus Address 001816 Shift clock Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Serial I/O transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register Transmit buffer register (TB) D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxDWrite signal to receive/transmit buffer register (address 001816) Overrun error (OE) detection Notes 1 : The serial I/O1 transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The serial I/O1 receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

1-273820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O1 mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 24 Block diagram of UART serial I/O1 Fig. 25 Operation of UART serial I/O1 function f(XIN) OE PE FE Data bus Receive buffer register(RB) Address 001816 Receive shift register Receive buffer full flag (RBF) Serial I/O receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register Data bus Transmit shift register Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 STdetector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronization clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD P45/TXD TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer register write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The serial I/O1 receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer register read signal

3820 GROUP USER’S MANUAL1-28

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 Control Register (SIO1CON) 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. UART Control Register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD pin. Serial I/O1 Status Register (SIO1STS) 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at re- set, but if the transmit enable bit (bit 4) of the serial I/O control reg- ister has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer/Receive Buffer Register (TB/ RB) 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write- only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer regis- ter is “0”. Baud Rate Generator (BRG) 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.

1-293820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Not used (returns “1” when read) Serial I/O1 status register (SIO1STS : address 0019 16) Serial I/O1 control register (SIO1CON : address 001A 16) 0 0 BRG count source selection bit (CSS) 0: f(X IN) 1: f(XIN)/4 Serial I/O1 synchronization clock selection bit (SCS)

• In clock synchronous mode 0 : BRG output/4 1 : External clock input
• In UART mode 0 : BRG output/16 1 : External clock input/16 S RDY1 output enable bit (SRDY) 0: P47 SRDY1 pin operates as I/O port P47 1: P47 SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) Transmit interrupt source selection bit (TIC) 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous serial I/O1 (UART) mode 1: Clock synchronous serial I/O1 mode Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4–P4 7 operate as I/O pins) 1: Serial I/O1 enabled (pins P4 4–P4 7 operate as serial I/O1 pins) UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return“1” when read) Fig. 26 Structure of serial I/O1 control registers

3820 GROUP USER’S MANUAL1-30

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 Control Register (SIO2CON) 001D16 The serial I/O2 control register contains 7 bits which control vari- ous serial I/O functions. Fig. 27 Structure of serial I/O2 control register Fig. 28 Block diagram of serial I/O2 function Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronization clock select bits 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: 1 0 1: 1 1 0: f(X IN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: S RDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Synchronization clock selection bit 0: External clock 1: Internal clock Not used (returns “0” when read) b2 b1 b0 Do not set XIN "1" "0" "0" "1" "0" "1" SRDY2 SCLK2 "0" "1" Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) Synchronization circuit Serial I/O2 port selection bit Synchronization clock selection bit SRDY2 output enable bit External clock Internal synchronization clock select bits Divider P53 latch P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P52 latch P51 latch

1-313820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 29 Timing of serial I/O2 function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 register write signal (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Notes

3820 GROUP USER’S MANUAL1-32

control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, Fig. 30 Structure of segment output enable register and LCD mode register 7 0 Segment output enable register (SEG : address 003816) 7 0 LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not available 0 1 : 2 (use COM0,COM 1) 1 0 : 3 (use COM0–COM 2) 1 1 : 4 (use COM0–COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Not used (returns "0" when read) (Do not write "1" to this bit) LCD circuit divider division ratio selection bits 0 0 : LCDCK count source 0 1 : 2 division of LCDCK count source 1 0 : 4 division of LCDCK count source 1 1 : 8 division of LCDCK count source LCDCK count source selection bit (Note) 0 : f(X CIN)/32 1 : f(XIN)/8192 Segment output enable bit 0 0 : Input ports P30–P37 1 : Segment output SEG16–SEG 23 Segment output enable bit 1 0 : I/O ports P00, P01 1 : Segment output SEG24,SEG 25 Segment output enable bit 2 0 : I/O ports P02–P07 1 : Segment output SEG26–SEG 31 Segment output enable bit 3 0 : I/O ports P10,P11 1 : Segment output SEG32,SEG 33 Segment output enable bit 4 0 : I/O port P12 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P13–P17 1 : Segment output SEG35–SEG 39 Not used (return "0" when read) (Do not write "1" to this bit) Note : LCDCK is a clock for a LCD timing controller. the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the LCD panel.

Table 8. Maximum number of display pixels at each

1-333820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 31 Block diagram of LCD controller/driver Data bus Timing controller LCD divider f(XCIN) f(XIN)/ 256 Common driverBias controlSegment driver Segment driver COM 0 COM 1 COM 2 COM 3 VSS VL1 VL2 VL3SEG 3SEG 2SEG 1SEG 0 Address 004016 Address 004116 “1” “0” LCDCK LCDCK count source selection bit LCD circuit divider division ratio selection bits Bias control bit LCD enable bit Duty ratio selection bits 2 2 Selector Selector Selector Selector SelectorSelector LCD display RAM Segment driver Segment driver Segment driver Segment driver Address 005316 Common driver Common driver Common driver P16/SEG 38P30/SEG 16 P17/SEG 39

3820 GROUP USER’S MANUAL1-34

Table 3 according to the bias value. Table 9. Bias control and applied voltage to VL1–VL3 Table 10. Duty ratio control and common pins used

1-353820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 33 LCD display RAM map Bit Address 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 25 SEG 27 SEG 29 SEG 31 SEG 33 SEG 35 SEG 37 SEG 39 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 SEG 24 SEG 26 SEG 28 SEG 30 SEG 32 SEG 34 SEG 36 SEG 38 004016 004116 004216 004316 004416 004516 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 11 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10

3820 GROUP USER’S MANUAL1-36

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 34 LCD drive waveform (1/2 bias) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty VL3 VL2=VL1 VSS VL3 VSS OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 VL3 VL2=VL1 VSS VL3 VSS OFFON OFFON OFFON OFFON COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

1-373820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 35 LCD drive waveform (1/3 bias) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 OFFON OFFON OFFON OFFON VL3 VL2 VSS VL1 VL3 VL2 VSS VL1 VL3 VSS VL3 VL2 VSS VL1 VL3 VSS COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

3820 GROUP USER’S MANUAL1-38

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 6- bit watchdog timer H. Initial Value of Watchdog Timer At reset or when writing data into the watchdog timer control reg- ister, the watchdog timer H is set to “3F16” and the watchdog timer L is set to “FF16”. As a write instruction, it is possible to use any in- struction that can cause a write signal such as STA, LDM and CLB. Write data except bit 7 has no significance and the above value is set independently. Watchdog Timer Operation The watchdog timer stops at reset and starts a countdown by writ- ing to the watchdog timer control register. When the watchdog timer H underflows, an internal reset occurs, and the reset status is released after waiting the reset release time. Then the program executes from the reset vector address. Usually, a program is designed so that data can be written into the watchdog timer control register before the watchdog timer H underflows. If data is not written once into the watchdog timer con- trol register, the watchdog timer does not function. At execution of the STP instruction, both clock and watchdog timer stops. At the same time that the stop mode is released, the watch- dog timer restarts a count (Note). On the other hand, at execution of the WIT instruction, the watchdog timer does not stop. The time from execution of writing to the watchdog timer control register until an underflow of the watchdog timer register H is as follows: (When bit 7 of the watchdog timer control register is “0”) Note: During the stop release wait time [XIN (or XCIN) : about 8200 clock cycles], the watchdog timer counts. Accordingly, does not underflow the watchdog timer H. Fig. 37 Structure of watchdog timer control register Fig. 36 Watchdog timer block diagram XIN Data bus XCIN “1” “0” Internal system clock selection bit (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit Undefined instruction Reset Watchdog timer H (6) When writing to watchdog timer control register set “3F16” Internal resetRESET Watchdog timer L (8) When writing to watchdog timer control register set “FF16” Note: This bit is bit 7 of CPU mode register. It selects the mode (middle/high-speed or low-speed) Reset release wait time (about 8200 XIN clock cycles) Watchdog timer H bits (read only) Not used (returns “1” when read) Watchdog timer H count source selection bit 0 : Underflow from watchdog timer L 1 : f(XIN)/16 or f(XCIN)/16 Watchdog timer control register (WDTCON : address 003716) 7 0

1-393820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER φ CLOCK OUTPUT FUNCTION The internal system clock φ can be output from port P41 by setting the φ output control register. Set bit 1 of the port P4 direction reg- ister to when outputting φ clock. Fig. 38 Structure of φ output control register 7 0 φ output control register (CKOUT : address 002A16) φ output control bit 0 : Port function 1 : φ clock output Not used (return “0” when read)

3820 GROUP USER’S MANUAL1-40

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Register contents (000116) • • • Timer Y (low-order) Port P0 direction register Port P1 direction register Port P2 direction register PULL register B Timer Y (high-order) Serial I/O1 control register UART control register Serial I/O2 control register Timer X (high-order) 1 ) (2 ) (3 ) (4 ) (5 ) (6 ) (7 ) (8 ) (9 ) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (0003 16) • • • (000516) • • • (001716) • • • (001A16) • • • (001B16) • • • (001D16) • • • (002016) • • • (002116) • • • (002216) • • • (002316) • • • (002416) • • • (002516) • • • (002616) • • • (002716) • • • (002816) • • • (002916) • • • (002A16) • • • Address Timer X (low-order) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register φ output control register 0016 0016 0016 FF16 0116 FF16 FF16 FF16 FF16 FF16 0016 0016 0016 Port P7 direction register(000F16) • • • 0016 111000 0 0 Serial I/O1 status register(001916) • • • 100000 0 0 Port P4 direction register Port P5 direction register Port P6 direction register (000916) • • • (000B16) • • • 0016 0016 0016 0016 0016 (25) (26) (27) (0037 16) • • • (003816) • • • (003916) • • • Watchdog timer control register Segment output enable register LCD mode register 0016 PULL register A (001616) • • • 000010 1 1 Note. 5 : Undefined The contents of all other registers and RAM are undefined at poweron reset, so they must be initialized by software. (28) (29) (30) (31) (32) (33) (34) (35) (003A 16) • • • (003B16) • • • (003C16) • • • (003D16) • • • (003E16) • • • Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter 0016 0016 0016 0016 010010 0 0 0016 Contents of address FFFC16 55555 1 55(PS) (PCH ) (PCL) Contents of address FFFD16 (003F16) • • • 0016 011111 1 1 0016 RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L ” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.5 V and 5.5 V, and the oscillation should be stable), reset is released. In or- der to give the X IN clock time to stabilize, internal operation does not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(XIN)/16) are complete. Af- ter the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for VCC of

2.5 V (Extended operating temperature version: the reset input

voltage is less than 0.6V for VCC of 3.0V). Fig. 40 Internal state of microcomputer immediately after re- set Fig. 39 Example of reset circuit (Note) 0.2VCC Note. Reset release voltage : VCC = 2.5V (Extended operating temperature version : 3.0V) Power on VCCRESET VCCRESET Power source voltage detection circuit Reset input voltage Power source voltage

1-413820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 41 Reset sequence FFFC FFFD AD H, AD L?? ? ? XIN : about 8200 clock cycles Notes 1 : XIN and f are in the relation : f(XIN) = 8•f(f) Notes 2 : A question mark (?) indicates an undefined status that depens on the previous status. Reset address from vector table RESET Internal reset Address Data SYNC f XIN AD L AD H

3820 GROUP USER’S MANUAL1-42

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 3820 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No exter- nal resistor is needed between X IN and XOUT since a feed-back re- sistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. The pull-up resistor of XCIN and XCOUT pins must be made invalid to use the sub-clock. Frequency Control Middle-speed mode The internal clock φ is the frequency of X IN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of XIN. Low-speed mode

• The internal clock φ is half the frequency of XCIN.
• A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscil- lation to stabilize by programming. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and XCIN oscillations. The suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(X IN)>3f(XCIN). Fig. 42 Ceramic resonator circuit Fig. 43 External clock input circuit XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd XIN XOUT External oscillation circuit Open VCC VSS C CIN C COUT Rf Rd XCIN XCOUT Oscillation Control Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of X IN and XCIN are the same as the state be- fore the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.

1-433820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 44 Clock generating circuit block diagram WIT instruction STP instruction Timing f (Internal system clock) S R Q STP instruction S R Q Main clock stop bit S R Q Timer 2Timer 11/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Interrupt disable flag I Reset Port XC switch bit "1" "0" "1" "0" Timer 1 count source selection bit "0" "1" Timer 2 count source selection bit Low-speed mode Middle/High-speed mode Internal system clock selection bit (Note 1) Middle-speed mode High-speed mode or Low-speed mode Note : When using the low-speed mode, set the port XC switch bit to "1" . Main clock division ratio selection bit

3820 GROUP USER’S MANUAL1-44

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 45 State transitions of internal clock φ CM 4 : Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM 5 : Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) Note ResetCM 4 CM 7 CM 4CM 5 CM 6 CM 6 CPU mode register (CPUM : address 003B16) 7 4 CM 7CM 5 CM 6 CM 6 "0""1" "0""1" "0""1" "0""1" CM 4CM 6 "1" "0" "0" "1"CM CM 6 "0" "1" "0" "1" CM 5CM 6 "1" "0" "0" "1"CM CM 6 "0" "1" "0" "1" CM 7=0(8MHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) CM 7=0(8MHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) CM 7=0(8MHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=0(High-speed) CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) CM 7=0(8MHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=1(Middle-speed) CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) Low-speed mode (f(φ) =16 kHz)Low-speed mode (f(φ) =16 kHz) Low-speed mode (f(φ) =16 kHz) Low-speed mode (f(φ) =16 kHz) High-speed mode (f(φ) =4MHz)Middle-speed mode (f(φ) =1 MHz) Middle-speed mode (f(φ) =1 MHz) High-speed mode (f(φ) =4MHz) 1:Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2:The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is released. 3:Timer and LCD operate in the wait mode. 4:In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5:In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2. 6:Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high- speed mode. 7:The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

1-453820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit en- able bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

3820 GROUP USER’S MANUAL1-46

1. Mask ROM Order Confirmation Form
2. Data to be written to ROM, in EPROM form (three identical

Table 11. Programming adapter Figure 46 is recommended to verify programming. expose to 150 °C exceeding 100 hours.

1-473820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Absolute maximum ratings Table 12 Absolute maximum ratings Power source voltage Input voltage P00–P0 7, P10–P17, P20–P2 7, P30–P3 7, P40–P47, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P07, P10–P17 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P47, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C Table 13 Recommended operating conditions (1) (VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Recommended operating conditions 5.5 5.5 5.5 V CC VCC VCC VCC

0.3 VCC

0.2 VCC

High-speed mode f(XIN)=8 MHz Power source voltage Middle-speed mode f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P17, P30–P37, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P44, P46, P50, P52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L” input voltage P0 0–P0 7, P10–P17, P30–P37, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L ” input voltage P2 0–P2 7, P42–P44, P46, P50, P52, P54, P55, P57, P60 “L ” input voltage RESET “L ” input voltage X IN VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.5 2.5 0.7 V CC

0.8 VCC

5.0 5.0 5.0 Typ. Max.

1-48 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 14 Recommended operating conditions (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50 %. 5:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 (4XVCC )–8 8.0 “H” total peak output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total peak output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P27, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P0 7, P10–P1 7 (Note 2) “L” peak output current P2 0–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (2XVCC )–4 MHz MHz

1-493820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note 1:When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P17, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” output voltage P00–P0 7, P10–P17, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note 1) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P17, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P57, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L ” input current P00–P0 7, P10–P1 7, P30–P37, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P57, P60, P61, P71 “L ” input current RESET “L ” input current X IN RAM hold voltage Symbol Parameter Limits Min. V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA V Unit Table 15 Electrical characteristics (1) (VCC =4.0 to 5.5 V , Ta = –20 to 85 °C, unless otherwise noted)

Electrical characteristics

0.5 0.5 0.5 4.0 –70 –25 –4.0 Typ. Max. IOH = –0.1 mA IOH = –25 µA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V RESET: VCC =2.5 V to 5.5 V VI = VCC Pull-downs “off” VCC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS When clock is stopped Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM VOH VOH VOL VOL VCC –2.0 VCC –1.0 VCC –2.0 VCC –0.5 VCC –1.0 6.0 –30 2.0 2.0 0.5 1.0 2.0 0.5 1.0 5.0 140 5.0 5.0 –5.0 –5.0 –140 –45 –5.0 5.5

1-50 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. Unit Table 16 Electrical characteristics (2) (VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Typ. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µA µA µA µA µA Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V , Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V , Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.1 3.2 14.0 9.0 1.0

1-513820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L ” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L ” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 17 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Timing requirements 1 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 18 Timing requirements 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 125 500/ CC –2) 250/ (VCC –2)–20 250/ (VCC –2)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). Timing requirements 2

1-52 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25t C(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 19 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tc(SCLK1 )/2–30 tc(SCLK1 )/2–30 –30 tc(SCLK2 )/2–160 tc(SCLK2 )/2–160 Typ. Max. t wH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25t C(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 20 Switching characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tc(SCLK1 )/2–50 tc(SCLK1 )/2–50 –30 tc(SCLK2 )/2–240 tc(SCLK2 )/2–240 Max. t wH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Switching characteristics 1 Switching characteristics 2 Typ.

1-533820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Absolute maximum ratings (Extended operating temperature version) Recommended operating conditions (Extended operating temperature version) Table 21 Absolute maximum ratings (Extended operating temperature version) Power source voltage Input voltage P00–P0 7, P10–P17, P20–P2 7, P30–P3 7, P40–P47, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P07, P10–P17 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P47, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –40 to 85 –65 to 150 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C Table 22 Recommended operating conditions (Extended operating temperature version) (1) (VCC = 3.0 to 5.5 V , Ta = –40 to –20 °C and VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 High-speed mode f(X IN)=8 MHz Middle-speed mode Power source voltage f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P17, P30–P3 7, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P44, P46, P50,P52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L ” input voltage P0 0–P0 7, P10–P17, P30–P3 7, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L ” input voltage P2 0–P2 7, P42–P44, P46, P50,P52, P54, P55, P57, P60 VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.5 3.0 5.0 5.0 5.0 5.0 Typ. Max. Ta = –20 to 85 °C Ta = –40 to –20 °C Ta = –20 to 85 °C Ta = –40 to –20 °C 2.5 3.0

0.7 VCC

5.0 5.5 VCC VCC VCC VCC “L ” input voltage RESET “L ” input voltage X IN

1-54 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 23 Recommended operating conditions (Extended operating temperature version) (2) (VCC = 3.0 to 5.5 V , Ta = –40 to –20 °C and VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C unless otherwise noted) Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50 %. 5:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 (4XVCC )–8 8.0 “H” total peak output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total peak output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P27, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P0 7, P10–P1 7 (Note 2) “L” peak output current P2 0–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (2XVCC )–4 MHz MHz

1-553820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note 1:When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P17, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P17, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P17, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P57, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L ” input current P00–P0 7, P10–P1 7, P30–P37, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P57, P60, P61, P71 “L ” input current RESET “L ” input current X IN RAM hold voltage Symbol Parameter Limits Min. V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA V Unit Table 24 Electrical characteristics (Extended operating temperature version) (1) (VCC =2.5 to 5.5 V , Ta = –20 to 85 °C, and VCC =3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted) Electrical characteristics (Extended operating temperature version) 0.5 0.5 0.5 4.0 –70 –25 –4.0 Typ. Max. IOH = –2.5 mA IOH = –0.6 mA VCC = 3.0 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 3.0 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 3.0 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 3.0 V RESET: VCC =3.0 V to 5.5 V VI = VCC Pull-downs “off” VCC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS When clock is stopped Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM VOH VOH VOL VOL VCC –2.0 VCC –0.9 VCC –2.0 VCC –0.5 VCC –0.9 6.0 –30 2.0 2.0 0.5 1.1 2.0 0.5 1.1 5.0 170 5.0 5.0 –5.0 –5.0 –140 –45 –5.0 5.5

1-56 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. Unit Table 25 Electrical characteristics (Extended operating temperature version) (2) (VCC =3.0 to 5.5 V, Ta = –40 to –20 °C and VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Typ. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µA µA µA µA µA Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V , Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V , Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.1 3.2 14.0 9.0 1.0

1-573820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L ” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L ” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 26 Timing requirements 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Timing requirements 1 (Extended operating temperature version) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 27 Timing requirements 2 (Extended operating temperature version) (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20 °C, unless otherwise noted) 125 500/ (VCC –2) 250/ (VCC –2)–20 250/ (VCC –2)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). Timing requirements 2 (Extended operating temperature version)

1-58 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25t C(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 28 Switching characteristics 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) tc(SCLK1 )/2–30 tc(SCLK1 )/2–30 –30 tc(SCLK2 )/2–160 tc(SCLK2 )/2–160 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25t C(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 29 Switching characteristics 2 (Extended operating temperature version) (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted) tc(SCLK1 )/2–50 tc(SCLK1 )/2–50 –30 tc(SCLK2 )/2–240 tc(SCLK2 )/2–240 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Switching characteristics 1 (Extended operating temperature version) Switching characteristics 2 (Extended operating temperature version) Typ.

1-593820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Absolute maximum ratings (Low power source voltage version) Table 30 Absolute maximum ratings (Low power source voltage version) Power source voltage Input voltage P00–P0 7, P10–P17, P20–P2 7, P30–P3 7, P40–P47, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P07, P10–P17 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P47, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C Table 31 Recommended operating conditions (Low power source voltage version) (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Recommended operating conditions (Low power source voltage version) 5.5 5.5 5.5 V CC VCC VCC VCC High-speed mode f(XIN)=8 MHz Power source voltage Middle-speed mode f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P17, P30–P37, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P44, P46, P50, P52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L” input voltage P0 0–P0 7, P10–P17, P30–P37, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L ” input voltage P2 0–P2 7, P42–P44, P46, P50, P52, P54, P55, P57, P60 “L ” input voltage RESET “L ” input voltage X IN VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.2 2.2 0.7 V CC 5.0 5.0 5.0 Typ. Max.

1-60 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 32 Recommended operating conditions (Low power source voltage version) (2) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50 %. 5:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 8.0 “H” total peak output current P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total peak output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L ” total average output currentP00–P0 7, P10–P1 7, P20–P2 7 (Note 1) “L ” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P27, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P0 7, P10–P1 7 (Note 2) “L” peak output current P2 0–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P47, P50–P57, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (10XVCC –4) MHz MHz (20XVCC –8)

1-613820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note 1:When “1” is set to port XC switch bit (bit 4of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P17, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P17, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P17, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P57, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L ” input current P00–P0 7, P10–P1 7, P30–P37, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P57, P60, P61, P71 “L ” input current RESET “L ” input current X IN Symbol Parameter Limits Min. V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA Unit Table 33 Electrical characteristics (Low power source voltage version) (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Electrical characteristics (Low power source voltage version) 0.5 0.5 0.5 8.0 4.0 –70 –25 –8.0 Typ. Max. IOH = –0.1 mA IOH = –25 µA VCC = 2.2 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.2 V RESET: VCC =2.2 V to 5.5 V VI = VCC Pull-downs “off” VCC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VOH VOH VOL VOL VCC –2.0 VCC –1.0 VCC –2.0 VCC –0.5 VCC –1.0 6.0 –30 2.0 0.5 1.1 2.0 0.5 1.0 5.0 170 5.0 5.0 –5.0 –5.0 –140 –45 –5.0

1-62 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER All oscillation stopped (in STP state) Output transistors “off” Symbol VRAM Parameter RAM hold voltage Limits Min. 2.0 Unit V Table 34 Electrical characteristics (Low power source voltage version) (2) (VCC =2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Typ. Max. 5.5 Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µA µA µA µA µA Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V , Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V , Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.2 3.2 14.0 9.0 2.0 When clock is stopped

1-633820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L ” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L ” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 35 Timing requirements 1 (Low power source voltage version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Timing requirements 1 (Low power source voltage version) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock iuput cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 36 Timing requirements 2 (Low power source voltage version) (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 125 900/ (VCC –0.4) 450/ (VCC –0.4)–20 450/ (VCC –0.4)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). Timing requirements 2 (Low power source voltage version)

1-64 3820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER Measurement output pin 100pF CMOS output Note : When bit 4 of the UART control register (address 001B16) is “1”. (N-channel open-drain output mode) Measurement output pin 100pF N-channel open-drain output (Note) 1kW Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25 tC(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 37 Switching characteristics 1 (Low power source voltage version) (VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C , unless otherwise noted) tc(SCL K1 )/2–30 tc(SCL K1 )/2–30 –30 tc(SCL K2)/2–160 tc(SCL K2)/2–160 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCL K1–TX D) tv(SCL K1–TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCL K2–S OUT 2) tv(SCL K2–SOUT 2) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes 1: When the P45/TXD P-channel output disable bit of the UAR T control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Switching characteristics 1 (Low power source voltage version) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25 tC(SCLK2) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 38 Switching characteristics 2 (Low power source voltage version) (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C , unless otherwise noted) tc(SCL K1 )/2–50 tc(SCL K1 )/2–50 –30 tc(SCL K2)/2–240 tc(SCL K2)/2–240 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCL K1–TX D) tv(SCL K1–TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCL K2–S OUT 2) tv(SCL K2–SOUT 2) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes 1: When the P45/TXD P-channel output disable bit of the UAR T control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Switching characteristics 2 (Low power source voltage version) Typ. Fig.47 Circuit for measuring output switching characteristics

1-653820GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 0.2VCC tf 0.2VCC 0.8VCC 0.8VCC tr 0.2VCC tWL(X IN) 0.8VCC tWH(X IN) tC(XIN) XIN 0.2VCC 0.8VCC tW(RESET) RESET 0.2VCC tWL(CNTR) 0.8VCC tWH(CNTR) tC(CNTR) 0.2VCC tWL(INT) 0.8VCC tWH(INT) CNTR 0,CNTR 1 INT0–INT3 TXD SOUT2 R XD SIN2 SCLK1 SCLK2 td(SCLK1 -TXD),td(SCLK2 -SOUT2 ) tsu(RXD-SCLK1 ) tsu(SIN2-SCLK2 ) th(SCLK1 -RXD) th(SCLK2 -SIN2) tv(SCLK1 -TXD), tv(SCLK2 -SOUT2 ) tC(SCLK1 ),tC(SCLK2 ) tWL(S CLK1 ),tWL(S CLK2 ) tWH(S CLK1 ),tWH(S CLK2 ) Timing diagram Fig.48 Timing diagram

3820 GROUP USER’S MANUAL1-66

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER STANDARD CHARACTERISTICS Power Source Current Characteristic Examples CC –VCC characteristics). Figure 49, Figure 50, and Figure 51 show ICC –V CC characteristic examples. Fig. 49 ICC –VCC characteristic example (f(XIN) = 8 MHz) Fig. 50 ICC –VCC characteristic example (f(XIN) = 4 MHz) Measuring condition : 25°C, f(XIN) = 8MHz Power source current ICC [mA] Power source voltage VCC [V] High-speed mode Middle-speed mode High-speed mode in wait mode Measuring condition : 25°C, f(XIN) = 4MHz Power source current ICC [mA] Power source voltage VCC [V] Middle-speed mode in wait mode High-speed mode in wait mode Middle-speed mode High-speed mode Middle-speed mode in wait mode and and

1-673820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 51 ICC –VCC characteristic example (f(XIN) = 32 kHz, oscillator used) Measuring condition : 25°C, f(XCIN) = 32 kHz oscillator used Power source current ICC [mA] Power source Voltage VCC [V] in low-speed mode in wait mode

3820 GROUP USER’S MANUAL1-68

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Power Source Frequency Characteristic Examples Figure 52 and Figure 53 show the ICC– f(XIN) characteristic examples. Fig. 52 ICC -f(XIN) characteristic example (VCC = 3.0 V) Fig. 53 ICC -f(XIN) characteristic example (VCC = 5.0 V) 02468 1 0 Measuring condition : 25°C, VCC = 3.0 V Power source current ICC [mA] Frequency f(XIN) [MHz] High-speed mode Middle-speed mode in wait mode High-speed mode in wait mode Middle-speed mode 02468 1 0 Measuring condition : 25°C, VCC = 5.0 V Power source current ICC [mA] Frequency f(XIN) [MHz] High-speed mode Middle-speed mode in wait mode High-speed mode in wait mode Middle-speed mode and

1-693820 GROUP USER’S MANUAL MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port Standard Characteristics Examples Figure 52, Figure 53, Figure 54, and Figure 55 show port standard characteristic examples. Fig. 54 IOH –VOH characteristic example of CMOS output port at P-channel drive (P0, P1, P3) Fig. 55 IOL –VOL characteristic example of CMOS output port at N-channel drive (P0, P1, P3) VOH [V] IOH [mA] –10 –20 VCC = 5 V Ta = 25°C VOC = 3 V Ta = 25°C Port P00 IOH -VOH characteristic (P-channel drive) (Pins with same characteristic : P0, P1, P3) VOL [V] IOL [mA] VCC = 5 V Ta = 25°C VCC = 3 V Ta = 25°C Port P00 IOL -VOL characteristic (N-channel drive) (Pins with same characteristic : P0, P1, P3)

3820 GROUP USER’S MANUAL1-70

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 56 IOH –VOH characteristic example of CMOS output port at P-channel drive (P2, P5, P6, P7) Fig. 57 IOL –VOL characteristic example of CMOS output port at N-channel drive (P2, P5, P6, P7) VOH [V] IOH [mA] –10 –50 –20 –30 –40 VCC = 5 V Ta = 25 °C VCC = 3 V Ta = 25 °C Port P20 IOH -VOH characteristic (P-channel drive) (Pins with same characteristic : P2, P5, P6, P7) VOL [V] IOL [mA] 100 VCC = 5 V Ta = 25 °C VCC = 3 V Ta = 25 °C Port P20 IOL -VOL characteristic (N-channel drive) (Pins with same characteristic : P2, P5, P6, P7)

2.1 I/O pins

2.2 Interrupts

2.3 Timer X and timer Y

2.4 Timer 1, timer 2, and

2.5 Serial I/O1

2.6 Serial I/O2

2.7 LCD drive control circuit

2.8 Watchdog timer

2.9 Standby function

2.11 Oscillation circuit

3820 GROUP USER’S MANUAL2–2

2.1.1 I/O ports

(1) I/O port write and read n The input-only ports and programmable I/O ports set for the input mode The input-only ports and the programmable I/O ports set for the input mode are floating. The value (pin state) input to the port is read by reading the port register corresponding to each port. In writing data into the port register corresponding to each port, the data is only written to the port register but the pin remains in the floating state. n Output-only ports and programmable I/O ports set for the output mode The value written to the port register corresponding to an output port or a programmable I/O port set for the output mode is output externally through a transistor. In reading the data of the port transistor corresponding to each port, the pin state is not read but the value written to the port register is read. Accordingly, even if the output “H” voltage is reduced or the output “L” voltage is increased by external load, the previous output value is correctly read. Fig. 2.1.1 I/O port write and read At output : •An output value is set by writing to the port register. Port register (at writing) At input : •Writing to a port register is possible. ] : The P- and N-channel transistors are cut off. Port register (at reading) Port direction register (“0”) Read the pin state Port register Port direction register (“1”) “H” level output “L” level output

• A pin state is read by reading the port register.•Reading a port register is possible.

3820 GROUP USER’S MANUAL 2–3

Table 2.1.1 shows the memory allocation of the port registers corresponding to each port. Table 2.1.1 Memory allocation of port registers Port Port register address 000016 000216 000416 000616 000816 000A 16 000C 16 000E 16 (2) Input/output switching of programmable I/O ports Input/output switching of the programmable I/O ports is performed by the port direction register cor- responding to each port (Note). Figure 2.1.2 shows the structure of the port Pi (i = 2, 4 to 7) direction register, and Table 2.1.2 shows the memory allocation of the port direction registers corresponding to each port. Figure 2.1.4 shows a port direction register setting example. Note: In ports P0 and P1, input/output switching is performed by a port unit. By setting bit 0 of the corresponding direction register to “0,” the port is set for the input mode. By setting to “1,” the port is set for the output mode. Figure 2.1.3 shows the structure of the ports P0 and P1 direction registers. Fig. 2.1.2 Structure of port Pi (i = 2, 4 to 7) direction register Notes 1: Nothing is allocated bit 0 of port P4 direction register and bit 2 to bit 7 of port P7 direction register. These bits cannot be written to. 2: The contents of the port Pi direction register cannot be read out (refer to “2.1.4 Notes on use”). b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 2, 4 to 7) [Address 05 16, 0916, 0B16, 0D16, 0F16] B Name Functions At reset R W Port Pi direction register Port Pi direction register 0 : Port Pi 0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode

3820 GROUP USER’S MANUAL2–4

Fig. 2.1.3 Structure of ports P0 and P1 direction registers Port Port direction register address 000116 000316 000516 000916 000B 16 000D 16 000F 16P7 Table 2.1.2 Memory allocation of port direction registers b7b6 b5b4b3 b2b1b0 Port P0 direction register (P0D) [Address 0116] Port P1 direction register (P1D) [Address 0316] B Name Functions At reset R W Port P0 direction register, port P1 direction register to Port P0 direction register / Port P1 direction register 0 : All bits are input mode 1 : All bits are output mode Note: In ports P0 and P1, input/output switching is performed by a port unit. By setting bit 0 of the corresponding port direction register to “0”, the port is set for the input mode. By setting to “1”, the port is set for the output mode. Nothing is allocated for bits 1 to 7 of the ports P0 and P1 direction registers, and these bits cannot be written to. Nothing is allocated. These bits cannot be written to and be read out. 0 × 0 ××

3820 GROUP USER’S MANUAL 2–5

Fig. 2.1.4 Port direction register setting example (3) Pull-up control and pull-down control The ports shown in Table 2.1.3 are controlled for pull-up and pull-down by software. Either pull-up or pull-down is controlled by the PULL register A (address 001616) and the PULL register B (address of the PULL register B. Table 2.1.3 I/O ports which either pull-up or pull- down is controlled by software Control Pull-down Pull-up Ports P0, P1, P3 P2, P41 to P47, P5 to P7 Example : When setting “6B16” to the port P2 direction register P27 P26 P25 P24 P23 P22 P21 P20 Input/output direction of port P2 OutputInputOutputOutputOutputOutputInput Input b7 b0 01101011

3820 GROUP USER’S MANUAL2–6

Fig. 2.1.6 Structure of PULL register B Fig. 2.1.5 Structure of PULL register A b7 b6b5b4 b3b2b1 b0 PULL register A (PULLA) [Address 1616] B Name Functions At resetR W PULL register A

0 P00–P07 pull-down 0 : No pull-down

1 : Pull-down Note: For ports set for the output mode, pull-up or pull-down is impossible.

1 P10–P17 pull-down 0 : No pull-down

1 : Pull-down

2 P20–P27 pull-up 0 : No pull-up

1 : Pull-up

3 P30–P37 pull-down 0 : No pull-down

1 : Pull-down

4 P70, P71 pull-up 0 : No pull-up

1 : Pull-up to Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. b7 b6b5 b4 b3b2b1 b0 PULL register B (PULLB) [Address 1716] B Name Functions At resetR W PULL register B

0 P41-P43 pull-up 0 : No pull-up

1 : Pull-up Note: For ports set for the output mode, pull-up is impossible. 1 0 : No pull-up 1 : Pull-up 2 0 : No pull-up 1 : Pull-up 3 0 : No pull-up 1 : Pull-up 4 0 : No pull-up 1 : Pull-up Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60, P61 pull-up to ×00

3820 GROUP USER’S MANUAL 2–7

2.1.2 Function pins

Each function pin except I/O ports is described below. (1) Pins VCC and VSS Power source input pins. In the high-speed mode, apply ( + 2) V–5.5 V to the VCC pin. In the middle-speed mode or the low-speed mode, apply 2.5 V–5.5 V to the VCC pin. In all modes, apply 0 V to the VSS pin. (2) Pins VL1, VL2 and VL3 Power source input pins for LCD. Apply 0 ≤ VL1 ≤ VL2 ≤V L3 ≤ VCC of voltage to these pins. (3) Pins XIN and XOUT An input pin and an output pin for the main clock generating circuit. (4) RESET pin The 3820 group is reset internally by keeping the level of this pin at “L” for 2 µs or more. Reset state is released by returning the level of this pin to “H”. (5) Pins SEG0 to SEG 15 Segment signal output pins for LCD. (6) Pins COM 0 to COM 3 Common signal output pins for LCD. When Ta = –40 °C to –20 °C, use the extended operating temperature version, and apply 3.0 V–5.5 V to the VCC pin. f(XIN) MHz

3820 GROUP USER’S MANUAL2–8

2.1.3 Application examples

The basic structure for key input without a pull-up resistor and an application examples of it are described below. In contrast to a method which uses a pull-up resistor, dissipating current incessantly, this method requires only a charging current for a very small capacitance, so it is especially suitable for a battery-driven unit. In the following description, ports A, B, C and D are only tentative names and differ from the real port names. (1) Basic structure for key input Fig. 2.1.7 Connection example 1 for key input Figure 2.1.7 shows a connection example 1 for key input without a pull-up resistor and Figure 2.1.8 shows the key input control procedure 1. Figure 2.1.9 shows a timing diagram 1 where switch A is pressed. Fig. 2.1.8 Key input control procedure 1 CMOS I/O port A CMOS I/O port B CMOS I/O port C SW A SW B SW C r = 10 kΩVirtual capacitor (C) Key input Output “H” for charging to each port ]1 In the case of no key input, output “L” (Noise counter- measure). ]2 A virtual capacitor (C) is charged by outputting “H.” (For capacitance, refer to the next page.) ]3 Set the port direction register for input mode with an instruction immediately after “H” is output. (For the limit timer for ON/OFF judgment and the discharging time at ON, refer to the next page.) ]4 For double reading to ensure data, repeat ]2 and ]3. After inputting data into the port direction register, judge ON/OFF of key input.

3820 GROUP USER’S MANUAL 2–9

Fig. 2.1.9 Timing diagram 1 where switch A is pressed The discharging time (´ , ˆ ) after completion of charge in Figure 2.1.9 is shown with the following expression. The discharging time (T) is obtained with T = CR. lThe capacitance of the virtual capacitor (C) is: Capacitance of microcomputer output transistors and input transistors ... Approx. 10 pF (minimum) Approx. 10 pF l In the leak current standard at 5 V, the maximum value is 5 µA and the standard value is 0.05 µA. Accordingly, the minimum resistance (R) is 1 MΩ and the standard resistance is 100 MΩ . In the above condition, the discharging time (T) is obtained as follows: T (minimum) = 10 pF 5 1 MΩ = 10 5 10-12 5 1 5 106 = 10 5 10-6 (s) T (standard) = 10 pF 5 100 M Ω = 10 5 10-12 5 100 5 106 = 1 5 10-3 (s) Accordingly, the discharging time (T) is 10 µs (minimum) to 1 ms (standard). CMOS I/O port A CMOS I/O port C CMOS I/O port B “L” output “H” output Charge time T “H” output Charge time À \`´ˆ ˜¯ Read port state “L” output “H” output Input Input “H” output “L” output “H” output Input Input “H” output Input Input Read port state

3820 GROUP USER’S MANUAL2–10

Fig. 2.1.11 Key input control procedure 2 <Example> The standard time at VO = 5.0 V, Vt1 = 3.5 V t1 = –1 5 10–3 5 1n ≈ 357 µs (2) Key input application example According to the key input without a pull-up resistor described in (1), an effective applica- tion example where there are enough ports is shown below. This method reduces both cur- rent dissipation and quantity of parts compared with the example shown in (1). Figure 2.1.10 shows a connection example 2 for key input using port D and Figure 2.1.11 shows the key input control procedure 2. Fig- ure 2.1.12 shows a timing diagram 2 where switch A is pressed. Fig. 2.1.10 Connection example 2 for key input [ The discharging time (t2) at ON is obtained with t = Cr in the same way as the previous page, with the result of t = 100 ns. [ Judge ON/OFF of key input within the time (t1) which is obtained as follows: After the completion of “H” output, V t1 = VO 5 e–t1/T t1 = –T 5 1n Vt1 VO V O : “H” output voltage V t1 : Input voltage after t1(s) 3.5 5.0 CMOS I/O port A CMOS I/O port B CMOS I/O port C SW A SW B SW C Virtual capacitor (C) CMOS I/O port D Key input ]1 In the case of no key input, output “L” (Noise counter- measure). ]2 A virtual capacitor (C) is charged by outputting “H.” (For capacitance, refer to the previous page.) ]3 Set the port direction register for input mode with an instruction immediately after “H” is output. ]4 Output “L” with the next instruction (refer to “Figure 2.1.12 (A)”) ]5 For double reading to ensure data, repeat ]2, ]3 and ]4. Set the port direction register for the input mode After outputting “L” from the port D, judge ON/OFF of key input. Output “H” for charging to each port

3820 GROUP USER’S MANUAL 2–11

With the exception that “L” is output using port D for key input (refer to “Figure 2.1.12 (A)”), the basic structure is the same as that shown in (1). The examples shown in (1) and (2) are already put into practical use. However, be sure to evaluate them on the user’s side. In this example, the ports are the same structure as the equivalent circuit which a pull-up resistor of about 1 kΩ is connected. Fig. 2.1.12 Timing diagram 2 where switch A is pressed CMOS I/O port A “L” output “H” output Charge time T “H” output Charge time CMOS I/O port B “L” output “H” output Input Input “H” output CMOS I/O port D “L” output “H” output “L” output “H” output CMOS I/O port C “L” output “H” output Input Input “H” output “L” output (A) (A) Read port state Input Input Read port state

3820 GROUP USER’S MANUAL2–12

2.1.4 Notes on use

When using I/O ports, note the following. (1) Reading the port direction register The value of the port direction register is not readable. The following cannot be used:

• the data transfer instruction (LDA , etc.)
• the operation instruction when the index X mode flag (T) is “1”
• the addressing mode which uses the value of a direction register as an index
• the bit-test instruction (BBC or BBS , etc.) to a direction register
• the read-modify-write instruction (ROR , CLB , or SEB , etc.) to a direction register Use instructions such as LDM and STA , etc., to set the port direction registers. (2) When the data register (port latch) of an I/O port is modified with the bit managing instruction When the data register (port latch) of an I/O port is modified with the bit managing instruction ] 1, the value of the unspecified bit may be changed. REASON The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the data register of an I/O port, the following is executed to all bits of the data register. l As for a bit which is set for an input port: The pin state is read in the CPU, and is written to this bit after bit managing. l As for a bit which is set for an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: l Even when a port which is set as an output port is changed for an input port, its data register holds the output data. l As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents ] 1 bit managing instructions : SEB and CLB instruction (3) Pull-up control and pull-down control To pull-up or pull-down ports by software, note the following. l When ports P0, P1 and P3 are used as segment output pins for LCD, the settings of the pull-down bits corresponding to these ports of the PULL register A are invalid (pull-down is impossible). l When ports P0–P2, P4 1–P4 7 and P5–P7 are set for the output mode, the settings of the bits corresponding to these ports of the PULL register A and PULL register B are invalid (pull-up or pull- down are impossible).

3820 GROUP USER’S MANUAL 2–13

(4) Notes in standby state In standby state] 2 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”, especially for I/O ports of the P-channel and the N-channel open-drain. Pull-up (connect the port to VCC ) or pull-down (connect the port to VSS ) these ports through a resistor. When determining a resistance value, note the following points: l External circuit l Variation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor as an option, note on varied current values. l When setting as an input port : Fix its input level l When setting as an output port : Prevent current from flowing out to external REASON Even when setting as an output port with its direction register, in the following state: the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are “undefined”. This may cause power source current. ] 2 standby state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction

3820 GROUP USER’S MANUAL2–14

(5) Termination of unused pins Table 2.1.4 shows termination of unused pins. TerminationsPins Table 2.1.4 Termination of unused pins P2 0–P2 7 P4 1/φ P4 4/RxD P4 5/TxD P4 6/SCLK1 P4 7/SRDY1 P5 0/SIN2 P5 1/SOUT2 P5 2/SCLK2 P5 3/SRDY2 P5 4/CNTR 0 P5 5/CNTR 1 P5 6/TOUT P6 1/RTP 1 P7 0/XCOUT P7 1/XCIN P0 0/SEG 24–P0 7/SEG 31 P1 0/SEG 32–P1 7/SEG 39 P4 0 P4 2/INT0 P4 3/INT1 P5 7/INT2 P6 0/INT3/RTP 0 VL1–VL3 COM 0–COM 3 SEG 0–SEG 15 P30/SEG 16–P37/SEG 23 À After set for the input mode and put the built-in pull-down resistor in the ON state, open.] 1 \ Set for the output mode and open at “L” or “H.”] 2 À After set for the input mode and put the built-in pull-up resistor in the ON state, open.] 1 \ Set for the output mode and open at “L” or “H.”] 2 À After disabling INT interrupts, set for the input mode, and put the built-in pull-up resistor in the ON state, open.] 1 \` Set for the output mode and open at “L” or “H.”] 2 Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ . Connect to VSS level ] 1 After reset and before the built-in pull-up (pull-down) resistor is put in the ON state by software, the built-in pull-up (pull-down) resistor is in the OFF state. Because of this, the potential at these pins are “undefined” and the power source current may increase. Since the direction register setup may be changed for the output mode because of a program runaway or noise, set direction register for the input mode periodically. And make the length of wiring which is connected I/O ports within 2 cm. ] 2 After reset and before I/O ports are switched for the output mode by software, I/O ports are set for the input mode. Because of this, the potential at these pins are “undefined” and the power source current may increase in the input mode. Since the direction register setup may be changed for the input mode because of a program runaway or noise, set direction register for the output mode periodically. And make the length of wiring which is connected I/O ports within 2 cm. Open Put the built-in pull-down resistor in the ON state, open.] 1

2–153820 GROUP USER’S MANUAL

2.2.1 Explanation of operations

When an interrupt request is accepted, the contents immediately before acceptance of the interrupt re- quests of the following registers is automatically pushed onto the stack area in the order of À , \ and ´ . À High-order (PC H ) contents of program counter \ Low-order (PCL) contents of program counter ´ Contents of processor status register (PS) After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of ´ , \` and À and the processing executed immediately before acceptance of the interrupts is continued. Figure 2.2.1 shows an interrupt operation diagram. Fig. 2.2.1 Interrupt operation diagram Interrupt occurs (Accepting interrupt request) Executing routine RTI instruction Interrupt processing routine Suspended operation Resume processing : Operation commanded by software : Internal operation to be performed automatically Contents of program counter (high-order) are pushed onto stack Contents of program counter (low-order) are pushed onto stack Contents of processor status register are pushed onto stack Contents of processor status register are poped from stack Contents of program counter (low-order) are poped from stack Contents of program counter (high-order) are poped from stack

2–16 3820 GROUP USER’S MANUAL INT0 INT1 Serial I/O1 receive Serial I/O1 transmit Timer X Timer Y Timer 2 Timer 3 CNTR CNTR 1 Timer 1 INT2 INT3 Key input (Key-on wake up) Serial I/O2 BRK instruction ReferenceInterrupt request generating conditionsInterrupt sources Table 2.2.1 Interrupt sources and interrupt request generating conditions At detection of either rising or falling edge of INT0 input (Active edge selectable) At detection of either rising or falling edge of INT1 input (Active edge selectable) At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmit buffer register is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR input (Active edge selectable) At detection of either rising or falling edge of CNTR1 input (Active edge selectable) At timer 1 underflow At detection of either rising or falling edge of INT2 input (Active edge selectable) At detection of either rising or falling edge of INT3 input (Active edge selectable) At falling of conjunction of input level for port P2 (at input mode) At completion of serial I/O2 data transmission or reception At BRK instruction execution (1) Interrupt request generating conditions Table 2.2.1 shows interrupt sources and interrupt request generating conditions. The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1.” When the following conditions are satisfied in this state, the interrupt request is accepted. For details, refer to “2.2.2 Control”. À Interrupt disable flag = “0” (interrupts enabled) \` Interrupt enable bit = “1” (interrupts enabled)

2.2.4 INT interrupts

2.4 Timer 1, timer 2, and timer 3

2.2.5 Key input interrupt

SERIES 740 <SOFTWARE> USER’S MANUAL

2–173820 GROUP USER’S MANUAL (2) Processing upon acceptance of an interrupt request Upon acceptance of an interrupt request, the following operations are automatically performed. À The processing being executed is stopped. \` The contents of the program counter and the processor status register are pushed onto the stack area. Figure 2.2.2 shows changes of the stack pointer and the program counter upon acceptance of an interrupt request. ´ Concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. ˆ After the interrupt processing routine is started, the corresponding interrupt request bit is automati- cally cleared to “0.” The interrupt disable flag is set to “1” so that multiple interrupts are disabled. Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. Fig. 2.2.2 Changes of stack pointer and program counter upon acceptance of interrupt request Interrupt disable flag = “0” Program counter Stack pointer Program counter (high-order) Program counter (low-order) PC L PC H (S)S Program counter Stack pointer PC L PC H (S) – 3S Vector address (from Interrupt vector area) Interrupt disable flag = “1” Interrupt request is accepted Stack area (S) Processor status register Program counter (low-order) Program counter (high-order)(S) (s) – 3 Stack area

2–18 3820 GROUP USER’S MANUAL (3) Timing after acceptance of an interrupt request The interrupt processing routine is started at the timing of machine cycle after completion of the executing instruction. Figure 2.2.3 shows the processing time up to the execution of an interrupt processing routine and Figure 2.2.4 shows timing after the acceptance of an interrupt request. Fig. 2.2.3 Processing time up to execution of interrupt processing routine Fig. 2.2.4 Timing after acceptance of interrupt request Interrupt request occurs Main routine Interrupt processing routine 7 to 23 cycles (At internal system clock φ = 3.15 MHz, 2.2 µ s to 7.3 µ s) 2 cycles 5 cycles Waiting time for pipeline post- processing Push onto stack Vector fetch Interrupt operation starts 0 to 16 cycles ] : Refer to “Figure 2.2.4” Note: Refer to “Table 6 in CHAPTER 1 HARDWARE .” : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) : Vector address of each interrupt : Jump destination address of each interrupt (Note) : “00 16” or “0116” SYNC BL, BH AL, AH SPS φ Data bus Not used PC H PC L PS A L AH Address bus S, SPS S-2 , SPSS-1, SPSPC BL BH AL, AH SYNC RD WR Waiting time for pipeline postprocessing Push onto stack Vector fetch Interrupt operation starts

2–193820 GROUP USER’S MANUAL An interrupt request bit, an interrupt enable bit and an interrupt disable flag function independently and do not affect each other. An interrupt is accepted when all the following conditions are satisfied. l Interrupt request bit — “1” l Interrupt enable bit — “1” l Interrupt disable flag — “0” Though the interrupt priority is determined by software, a variety of priority processing can be performed by software using the above bits and flag. Table 2.2.2 shows a list of interrupt bits for individual interrupt sources. (1) Interrupt request bits The interrupt request bits are allocated to the interrupt request register 1 (address 003C 16) and interrupt request register 2 (address 003D16). The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1.” The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt is accepted, this bit is automatically cleared to “0.” Each interrupt request bit can be set to “0” by software, but it cannot be set to “1” by software. Fig. 2.2.5 Interrupt control diagram

2.2.2 Control

For interrupts except the BRK instruction interrupt, the acceptance of interrupt can be controlled by an interrupt request bit, an interrupt enable bit, and an interrupt disable flag. In this section, control of inter- rupts except the BRK instruction interrupt is described and Figure 2.2.5 shows an interrupt control diagram. Interrupt request bit Interrupt enable bit Interrupt disable flag BRK instruction Reset Interrupt request

2–20 3820 GROUP USER’S MANUAL (2) Interrupt enable bits The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F16). The interrupt enable bits control the acceptance of the corresponding interrupt request. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1” and this interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the interrupt request bit remains in the “1” state. When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request occurs when this bit is “1,” this interrupt is accepted (at interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request. When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,” so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. Figure 2.2.6 shows an example of multiple inter- rupts. Interrupt enable bitInterrupt sources Interrupt request bit Address Bit Address Bit 003E 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 003F16 Table 2.2.2 List of interrupt bits for individual interrupt sources 003C 16 003C 16 003C 16 003C 16 003C 16 003C 16 003C 16 003C 16 003D 16 003D 16 003D 16 003D 16 003D 16 003D 16 003D 16 INT0 INT1 Serial I/O1 receive Serial I/O1 transmit Timer X Timer Y Timer 2 Timer 3 CNTR CNTR 1 Timer 1 INT2 INT3 Key input Serial I/O2

2–213820 GROUP USER’S MANUAL Fig. 2.2.6 Example of multiple interrupts Reset I = 1 Interrupt 1 I = 1 I = 0 I = 1 RTI Interrupt request 1 Interrupt request Nesting Time Multipul interrupt C1 = 1 C2 = 1 I = 0 Interrupt request 2 Main routine Interrupt 2 RTI : Interrupt disable flag : Interrupt enable bit of interrupt 1 : Interrupt enable bit of interrupt 2 I I = 0 I = 0 C1 = 0, C2 = 0 : They are set automatically. : Set by software.

2–22 3820 GROUP USER’S MANUAL

2.2.3 Related registers

Figure 2.2.7 shows memory allocation of interrupt-related registers. Each of these registers is described below. (1) Interrupt edge selection register (address 003A16) The interrupt edge selection register selects an active edge of each INT interrupt. Bit 0 to bit 3 select active edges of INT 0–INT3 pins inputs. In the “0” state, the falling edge ( ) of the corresponding pin input is active. In the “1” state, the rising edge ( ) of the corresponding pin input is active. Figure 2.2.8 shows the structure of the interrupt edge selection register. Fig. 2.2.8 Structure of interrupt edge selection register Fig. 2.2.7 Memory allocation of interrupt-related registers Interrupt edge selection register (INTEDGE)003A16 Address Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 003B16 003C 16 003D 16 003E16 003F16 b7b6 b5b4b3 b2b1b0 Interrupt edge selection register (INTEDGE) [Address 3A16] B Name Functions At reset R W Interrupt edge selection register

0 INT0 interrupt edge

0 : Falling edge active 1 : Rising edge active0

1 INT1 interrupt edge

0 : Falling edge active 1 : Rising edge active

2 INT2 interrupt edge

3 INT3 interrupt edge

Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. to 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active

2–233820 GROUP USER’S MANUAL (2) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16) indicate whether an interrupt request has occurred or not. Figure 2.2.9 shows the structure of the interrupt request register 1 and Figure 2.2.10 shows the structure of the interrupt request register 2. The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the interrupt enable bits (refer to the next item). Fig. 2.2.9 Structure of interrupt request register 1 b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 3C16] B Name Functions At reset R W Interrupt request register 1 0 0 : No interrupt request issued 1 : Interrupt request issued 0 ]INT0 interrupt request bit

1 INT 1 interrupt request

2 Serial I/O1 receive

3 Serial I/O1 transmit

] : “0” can be set by software, but “1” cannot be set.

4 Timer X interrupt

5 Timer Y interrupt

6 Timer 2 interrupt

7 Timer 3 interrupt

0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

2–24 3820 GROUP USER’S MANUAL Fig. 2.2.10 Structure of interrupt request register 2 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 3D16] B Name Functions At resetRW Interrupt request register 2

0 CNTR 0 interrupt

0 : No interrupt request issued 1 : Interrupt request issued

1 CNTR 1 interrupt

2 Timer 1 interrupt

3 INT2 interrupt

] : “0” can be set by software, but “1” cannot be set.

4 INT3 interrupt

5 Key input interrupt

6 Serial I/O2

7 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

2–253820 GROUP USER’S MANUAL (3) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F16) control each interrupt request source. Figure 2.2.11 shows the structure of the interrupt control register 1 and Figure 2.2.12 shows the structure of the interrupt control register 2. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1,” and the interrupt request is not accepted. When an interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (at interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. Fig. 2.2.11 Structure of interrupt control register 1 b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 3E16] B Name Functions At resetRW Interrupt control register 1

0 INT0 interrupt enable

0 : Interrupts disabled 1 : Interrupts enabled

1 INT1 interrupt enable

0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

2–26 3820 GROUP USER’S MANUAL Fig. 2.2.12 Structure of interrupt control register 2 b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 3F16] B Name Functions At resetRW Interrupt control register 2 0 : Interrupts disabled 1 : Interrupts enabled

3 INT2 interrupt enable

7 Fix this bit to “0.” 0 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

2–273820 GROUP USER’S MANUAL (4) Processor status register The processor status register is an 8-bit register. Figure 2.2.13 shows the structure of the processor status register. Bit 2 related to an interrupt is described below. n Interrupt disable flag : bit 2 The interrupt disable flag controls the acceptance of interrupt requests except BRK instruction inter- rupt. When this flag is “1,” the acceptance of an interrupt request is disabled. When this flag is “0,” the acceptance of an interrupt request is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,” so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. Fig. 2.2.13 Structure of processor status register b7 b2 b0 Processor status register (PS) B Flag name Processor status register

0 C : Carry flag

1 Z : Zero flag

2 I : Interrupt disable flag

3 D : Decimal mode flag

4 B : Break flag

5 T : Index X mode flag

6 V : Overflow flag

7 N : Negative flag

indicates initial value immediately after reset b7 b0

2–28 3820 GROUP USER’S MANUAL Fig. 2.2.14 Structure of interrupt edge selection register The INT interrupt requests occur by detecting a level change of each INT pin (INT0–INT3). (1) Active edge selection As an active edge, falling edge ( ) detection or rising edge ( ) detection can be selected by bits 0 to 3 of the interrupt edge selection register (address 003A16). In the “0” state, the falling edge of the corresponding pin is detected. In the “1” state, the rising edge of the corresponding pin is detected. The pins INT 0 to INT3 are also used as I/O ports P42, P43, P57, and P60, but no register to switch between INT pin and I/O port is available. When the port is an input port, the active edges of the port are always detected. Accordingly, when using ports P42, P43, P57 and P60 as input ports, put the corresponding INT interrupt into the disabled state. If this interrupt is not disabled, an INT interrupt is caused by pin level change, so that the program runs away. Figure 2.2.14 shows the structure of the interrupt edge selection register. b7b6 b5b4b3 b2b1b0 Interrupt edge selection register (INTEDGE) [Address 3A16] B Name Functions At reset R W Interrupt edge selection register 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. to 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active

2–293820 GROUP USER’S MANUAL The Key input interrupt request occurs when an “L” level voltage is applied to the pin set for the input mode of the port P2. For interrupt sources except the INT interrupts and the Key input interrupt, refer to “CHAPTER 1” . (1) Connection example when the Key input interrupt is used When using the Key input interrupt, after set ports P2 0 to P23 for the input mode, configure an “L” level valid key-matrix. Figure 2.2.15 shows a connection example when the key input interrupt is used, and a port P2 block diagram. In the connection example in Figure 2.2.15, an Key input interrupt request is caused by pressing the key corresponding to one of ports P20 to P23. Fig. 2.2.15 Connection example when key input interrupt is used, and port P2 block diagram ]1: P-channel transistor for pull-up ]2: CMOS output buffer Port P20 latch Port P2 direction register, b0 = “0” ]1 ]2 Port P21 latch Port P2 direction register, b1 = “0” ]1 ]2 Port P22 latch Port P2 direction register, b2 = “0” ]1 ]2 Port P23 latch Port P2 direction register, b3 = “0”]1 ]2 Port P24 latch\` Port P2 direction register, b4 = “1” ]1 ]2 Port P25 latch Port P2 direction register, b5 = “1” ]1 ]2 Port P26 latch Port P2 direction register, b6 = “1”]1 ]2 Port P27 latch Port P2 direction register, b7 = “1” ]1 ]2 P27 output Port PXx “L” level output PULL register A, b2 = “1” Port P2 input reading circuit Key input interrupt request P26 output P25 output P24 output P23 input P22 input P21 input P20 input

2–30 3820 GROUP USER’S MANUAL (2) Set values of Key input interrupt-related registers When using the Key input interrupt, set the following: l Port P2 direction register (address 000516) l Bit 2 of PULL register A (address 001616) l Bit 5 of interrupt request register 2 (address 003D16) = “0” l Bit 5 of interrupt control register 2 (address 003F16) (Note) = “1” Figure 2.2.16 shows the setting values (corresponding to Figure 2.2.15) of the Key input interrupt- related registers. Note: Fix bit 7 of the interrupt control register 2 (address 003F16) to “0.” PULL register A [Address 1616] P20–P27 pull-up 0 : No pull-up 1 : Pull-up Interrupt request register 2 [Address 3D16] Key input interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 2 [Address 3F16] Key input interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled Port P2 direction register [Address 0516] Bits corresponding to P20–P27 0 : Input port 1 : Output port b7 b0 00001111 b7 b0 b7 b0 b7 b0 : “0” or “1.”

2–313820 GROUP USER’S MANUAL

2.2.6 Notes on use

When using interrupts, note the following. (1) Register setting n Fix bit 7 of the interrupt control register 2 (address 003F16) to “0.” Nothing is allocated for this bit, however, do not write “1” to it. n When using I/O ports P42, P43, P57 and P60 as input ports, put the INT interrupts corresponding to each port into the disabled state. n When the active edges of the following interrupts are switched, the corresponding interrupt request bit may be set to “1.” To avoid accepting an interrupt request, we recommend the register setting example shown in Figure 2.2.17. l INT 0 interrupt to INT3 interrupt l CNTR 0 interrupt and CNTR1 interrupt Fig. 2.2.17 Register setting example ˆ Set the corresponding interrupt enable bit to “0” Set the interrupt active edge Set the corresponding interrupt request bit to “0” Set the corresponding interrupt enable bit to “1” À

3820 GROUP USER’S MANUAL2–32

2.3.1 Explanation of timer X operations

Timer X has 4 modes of operation. Operation in each mode is described below. (1) Timer mode Operation in the timer mode is described below. ‹ Start of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the timer X counter (referred as “the X counter”) is decremented by 1 each time a count source is input. The count source is f(X IN)/16 clock (low-speed mode ; f(XCIN )/16 clock). \` Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “0016.” At this time, the value of the timer X latch (referred as “the X latch”) is transferred (reloaded) to the X counter. ´ Interrupt operation An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the X counter initial value + 1” count of the rising edge of the count source. ˆ Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.1 shows a timer mode operation example.

3820 GROUP USER’S MANUAL 2–33

Fig. 2.3.1 Timer mode operation example Value of timer X counter Timer X interrupt request bit n16 1 : •Clearing by writing “0” to the timer X interrupt request bit.

• Clearing by accepting the timer X interrupt request when the timer X interrupt enable bit is “1.” 000016 Time RL Timer X stop control bit Timer X interrupt enable bit 1 111 Writing “1”Writing “0” Count stop Count source Timer mode operation example
• UF
• RL Count period Count period T(s) = 1 ÷ count source frequency 5 (the X counter initial value + 1) RLRLRL UF UF UF UF T Count restart : Underflow : Reload : The X counter initial value

3820 GROUP USER’S MANUAL2–34

(2) Pulse output mode The operation in the pulse output mode is the same as that in the timer mode, besides, which is added a pulse output operation. In this mode, a pulse whose polarity is reversed at every the X counter underflow is output from the P5 4/CNTR 0 pin. Operation in the pulse output mode is described below. ‹ Start of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the X counter is decremented by 1 each time a count source is input. The count source is f(X IN)/16 clock (low-speed mode ; f(XCIN )/16 clock). \` Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “0016.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ´ Pulse output A pulse whose polarity is reversed every the X counter underflow is output from the P54/CNTR 0 pin. As a level at a start of pulse output, a “H” or “L” is selected by the CNTR0 active edge switch bit. At the time when the pulse output mode is selected by the timer X operating mode bits, a pulse output is started. ˆ Interrupt operation n Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. n Edge of pulse output At the edge of the pulse output from the P54/CNTR 0 pin, an interrupt request occurs. At the same time, the CNTR0 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 0 interrupt enable bit. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR0 active edge switch bit. ˜ Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.2 shows a pulse output mode operation example.

3820 GROUP USER’S MANUAL 2–35

Fig. 2.3.2 Pulse output mode operation example Timer X stop control bit Writing “1”Writing “0” Count source Pulse output mode operation example Count period

• UF
• RL Count period T(s) = 1 ÷ count source frequency 5 (the X counter initial value + 1) ] : When the CNTR 0 active edge switch bit is “1” ;
• The reverse-polarity pulse of above pulse is output.
• The CNTR 0 interrupt request occurs at the rising edge of the output pulse. : Underflow : Reload : The X counter initial value Value of timer X counter CNTR 0 interrupt request bit n16 000016 Time RL CNTR 0 interrupt enable bit Count stopRLRLRL UF UF UF UF T Count restart P54/CNTR 0 pin CNTR 0 active edge switch bit Timer X interrupt request bit Timer X interrupt enable bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Programmable I/O port Select pulse output mode 1 1 1 1 1 1 1 : •Clearing by writing “0” to the timer X interrupt request bit or the CNTR0 interrupt request bit.
• Clearing by accepting the timer X interrupt request and the CNTR0 interrupt request when the respective interrupt enable bits are “1.”

3820 GROUP USER’S MANUAL2–36

(3) Event counter mode The operation in the event counter mode is the same as that in the timer mode except that the input signal to the P54/CNTR 0 pin is used as a count source. Operation in the event counter mode is described below. ‹ Start of count operation Immediately after reset release, the timer X stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the X counter is decremented by 1 each time a count source is input. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR0 active edge switch bit. \` Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “0016.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ´ Interrupt operation n Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer X interrupt enable bit. n Edge of count source At the edge of the count source input from the P5 4/CNTR 0 pin, an interrupt request occurs. At the same time, the CNTR0 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 0 interrupt enable bit. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR0 active edge switch bit. ˆ Stop of count operation By writing “1” to the timer X stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer X stop control bit. Figure 2.3.3 shows an event counter mode operation example.

3820 GROUP USER’S MANUAL 2–37

Fig. 2.3.3 Event counter mode operation example Value of timer X counter CNTR 0 interrupt request bit n16 000016 Time Timer X stop control bit CNTR 0 interrupt enable bit Writing “1”Writing “0” Count stop Count source (P54/CNTR 0 pin) RL UF UF UF UF T Count restart CNTR 0 active edge switch bit Timer X interrupt request bit Timer X interrupt enable bit 11 1 1 1 1 1 1 1 Event counter mode operation example

• UF
• RL Count period Count period T(s) = 1 ÷ count source frequency 5 (the X counter initial value + 1) ] : When the CNTR0 active edge switch bit is “1” ;
• Falling edge of the count source is valid.
• The CNTR 0 interrupt request occurs at the rising edge of the output pulse. 1 : •Clearing by writing “0” to the timer X interrupt request bit or the CNTR0 interrupt request bit.
• Clearing by accepting the timer X interrupt request and the CNTR0 interrupt request when the respective interrupt enable bits are “1.” : Underflow : Reload : The X counter initial value RL RL RL CNTR 0 interrupt request occurs at falling edge of the count source

3820 GROUP USER’S MANUAL2–38

(4) Pulse width measurement mode In the pulse width measurement mode, the width (“H” or “L” level) of a pulse input from the P54/CNTR 0 pin is measured. Operation in the pulse width measurement mode is described below. ‹ Count operation Immediately after reset, the timer X stop control bit is in the “0” state. In this state, a count operation is continued in the period in which the measurement level is input to the P54/CNTR 0 pin. The value of the X counter is decremented by 1 each time a count source is input. The count source is f(X IN)/16 clock (low-speed mode ; f(XCIN )/16 clock). \` Reload operation The X counter underflows at the first count pulse after the value of the X counter reaches “0016.” At this time, the value of the X latch is transferred (reloaded) to the X counter. ´ Pulse width measurement As a pulse measurement period, a “H” or “L” is selected by the CNTR0 active edge switch bit. The difference between the initial value of the X counter and the X counter value at counter stop is a measured pulse width. A reload operation by reading the count value is not performed automatically. Accordingly, to con- tinue the measurement, set the initial value anew by software. When reading a value from the timer X, read both registers in order of the timer X (high–order) and the timer X (low–order). ˆ Interrupt operation n Edge of pulse measured At the edge of the pulse input from the P5 4/CNTR 0 pin, an interrupt request occurs. At the same time, the CNTR0 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 0 interrupt enable bit. The CNTR 0 active edge switch bit specifies an active edge. When “H” level width is measured, the falling edge ( ) is active, when “L” level width is measured, the rising edge ( ) is active. n Counter underflow An interrupt request occurs at the X counter underflow. At the same time, the timer X interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by using the timer X interrupt enable bit. Figure 2.3.4 shows a pulse width measurement mode operation example.

3820 GROUP USER’S MANUAL 2–39

Fig. 2.3.4 Pulse width measurement mode operation example Value of timer X counter CNTR 0 interrupt request bit m 16 000016 Time Timer X stop coutrol bit Count stop Count source H Count start P54/CNTR 0 pin CNTR 0 active edge switch bit n16 Set initial value to counter Count start H 2 2 Pulse width measurment mode operation example

• n : The X counter initial value
• m: The X counter value at count stop Pulse width Pulse width H(s) = 1 ÷ count source frequency 5 (the X counter initial value – the X counter value at count stop) 1 : •Clearing by writing “0” to the CNTR0 interrupt request bit.
• Clearing by accepting the CNTR0 interrupt request when the CNTR0 interrupt enable bit is “1.” 2 : Set initial value to the timer X when timer X write control bit is “0.” Set initial value to counter CNTR 0 interrupt enable bit Timer X interrupt request bit Timer X interrupt enable bit ] : When the CNTR0 active edge switch bit is “1” ;
• “L” level width of the input pulse is measured.
• The CNTR 0 interrupt request occurs at the rising edge of the input pulse.

3820 GROUP USER’S MANUAL2–40

(5) Real time port control The real time port control is the function which outputs preset data from the real time ports in synchronization with an underflow of the X coun- ter. Table 2.3.1 shows real time ports and bits for storing data. This real time port control func- tion is available in every mode. A data output from the real time port is started at setting the real time port control bit to “1” (when setting “1” to the real time port control bit of the timer X mode register, use the SEB instruction). When the data for real time port is rewritten, the rewritten values are output at the first underflow of the X counter after rewritting. Figure 2.3.5 shows a timer mode operation example with the real time port function. The real time port is also used as port P6 0 and P6 1. When using the real time port, set the corresponding bit of the port P6 direction reg- ister (address 000D 16) to “1” for the output mode. Table 2.3.1 Real time ports and bits for storing data Real time port RTP 0 (P60) RTP 1 (P61) Bit for storing data Bit 2 of timer X mode register Bit 3 of timer X mode register

3820 GROUP USER’S MANUAL 2–41

Fig. 2.3.5 Timer mode operation example with real time port function Value of timer X counter n16 000016 Time RL Timer X stop control bit Count source Timer mode operation example with real time port function

• UF
• RL RLRLRL UF UF UF UF Bit 2 of timer X mode register P60/INT3/RTP0 pin Real time port control bit mode register P61/RTP1 pin Rewrite Rewrite RewriteRewriteRewrite Programmable I/O port 1 : In the case that following are set immediately after reset release, “0” is output from pins P60/INT3/RTP0 and P62/RTP1.
• Set ports P60 and P61 for the output mode.
• Set the real time port control bit to “1.” Programmable I/O port : Underflow : Reload : The X counter initial value Bit 3 of timer X

3820 GROUP USER’S MANUAL2–42

2.3.2 Explanation of timer Y operations

Timer Y has 4 modes of operation. Operation in each mode is described below. (1) Timer Mode Operation in the timer mode is described below. ‹ Start of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the timer Y counter (referred as “the Y counter”) is decremented by 1 each time a count source is input. The count source is f(X IN)/16 clock (low-speed mode ; f(XCIN )/16 clock). \` Reload operation The Y counter underflows at the first count pulse after the value of the Y counter reaches “0016.” At this time, the value of the timer Y latch (referred as “the Y latch”) is transferred (reloaded) to the Y counter. ´ Interrupt operation An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the Y counter initial value + 1” count of the rising edge of the count source. ˆ Stop of count operation By writing “1” to the timer Y stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set to the timer Y stop control bit. Figure 2.3.6 shows a timer mode operation example.

3820 GROUP USER’S MANUAL 2–43

Fig. 2.3.6 Timer mode operation example Value of timer Y counter Timer Y interrupt request bit n16 000016 Time RL Timer Y stop control bit Timer Y interrupt enable bit 1 111 Writing “1”Writing “0” Count stop Count source Timer mode operation example

• UF
• RL Count period Count period T(s) = 1 ÷ count source frequency 5 (the Y counter initial value + 1) RLRLRL UF UF UF UF T Count restart : Underflow : Reload : The Y counter initial value 1 : •Clearing by writing “0” to the timer Y interrupt request bit.
• Clearing by accepting the timer Y interrupt request when the timer Y interrupt enable bit is “1.”

3820 GROUP USER’S MANUAL2–44

(2) Period measurement mode In the period measurement mode, the period of a pulse input from the P55/CNTR 1 pin is measured. Operation in the period measurement mode is described below. ‹ Start of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. The count source is f(XIN)/16 clock (low-speed mode ; f(XCIN )/16 clock). \` Reload operation At the edge of the pulse input from the P55/CNTR 1 pin, the value of the Y latch is transferred (reloaded) to the Y counter. The count value immediately before reload is held until it is read out once after reload. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR 1 active edge switch bit. The value of the Y latch is also reloaded at the Y counter underflow. ´ Period measurement As a period measurement duration, the following is selected by the CNTR1 active edge switch bit (bit 6) : Duration from the falling edge to the falling edge (bit 6 = “0”) Duration from the rising edge to the rising edge (bit 6 = “1”) The difference between the count value at an active edge input and that immediately before reload is a measured period. ˆ Interrupt operation n Edge of input pulse At the edge of the pulse input from the P5 5/CNTR 1 pin, an interrupt request occurs. At the same time, the CNTR1 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 1 interrupt enable bit. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR1 active edge switch bit. n Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. Figure 2.3.7 shows a period measurement mode operation example.

3820 GROUP USER’S MANUAL 2–45

Fig. 2.3.7 Period measurement mode operation example TimeT RL RLRL T 1 1 1 Value of timer Y counter CNTR 1 interrupt request bit m 16 000016 Timer Y stop control bit Count source P55/CNTR 1 pin CNTR 1 active edge switch bit n16 Period measurement mode operation example

• RL Pulse period Pulse period T(s) = 1 ÷ count source frequency 5 (the Y counter initial value – the Y counter value immediately before reload ) 1 : •Clearing by writing “0” to the CNTR1 interrupt request bit.
• Clearing by accepting the CNTR1 interrupt request when the CNTR1 interrupt enable bit is “1.” CNTR 1 interrupt enable bit Timer Y interrupt request bit Timer Y interrupt enable bit : Reload : The Y counter initial value : The Y counter value immediately before reload ] : When the CNTR 1 active edge switch bit is “1” ;
• From the rising edge to the rising edge of the input pulse is measured.
• The CNTR 1 interrupt request occurs at the rising edge of the input pulse.

3820 GROUP USER’S MANUAL2–46

(3) Event counter mode The operation in the event counter mode is the same as that in the timer mode except that the input signal to the P55/CNTR 1 pin is used as a count source. Operation in the event counter mode is described below. ‹ Start of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR1 active edge switch bit. \` Reload operation The Y counter underflows at the first count pulse after the value of the Y counter reaches “0016.” At this time, the value of the Y latch is transferred (reloaded) to the Y counter. ´ Interrupt operation n Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. n Edge of count source At the edge of the count source input from the P55/CNTR 1 pin, an interrupt request occurs. At the same time, the CNTR1 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 1 interrupt enable bit. As an active edge, the falling edge ( ) or rising edge ( ) is specified by the CNTR1 active edge switch bit. ˆ Stop of count operation By writing “1” in the timer Y stop control bit by software, the count operation is stopped. The count operation is continued until “1” is set in the timer Y stop control bit. Figure 2.3.8 shows an event counter mode operation example.

3820 GROUP USER’S MANUAL 2–47

Fig. 2.3.8 Event counter mode operation example Value of timer Y counter CNTR 1 interrupt request bit n16 000016 Time RL Timer Y stop control bit CNTR 1 interrupt enable bit Writing “1”Writing “0” Count stop Count source (P55/CNTR 1 pin) RLRLRL UF UF UF UF T Count restart CNTR 1 active edge switch bit Timer Y interrupt request bit Timer Y interrupt enable bit CNTR 0 interrupt request occurs at falling edge of the count source 11 1 1 1 1 1 1 1 Event counter mode operation example

• UF
• RL Count period Count period T(s) = 1 ÷ count source frequency 5 (the Y counter initial value + 1) ] : When the CNTR1 active edge switch bit is “1” ;
• Falling edge of the count source is valid.
• The CNTR 1 interrupt request occurs at the rising edge of the output pulse. 1 : •Clearing by writing “0” to the timer Y interrupt request bit or the CNTR1 interrupt request bit.
• Clearing by accepting the timer Y interrupt request and the CNTR1 interrupt request when the respective interrupt enable bits are “1.” : Underflow : Reload : The Y counter initial value

3820 GROUP USER’S MANUAL2–48

(4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the width (“H” and “L” level) of pulses input from the P55/CNTR 1 pin are continuously measured. With the exception that reload and an interrupt request occur at both edges of pulses input from the 5/CNTR 1 pin, the operation in the pulse width HL continuously measurement mode is the same as that in the period measurement mode. The pulse width HL continuously measurement mode of operation is described below. ‹ Start of count operation Immediately after reset release, the timer Y stop control bit is in the “0” state. For this reason, the count operation is automatically started after reset release. The value of the Y counter is decremented by 1 each time a count source is input. The count source is f(X IN)/16 (low-speed mode ; f(XCIN )/16). \` Reload operation At both edges of the pulse input from the P55/CNTR 1 pin, the value of the timer Y is transferred (reloaded) to the Y counter. The count value immediately before reload is held until it is read out once after reload. The value of the Y latch is also reloaded at the Y counter underflow. ´ Pulse width measurement The difference between the count value at an active edge input and that immediately before reload is a measured pulse width. When reading a value from the timer Y, read both registers in order of the timer Y (high–order) and the timer Y (low–order). ˆ Interrupt operation n Edge of input pulse At both edges of pulses input from the P5 5/CNTR 1 pin, an interrupt request occurs. At the same time, the CNTR1 interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the CNTR 1 interrupt enable bit. n Counter underflow An interrupt request occurs at the Y counter underflow. At the same time, the timer Y interrupt request bit is set to “1.” The occurrence of an interrupt is controlled by the timer Y interrupt enable bit. Figure 2.3.9 shows a pulse width HL continuously measurement mode operation example.

3820 GROUP USER’S MANUAL 2–49

Fig. 2.3.9 Pulse width HL continuously measurement mode operation example TimeH RL RLRL H 1 1 1 Value of timer Y counter CNTR 1 interrupt request bit m 16 000016 Timer Y stop control bit Count source P55/CNTR 1 pin CNTR 1 active edge switch bit n16 Operation example in pulse width HL continuously measurement mode

• RL Pulse width Pulse width H(s) = 1 ÷ count source frequency 5 (the Y counter initial value – the Y counter value immediately before reload) 1 : •Clearing by writing “0” to the CNTR1 interrupt request bit.
• Clearing by accepting the CNTR1 interrupt request when the CNTR1 interrupt enable bit is “1.” CNTR 1 interrupt enable bit Timer Y interrupt request bit Timer Y interrupt enable bit : Reload : The Y counter initial value : The Y counter value immediately before reload

3820 GROUP USER’S MANUAL2–50

2.3.3 Related registers

Figure 2.3.10 shows the memory allocation of the timer X- and timer Y-related registers. Each of these registers is described below. Fig. 2.3.10 Memory allocation of timer X- and timer Y-related registers Address Port P5 direction register (P5D)000B16

002016 Timer X (low-order) (TXL)

Timer X mode register (TXM) Timer Y mode register(TYM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 002216 002316 002116 003C 16 003D 16 003E16 003F16 Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) 002716 002816 Port P6 direction register (P6D)000D 16

2–513820 GROUP USER’S MANUAL (1) Port P5 direction register (P5D) The port P5 direction register (address 000B16) selects the I/O direction of port P5. Figure 2.3.11 shows the structure of the port P5 direction register. The CNTR 0 pin is also used as P54, while the CNTR1 pin is also used as P55. n Timer X In the pulse output mode, set bit 4 to “1” for the output mode. In the event counter mode or the pulse width measurement mode, set bit 4 to “0” for the input mode. n Timer Y In the period measurement mode or the event counter mode or the pulse width HL continuously measurement mode, set bit 5 to “0” to set it for the input mode. Fig. 2.3.11 Structure of port P5 direction register Note : Port P5 direction register cannot be read out. b7 b6b5b4 b3b2b1 b0 Port P5 direction register (P5D) [Address 0B16] B Name Functions At reset R W Port P5 direction register Port P5 direction register 0 : Port P5 0 input mode 1 : Port P50 output mode P55 CNTR 1 P56 TOUT P57 INT2 P54 CNTR 0 P53 SRDY2 P52 SCLK2 P51 SOUT2 P50 SIN2 0 : Port P51 input mode 1 : Port P51 output mode 0 : Port P52 input mode 1 : Port P52 output mode 0 : Port P53 input mode 1 : Port P53 output mode 0 : Port P54 input mode 1 : Port P54 output mode 0 : Port P55 input mode 1 : Port P55 output mode 0 : Port P56 input mode 1 : Port P56 output mode 0 : Port P57 input mode 1 : Port P57 output mode

3820 GROUP USER’S MANUAL2–52

(2) Port P6 direction register (P6D) The port P6 direction register (address 000D16) selects the I/O direction of port P6. Figure 2.3.12 shows the structure of the port P6 direction register. n Timer X The real time port RTP0 pin is also used as P60, while the RTP1 pin is also used as P61. To use as the RTP0 pin, set bit 0 to “1” for the output mode. To use as the RTP1 pin, set bit 1 to “1” for the output mode. Fig. 2.3.12 Structure of port P6 direction register Note : Port P6 direction register cannot be read out. b7 b6b5b4 b3b2b1 b0 Port P6 direction register (P6D) [Address 0D16] B Name Functions At reset R W Port P6 direction register to Port P6 direction register 0 : Port P6 0 input mode 1 : Port P60 output mode P60 RTP 0 INT3 P61 RTP 1 0 : Port P61 input mode 1 : Port P61 output mode Nothing is allocated. These bits cannot be written to and be read out. × ×

2–533820 GROUP USER’S MANUAL Fig. 2.3.13 Structure of timer X latch (3) Timer X latch and timer X counter (TXL and TXH) The timer X latch (referred as “the X latch”) and the timer X counter (referred as “the X counter”) consist of 16 bits in a combination of high-order (address 002116) and low-order (address 002016). The X latch and the X counter are allocated at the same address. To access the X latch and the X counter, access both the timer X (low-order) and the timer X (high-order). n Read When the timer X (high-order) and the timer X (low-order) are read out, the value of the X counter (count value) are read out. Read both registers in the order of the timer X (high-order) and the timer X (low-order). Do not write any value to the timer X (high-order) and the timer X (low-order) before the timer X (low- order) has been read out. In this case, timer X will not operate normally. n Write When a value is written to the timer X (low-order) and the timer X (high-order), the value is set in the X latch and the X counter at the same time. Writing to the X latch only can be selected by the timer X write control bit (refer to “2.3.3 Related registers, (5) Timer X mode register”). Write the values to both registers in the order of the timer X (low-order) and the timer X (high-order). Do not read timer X (low-order) and the timer X (high-order) before the timer X (high-order) has been written. In this case, timer X will not operate normally. l Timer X latch The X latch is a register which holds the value to be transferred (reloaded) automatically to the X counter as the initial value of the X counter at the X counter underflow. Figure 2.3.13 shows the structure of the timer X latch. The contents of the X latch cannot be read out. Note : Write both registers in the order of TXL and TXH. b7b6 b5b4b3 b2b1b0 Timer X (high-order, low-order) (TXH, TXL) [Address 2116, 2016] B Functions At reset R W Timer X (high-order, low-order) to

• Set “000016 to FFFF16” as timer X count value.
• Write high-order byte of setting value to TXH, and low-order byte to TXL, respectively.
• The values of TXH and TXL are set to the respective X latches and transferred auto- matically to the respective X counters at the X counter underflow. l Timer X latch

3820 GROUP USER’S MANUAL2–54

The X counter counts the count source. Figure 2.3.14 shows the structure of the timer X counter. The contents of the X counter are decremented by 1 each time a count source is input. The division ratio of the counter is represented by the following expression. Division ratio of the X counter = Fig. 2.3.14 Structure of timer X counter the X counter initial value + 1 Notes 1 : Write both registers in the order of TXL and TXH. b7b6 b5b4b3 b2b1b0 Timer X (high-order, low-order) (TXH, TXL) [Address 2116, 2016] B Functions At reset R W Timer X (high-order, low-order) to

• Set “000016 to FFFF16” as timer X count value.
• The value of the X counter is decremented by 1 each time a count source is input.
• When the timer X write control bit is “0,” the values of TXH and TXL are set to the respec- tive X latches at the same time.
• The values of each X counter are read out by reading the respective timer Xs. l Timer X counter 2 : Read both registers in the order of TXH and TXL.

2–553820 GROUP USER’S MANUAL Fig. 2.3.15 Structure of timer Y latch (4) Timer Y latch and timer Y counter (TYL and TYH) The timer Y latch (referred as “the Y latch”) and the timer Y counter (referred as “the Y counter”) consist of 16 bits in a combination of high-order (address 002316) and low-order (address 002216). The Y latch and Y counter are allocated at the same address. To access the Y latch and the Y counter, access both the timer Y (low-order) and the timer Y (high-order). n Read When the timer Y (high-order and low-order) are read out, the value of the Y counter (count value) are read out. Read both registers in the order of the timer Y (high-order) and the timer Y (low-order). Do not write any value to the timer Y (high-order and low-order) before the timer Y (low-order) has been read out. In this case, timer Y will not operate normally. n Write When a value is written to the timer Y (low-order and high-order), the value is set in the Y latch and the Y counter at the same time. Write the values to both registers in the order of the timer Y (low- order) and the timer Y (high-order). Do not read the timer Y (low-order and high-order) before the timer Y (high-order) has been written. In this case, timer Y will not operate normally. l Timer Y latch The Y latch is a register which holds the value to be transferred (reloaded) automatically to the Y latch as the initial value of the Y counter at the Y counter underflow. Figure 2.3.15 shows the structure of the timer Y latch. Reload is performed at the following :

• At the Y counter underflow
• At the edge of the input pulse from the P5 5/CNTR 1 pin (period measurement mode/pulse width HL coutinuously measurement mode) The contents of the Y latch cannot be read out. Note : Write both registers in the order of TYL and TYH. b7b6 b5b4b3 b2b1b0 Timer Y (high-order, low-order) (TYH, TYL) [Address 2316, 2216] B Functions At reset R W Timer Y (high-order, low-order) to
• Set “000016 to FFFF16” as timer Y count value.
• Write high-order byte of setting value to TYH, and low-order byte to TYL, respectively.
• The values of TYH and TYL are set to the respective Y latches and transferred auto- matically to the respective Y counters at the Y counter underflow. l Timer Y latch

3820 GROUP USER’S MANUAL2–56

The Y counter counts the count source. Figure 2.3.16 shows the structure of the timer Y counter. The contents of the Y counter are decremented by 1 each time a count source is input. The division ratio of the counter is represented by the following expression. Division ratio of the Y counter = In the period measurement mode or the pulse width HL coutinuously measurement mode, the value immediately before reload is held until it is read out once after reload. The count operation is coutinued. Fig. 2.3.16 Structure of timer Y counter the Y counter initial value + 1 b7b6 b5b4b3 b2b1b0 Timer Y (high-order, low-order) (TYH, TYL) [Address 2316, 2216] B Functions At reset R W Timer Y (high-order, low-order) to

• Set “000016 to FFFF16” as timer Y count value.
• The value of the Y counter is decremented by 1 each time a count source is input.
• The values of each Y counter are read out by reading the respective timer Ys.
• The Y counter value immediately before reload is held until it is read out once after reload. (period measurement mode/pulse width HL continuously measurement mode) l Timer Y counter Notes 1 : Write both registers in the order of TYL and TYH. 2 : Read both registers in the order of TYH and TYL.

2–573820 GROUP USER’S MANUAL (5) Timer X mode register (TXM) The timer X mode register (address 002716) consists of bits which select operation or control counting. Figure 2.3.17 shows a structure of the timer X mode register. Each bit is described below. Fig. 2.3.17 Structure of timer X mode register b7b6 b5b4b3 b2b1b0 Timer X mode register (TXM) [Address 2716] B Name Functions At reset R W Timer X mode register Timer X write control bit 0 : Count start 1 : Count stop 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit P60 data for real time port P61 data for real time port Timer X operating mode bits CNTR 0 active edge switch bit Timer X stop control bit 0 : Real time port function invalid 1 : Real time port function valid 0 : “L” level output 1 : “H” level output 0 : “L” level output 1 : “H” level output 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode

• CNTR 0 interrupt 0 : Falling edge active 1 : Rising edge active
• Pulse output mode 0 : Start at initial level “H” output 1 : Start at initial level “L” output
• Event counter mode 0 : Rising edge active 1 : Falling edge active
• Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width b5b4

3820 GROUP USER’S MANUAL2–58

n Timer X write control bit (bit 0) The timer X write control bit controls writing to the timer X (low-order and high-order). When bit 0 is “0,” the value written in the timer X (low-order and high-order) are set into both the X latch and the X counter at the same time. When bit 0 is “1,” the value written in the timer X (low-order and high-order) is set into the X latch only. When a value is written into the X latch only, this rewritten value is transferred to the X counter at the first X counter underflow after rewriting. n Real time port control bit (bit 1) The real time port control bit selects a function to output data from the real time port. When bit 1 is “0,” this function is invalid. When the bit is “1,” this function is valid. For an explanation of operations, refer to “2.3.1 Explanation of timer X operations, (5) Real time port control.” n Data for real time port (bit 2 and bit 3) The data for real time port is the data to be output from the real time port. n Timer X operating mode bits (bit 4 and bit 5) The timer X operating mode bits select a operating mode of the timer X. Table 2.3.2 shows the relation between the timer X operating mode bits and the operating modes. For an explanation of each mode operation, refer to the section pertaining to the explanation of each operation. Table 2.3.2 Relation between timer X operating mode bits and operating modes b5 b4 0 0 0 1 1 0 1 1 Operation mode Timer mode Pulse output mode Event counter mode Pulse width measurement mode

2–593820 GROUP USER’S MANUAL n CNTR 0 active edge switch bit (bit 6) The CNTR 0 active edge switch bit has a function which selects an active edge of the CNTR0 interrupt, and functions for each mode. l CNTR 0 interrupt When bit 6 is “0,” the falling edge ( ) is active. When bit 6 is “1,” the rising edge ( ) is active. l Pulse output mode In the pulse output mode, the initial level at the start of pulse output is selected. When bit 6 is “0,” the initial level is “H.” When bit 6 is “1,” the initial level is “L.” l Event counter mode An active edge of the count source is selected. When bit 6 is “0,” the rising edge ( ) is active. When bit 6 is “1,” the falling edge ( ) is active. l Pulse width measurement mode A duration of pulse width measured is selected. When bit 6 is “0,” the “H” level width is measured. When bit 6 is “1,” the “L” level width is measured. n Timer X stop control bit (bit 7) The timer X stop control bit controls the count operation of the timer X. By writing “0” to bit 7, a count source is input to the X counter, so that a count operation is started. As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started after reset release. By writing “1” to bit 7, the input of count source to the X counter is stopped, so that the count operation stops. In the pulse width measurement mode, however, a count operation is performed only in the period in which the measurement level is input to the P5 4/CNTR 0 pin when bit 7 is in the “0” state. At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the X counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in the stop state.

3820 GROUP USER’S MANUAL2–60

(6) Timer Y Mode Register (TYM) The timer Y mode register (address 002816) consists of bits which select operation or control counting. Figure 2.3.18 shows a structure of the timer Y mode register. Each bit is described below. Fig. 2.3.18 Structure of timer Y mode register b7b6 b5b4b3 b2b1b0 Timer Y mode register (TYM) [Address 2816] B Name Functions At reset R W Timer Y mode register to Nothing is allocated. These bits cannot be written and are fixed to “0” at reading. Timer Y operating mode bits CNTR 1 active edge switch bit Timer Y stop control bit 0 : Count start 1 : Count stop 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode

• CNTR 1 interrupt 0 : Falling edge active 1 : Rising edge active
• Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge
• Event counter mode 0 : Rising edge active 1 : Falling edge active b5b4 0 ×

2–613820 GROUP USER’S MANUAL Table 2.3.3 Relation between timer Y operating mode bits and operating modes b5 b4 0 0 0 1 1 0 1 1 Operation mode Timer mode Period measurement mode Event counter mode Pulse width HL continuously measurement mode n Timer Y operating mode bits (bit 4 and bit 5) The timer Y operating mode bits select a op- erating mode of the timer Y. Table 2.3.3 shows the relation between the timer Y operating mode bits and the operating modes. For an explanation of each mode operation, refer to the section pertaining to the explana- tion of each operation. n CNTR 1 active edge switch bit (bit 6) The CNTR 1 active edge switch bit has a function which selects an active edge of the CNTR1 interrupt and functions for each mode. In the pulse width HL continuously measurement mode, this bit is invalid. l CNTR 1 interrupt When bit 6 is “0,” the falling edge ( ) is active. When bit 6 is “1,” the rising edge ( ) is active. In the pulse width HL continuously measurement mode, an interrupt request occurs at the both edges regardless of the value of this bit. l Period measurement mode This bit selects the duration which is measured. When bit 6 is “0,” the falling edge to the falling edge duration is measured. When bit 6 is “1,” the rising edge to the rising edge duration is measured. l Event counter mode An active edge of the count source is selected. When bit 6 is “0,” the rising edge ( ) is active. When bit 6 is “1,” the falling edge ( ) is active. n Timer Y stop control bit (bit 7) The timer Y stop control bit controls the count operation of the timer Y. By writing “0” to bit 7, a count source is input to the Y counter, so that a count operation is started. As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started after reset release. By writing “1” to bit 7, the input of count source to the Y counter is stopped, so that the count operation stops. At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in the stop state.

3820 GROUP USER’S MANUAL2–62

(7) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16) indicate whether an interrupt request has occured or not. Figure 2.3.19 shows the structure of the interrupt request register 1 and Figure 2.3.20 shows the structure of the interrupt request register 2. The occurrence of an interrupt request (timer X, timer Y, CNTR 0, and CNTR 1 interrupt requests) causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the corresponding interrupt enable bit (refer to the next item). For details of interrupts, refer to “2.2 Interrupts.” Fig. 2.3.19 Structure of interrupt request register 1 b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 3C16] B Name Functions At reset R W Interrupt request register 1 0 0 : No interrupt request issued 1 : Interrupt request issued 0 ]INT0 interrupt request bit ] : “0” can be set by software, but “1” cannot be set. 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

2–633820 GROUP USER’S MANUAL Fig. 2.3.20 Structure of interrupt request register 2 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 3D16] B Name Functions At resetRW Interrupt request register 2 0 : No interrupt request issued 1 : Interrupt request issued ] : “0” can be set by software, but “1” cannot be set. 7 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

3820 GROUP USER’S MANUAL2–64

(8) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F16) control each interrupt request source. Figure 2.3.21 shows the structure of the interrupt control register 1 and Figure 2.3.22 shows the structure of the interrupt control register 2. When an interrupt enable bit (timer X, timer Y, CNTR 0, and CNTR 1 interrupt enable bits) is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit only is set to “1,” and the interrupt request is not accepted. When the interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. For details of interrupts, refer to “2.2 Interrupts.” Fig. 2.3.21 Structure of interrupt control register 1 b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 3E16] B Name Functions At resetRW Interrupt control register 1 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

2–653820 GROUP USER’S MANUAL Fig. 2.3.22 Structure of interrupt control register 2 b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 3F16] B Name Functions At resetRW Interrupt control register 2 0 : Interrupts disabled 1 : Interrupts enabled 7 Fixed this bit to “0.” 0 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

3820 GROUP USER’S MANUAL2–66

2.3.4 Register setting example

In the following, an example of setting registers for using each mode of the timer X and timer Y is described. (1) Timer X n Timer mode Figure 2.3.23 shows an example of setting registers for using the timer mode. Fig. 2.3.23 Example of setting registers for using timer mode TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b7 b0 À Setting of timer X mode register Select timer mode or others b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid \` Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ´ Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the timer X interrupt enable bit and the timer X interrupt request bit to “0.”
• After setting ˆ below, set the timer X interrupt enable bit to “1” (interrupts enabled). 2: Write values in the order of the timer X (low-order) and the timer X (high-order). b2 : P60 data for real time port b3 : P61 data for for real time port b5, b4 : Timer X operating mode bits 0 0 : Timer mode b6 : CNTR0 active edge switch bit b7 : Timer X stop control bit 1 : Count stop ˆ Set timer X stop control bit of timer X mode register to “0” to start counting

2–673820 GROUP USER’S MANUAL Fig. 2.3.24 Example of setting registers for using pulse output mode n Pulse output mode Figure 2.3.24 shows an example of setting registers for using the pulse output mode. P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b4 : Bit corresponding to port P54 1 : Output mode ˜ Set timer X stop control bit of timer X mode register to “0” to start counting ´ Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ˆ Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b7 b0 \` Setting of timer X mode register Select pulse output mode or others b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P60 data for real time port b3 : P61 data for real time port b5, b4 : Timer X operating mode bits 0 1 : Pulse output mode b6 : CNTR 0 active edge switch bit 0 : Start at initial level “H” level output 1 : Start at initial level “L” level output b7 : Timer X stop control bit 1 : Count stop [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer X or CNTR0) and the interrupt request bits (timer X or CNTR0) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled). 2: Write values in the order of the timer X (low-order) and the timer X (high-order).

3820 GROUP USER’S MANUAL2–68

Fig. 2.3.25 Example of setting registers for using event counter mode n Event counter output mode Figure 2.3.25 shows an example of setting registers for using the event counter mode. P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b4 : Bit corresponding to port P54 0 : Input mode ˜ Set timer X stop control bit of timer X mode register to “0” to start counting ´ Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ˆ Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b7 b0 \` Setting of timer X mode register Select event counter mode or others b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P60 data for real time port b3 : P61 data for real time port b5, b4 : Timer X operating mode bits 1 0 : Event counter mode b6 : CNTR 0 active edge switch bit 0 : Rising edge active 1 : Falling edge active b7 : Timer X stop control bit 1 : Count stop [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer X or CNTR0) and the interrupt request bits (timer X or CNTR0) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled). 2: Write values in the order of the timer X (low-order) and the timer X (high-order).

2–693820 GROUP USER’S MANUAL Fig. 2.3.26 Example of setting registers for using pulse width measurement mode n Pulse width measurement mode Figure 2.3.26 shows an example of setting registers for using the pulse width measurement mode. P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b4 : Bit corresponding to port P54 0 : Input mode ˜ Set timer X stop control bit of timer X mode register to “0” to start counting ´ Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ˆ Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b7 b0 \` Setting of timer X mode register Select pulse width measurement mode or others b1 : Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid b2 : P60 data for real time port b3 : P61 data for real time port b5, b4 : Timer X operating mode bits 1 1 : Pulse width measurement mode b6 : CNTR 0 active edge switch bit 0 : Measure “H” level width 1 : Measure “L” level width b7 : Timer X stop control bit 1 : Count stop [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer X or CNTR0) and the interrupt request bits (timer X or CNTR0) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR0) to “1” (interrupts enabled). 2: Write values in the order of the timer X (low-order) and the timer X (high-order).

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Figure 2.3.27 shows an example of setting registers for using the real time port (referred as RTP) function. Fig. 2.3.27 Example of setting registers for using RTP P6D : Port P6 direction register [Address 0D16] À Port P6 direction register b7 b0 b0, b1 : Bits corresponding to ports P60 (RTP0) and P61 (RTP1) 0 : Input mode 1 : Output mode ˜ Set timer X stop control bit of timer X mode register to “0” to start counting ´ Set count value (low-order) to timer X (low-order) (TXL) [Address 2016] ˆ Set count value (high-order) to timer X (high-order) (TXH) [Address 2116] TXM : Timer X mode register [Address 2716] b0 : Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only b7 b0 \` Setting of timer X mode register Select RTP or others b1 : Real time port control bit 1 : Real time port function valid b2 : P60 data for real time port b3 : P61 data for real time port b5, b4 : Timer X operating mode bits 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode b6 : CNTR 0 active edge switch bit

• CNTR0 interrupt 0 : Falling edge active 1 : Rising edge active
• Pulse output mode 0 : Start at initial level “H” output 0 : Start at initial level “L” output
• Event counter mode 0 : Rising edge active 1 : Falling edge active
• Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width b7 : Timer X stop control bit 1 : Count stop [Notes on use] Notes 1: After reset release, port P6 direction register is set for the input mode, so pins P60/INT3/RTP0 and P61/RTP1 operate as ordinary input ports. For using as RTP, be sure to set the corresponding bits of the port P6 direction register for the output mode. 2: Change RTP output data as required, for example, by using an interrupt. 3: Do not change ports P60 and P61 selected as RTP into input pins during RTP operation. : Nothing is allocated

2–713820 GROUP USER’S MANUAL (2) Timer Y n Timer mode Figure 2.3.28 shows an example of setting registers for using the timer mode. Fig. 2.3.28 Example of setting registers for using timer mode ˆ Set timer Y stop control bit of timer Y mode register to “0” to start counting TYM : Timer Y mode register [Address 2816] b7 b0 À Setting of timer Y mode register Select timer mode or others \` Set count value (low-order) to timer Y (low-order) (TYL) [Address 2216] ´ Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] b5, b4 : Timer Y operating mode bits 0 0 : Timer mode b6 : CNTR1 active edge switch bit b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated 001 [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the timer Y interrupt enable bit and the timer Y interrupt request bit to “0.”
• After setting ˆ below, set the timer Y interrupt enable bit to “1” (interrupts enabled) . 2: Write values in the order of the timer Y (low-order) and the timer Y (high-order).

3820 GROUP USER’S MANUAL2–72

Fig. 2.3.29 Example of setting registers for using period measurement mode n Period measurement mode Figure 2.3.29 shows an example of setting registers for using the period measurement mode. P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b5 : Bit corresponding to port P55 0 : Input mode ˜ Set timer Y stop control bit of timer Y mode register to “0” to start counting ´ Set count value (low-order) to timer Y (low-order) (TYL) [Address 2216] ˆ Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] TYM : Timer Y mode register [Address 2816] b7 b0 \` Setting of timer Y mode register Select period measurement mode or others b5, b4 : Timer Y operating mode bits 0 1 : Period measurement mode b6 : CNTR1 active edge switch bit 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated 101 [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR1) to “1” (interrupts enabled). 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order).

2–733820 GROUP USER’S MANUAL Fig. 2.3.30 Example of setting registers for using event counter mode n Event counter mode Figure 2.3.30 shows an example of setting registers for using the event counter mode. P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b5 : Bit corresponding to port P55 0 : Input mode ˜ Set timer Y stop control bit of timer Y mode register to “0” to start counting ´ Set count value (low-order) to timer Y (low-order) (TYL) [Address 2216] ˆ Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] TYM : Timer Y mode register [Address 2816] b7 b0 \` Setting of timer Y mode register Select event counter mode or others b5, b4 : Timer Y operating mode bits 1 0 : Event counter mode b6 : CNTR1 active edge switch bit 0 : Rising edge active 1 : Falling edge active b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated 011 [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR1) to “1” (interrupts enabled). 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order).

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n Pulse width HL countinuously measurement mode Figure 2.3.31 shows an example of setting registers for using the pulse width HL countinuously measurement mode. Fig. 2.3.31 Example of setting registers for using pulse width HL continuously measurement mode P5D : Port P5 direction register [Address 0B16] À Port P5 direction register b7 b0 b5 : Bit corresponding to port P55 0 : Input mode ˜ Set timer Y stop control bit of timer Y mode register to “0” to start counting ´ Set count value (low-order) to timer Y (low-order) (TYL) [Address 2216] ˆ Set count value (high-order) to timer Y (high-order) (TYH) [Address 2316] TYM : Timer Y mode register [Address 2816] b7 b0 \` Setting of timer Y mode register Select pulse width HL continuously measurement mode or others b5, b4 : Timer Y operating mode bits 1 1 : Pulse width HL continuously measurement mode b6 : CNTR1 active edge switch bit Invalid in pulse width HL continuously measurement mode b7 : Timer Y stop control bit 1 : Count stop : Nothing is allocated 111 [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR1) and the interrupt request bits (timer Y or CNTR1) to “0.”
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR1) to “1” (interrupts enabled). 2: Write values in the order of the timer Y (low-order) ant the timer Y (high-order).

2–753820 GROUP USER’S MANUAL

2.3.5 Application examples

(1) Pulse output mode : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : •The rectangular waveform which is divided clock f(XIN) = 8 MHz up to about 2 kHz is output from the P54/CNTR 0 pin.

• The level of the P54/CNTR 0 pin fixes to “H” while a piezoelectric buzzer output is stopped. Figure 2.3.32 shows an example of a peripheral circuit, Figure 2.3.33, a connection of the timer and a setting of the division ratio, Figure 2.3.34, the setting of the related registers, and Figure 2.3.35, the control procedure. Fig. 2.3.32 Example of peripheral circuit Fig. 2.3.33 Connection of timer and setting of division ratio 250 µ s 250 µ s Set a division ratio so that the underflow cycle of the timer X is this value. The “H” level is output while a piezoelectric buzzer output is stopped. 3820 group P54/CNTR 0 PiPiPi.... f(XIN) = 8 MHz Fix Timer X 1/16 1/125 CNTR 0

3820 GROUP USER’S MANUAL2–76

Fig. 2.3.34 Setting of related registers Fig. 2.3.35 Control procedure TXM : Timer X mode register [Address 2716] b5, b4 : Timer X operating mode bits 0 1 : Pulse output mode b7 : Timer X stop control bit 1 : Count stop P5D : Port P5 direction register [Address 0B16] b7 b0 b4 : Bit corresponding to port P54 1 : Output mode b7 b0 101 TXL : Timer X (low-order) [Address 2016] TXH : Timer X (high-order) [Address 2116] 7C 16 0016 Set “division ratio – 1 (124 : 007C16)” in the timer X register Note : Write values in the order of the low-order byte and the high-order byte. ICON1 : Interrupt control register 1 [Address 3E 16] b7 b0 b4 : Timer X interrupt enable bit 1 : Interrupt enabled XXXX XXX XXXXX XXXXXXX Timer X interrupt; Disabled CNTR 0 output stops at this point (A piezoelectric buzzer output stops) Set port conditions at stop of a piezoelectric buzzer output (“H” level output) Timer X interrupt; Enabled Interrupts; EnabledA piezoelectric buzzer request has occurred? N (= OFF) Y (= ON) RESET A piezoelectric buzzer request generated during the main processing is processed at the output unit Output unit Switch bit 7 of TXM Count (ON)↔ Stop (OFF) TXM (Address 2716), bit 7 P5 (Address 0A16), bit 4 Initialization CLI Main processing Y (= No request) CLT CLD SEI ICON1 (Address 3E 16) TXM (Address 2716) P5D (Address 0B16), bit 4 P5 (Address 0A16), bit 4 TXL (Address 2016) TXH (Address 2116) ICON1 (Address 3E16) ← XXX0XXXX 2 ← 1X01XXXX 2 ← 1 ← 1 ← 7C 16 ← 0016 (125 – 1) ← XXX1XXXX 2 All interrupts; Disabled ← 1 ← 1 TXL (Address 2016) TXH (Address 2116) TXM (Address 2716), bit 7 ← 7C 16 ← 0016 (125 – 1) ← 0 Immediately after no request? N (= Request)

2–773820 GROUP USER’S MANUAL (2) Pulse width measurement mode: Ringer signal detection Outline : A telephone ringing pulse] is detected by applying the timer X interrupt and the pulse width measurement mode. Specifications : •Whether a telephone call exists or not is judged by measuring a pulse width output from the “H” active ringing pulse detection circuit.

• f(XIN) = 8 MHz is used as the count source.
• When the following condition is satisfied, it is regard as normal. 200 ms ≤ pulse width of a ringing pulse < 1.2 s Figure 2.3.36 shows an example of a peripheral circuit, Figure 2.3.37, the setting of the related registers, Figure 2.3.38, a ringing pulse waveform, Figure 2.3.39, an operation timing when a ringing pulse is input, and Figure 2.3.40, the control procedure. Fig. 2.3.36 Example of peripheral circuit Fig. 2.3.37 Setting of related registers 3820 group CNTR 0 Ringing pulse detection circuit Telephone circuit ] Ringing pulse : Signal which is sent by turning on/off (make/break) the telephone line. Each country has a different standard. In this case, Japanese domestic standard is adopted as an example. TXM : Timer X mode register [Address 2716] b5, b4 : Timer X operating mode bits 1 1 : Pulse width measurement mode b7 : Timer X stop control bit 1 : Count stop P5D : Port P5 direction register [Address 0B16] b7 b0 b4 : Bit corresponding to port P54 0 : Input mode b7 b0 111 TXL : Timer X (low-order) [Address 2016] TXH : Timer X (high-order) [Address 2116] A716 6116 Set “division ratio – 1 (24999 : 61A716) ” in the timer X register ICON1 : Interrupt control register 1 [Address 3E16] b7 b0 b4 : Timer X interrupt enable bit 1 : Interrupt enabled XXXX XXX XXXX0 XXXXXXX b6 : CNTR 0 active edge switch bit 0 : •Pulse width measurement mode (Measure “H” level width)
• CNTR 0 interrupt (Falling edge active) ICON2 : Interrupt control register 2 [Address 3F16]0 b7 b0 b0 : CNTR0 interrupt enable bit 1 : Interrupt enabled XX XX1XX Note : Write values in the order of the low-order byte and the high-order byte.

3820 GROUP USER’S MANUAL2–78

Fig. 2.3.38 Ringer signal waveform Fig. 2.3.39 Operation timing when ringing pulse is input Ringing pulse from telephone line

16 HzOFF ON

Approx. 1 second Approx. 2 second Ringing duration No ringing duration Waveform-shaped signal input to microcomputer Ringing duration No ringing duration Reload <When a normal-range ringing pulse is input><When abnormal ringing pulse is input> 4 to 23 interrupts occur Approx. 1 second Approx. 2 second Timer X value Timer X interrupt CNTR 0 interrupt Reload 24 or more interrupts occur Approx. 1.2 second or more Signal input to microcomputer Ringing durationNo ringing duration Timer X value Timer X interrupt CNTR 0 interrupt Signal input to microcomputer

2–793820 GROUP USER’S MANUAL Fig. 2.3.40 Control procedure RESET Timer X interrupt processing routine RTI RTI CNTR 0 interrupt occurs at transition from “H” to “L” of waveform which is input to 4/CNTR 0 pin Timer X interrupt occurs at timer X underflow (at every 50 ms) CNTR 0 interrupt processing routine Reload to timer X register Check the number of underflows counted by timer X interrupt → If the number is 4 or less and 24 or more, the pulse is abnormalY N Check pulse width → When pulse width is within range, the pulse is normal Y N If 24 underflows or more are counted, regard the ringing pulse as out of standard, and execute error processing Y N Initialization CLI CLT CLD SEI ICON1 (Address 3E 16) ICON2 (Address 3F16) P5D (Address 0B16), bit 4 TXM (Address 2716) TXL (Address 2016) TXH (Address 2116) TXM (Address 2716), bit 7 ICON1 (Address 3E16) ICON2 (Address 3F16) All interrupts; Disabled Timer X interrupt; Disabled CNTR 0 interrupt; Disabled Set P54/CNTR 0 pin for input mode Connect timer X Set “division ratio – 1” to timer X (low-order) and timer X (high-order) (Set values in the order of low-order byte and high-order byte) Timer count start Timer X interrupt; Enabled CNTR 0 interrupt; Enabled Interrupts; Enabled TXL (Address 2016) TXH (Address 2116) ← A716 ← 6116 (25000 – 1) The number of underflows is within the range ? Timer X value is within the range ? Judged as presence of ringing pulse (Set ringer flag) A ringing pulse exists ? (Ringer flag = “H”) Processing when a ringing pulse exists Count the number of underflows ← XXX0XXXX 2 ← 0 ← 0XXXXXX0 2 ← 1011XXXX 2 ← A716 ← 6116 (25000 – 1) ← 0 ← XXX1XXXX 2 ← 0XXXXXX1 2

3820 GROUP USER’S MANUAL2–80

(3) Real time port function : Stepping motor drive Outline : A stepping motor is driven by applying a timer X interrupt and the real time port (referred as “RTP”) function. Specifications : • The RTP output time is controlled by changing a timer X setting value in a timer X interrupt processing.

• The RTP output pattern to the motor driver by changing data for RTP. a timer X interrupt processing procedure example when the RTP is used. Fig. 2.3.41 Application connection example when RTP is used Fig. 2.3.42 RTP output example RTP setting value table TXM Data for RTP RTP 0 (P60) RTP 1 (P61) Motor driver Timer X 3820 group Stepping motor Timer X setting value table Timer X setting value (T1) (T5)RTP output time (T6) RTP output pattern À Timer X setting value (T2) Timer X setting value (T3) Timer X setting value (T4) RTP 0 output RTP 1 output RTP output pattern \` RTP output pattern RTP output pattern ˆ À

2–813820 GROUP USER’S MANUAL RTP output pattern À ˆ RTP setting values TXM, b2 TXM, b3 2FD0 16 2B7116 208116 186916 13C9 16 13A916 122116 11C1 16 Timer X setting valueRTP output time Table 2.3.5 Table example for RTP setting valueTable 2.3.4 Table example for timer X setting value Fig. 2.3.43 Timer X interrupt processing procedure example when RTP is used Push to stack area Interrupt processing routine Pop from stack area RTI À ˆ [Notes on use] Notes 1 : When there is no necessity for changing the timer X underflow time in \ , omit it. 2 : When writing to the latch only is selected as the timer X write control, the timer X value (TXL, TXH) is rewritten at the first underflow after \ . 3 : Execute another timer X interrupt processing in À to ˆ . Transfer the next timer X underflow time from internal ROM table and store it in TXL (address 2016) and TXH (address 2116). Transfer RTP output data at the next timer X underflow from internal ROM table and store it in bits 2 and 3 of TXM (address 2716) .

3820 GROUP USER’S MANUAL2–82

2.3.6 Notes on use

Notes on using each mode of the timer X and timer Y are described below. (1) Timer X n Common to all modes l When reading or writing for timer X, be sure to execute for both the timer X (high-order) and the timer X (low-order). When reading a value from the timer X, read it in the order of the timer X (high- order) and the timer X (low-order). When writing a value to the timer X, execute in the order of the timer X (low-order) and the timer X (high-order). If the following operations are performed for the timer X, abnormal operation will occur.

• Write operation before execution of timer X (low-order) reading
• Read operation before execution of timer X (high-order) writing
• In writing for the latch only (timer X write control bit = “1”), if writing timing for the high-order latch is almost same as the underflow timing, a normal value may not be set in the high-order counter. n Pulse output mode l In the pulse output mode, set the bit 4 (corresponding to the P5 4/CNTR 0) of the port P5 direction register (address 000B16) to “1” (output mode). l When the bit 4 (corresponding to the P54/CNTR 0) of the port P5 register (address 000A16) in the pulse output mode is read, the value of the port register are not read out but the output value of the pin is read out. n Event counter mode l When using the event counter mode, set the bit 4 (corresponding to the P54/CNTR 0) of the port P5 direction register (address 000B16) to “0” (input mode). l The maximum input frequency in the event counter mode is: The minimum “H” pulse width is: CC = 4.0 V to 5.5 V The minimum “L” pulse is: CC = 4.0 V to 5.5 V n Pulse width measurement mode l In the pulse width measurement mode, set the bit 4 (corresponding to P54/CNTR 0) of the port P5 direction register (address 000B16) to “0” (input mode). l In reading the value of the P54/CNTR 0 pin as an input pin, the value is “1” at “H” level input or “0” at “L” level input regardless of the value of the CNTR0 active edge switch bit. l Setting the CNTR0 active edge switch bit effects on the active edge of an interrupt. Consequently, a CNTR 0 interrupt request may be caused by setting the CNTR0 active edge switch bit. As a countermeasure against the above, switch the active edge after disabling the CNTR0 interrupt, then set the CNTR0 interrupt request bit to “0.” l The minimum “H” pulse width in the pulse width measurement mode is: The minimum “L” pulse is: 250 V CC – 2 500 V CC – 2 250 V CC – 2 250 V CC – 2 250 V CC – 2

2–833820 GROUP USER’S MANUAL n Real time port function l After reset release, the port P6 direction register is set for the input mode, so the pins P60 and P61 function as ordinary I/O ports. For the pin to be used as RTP, be sure to set the corresponding bits of the port P6 direction register for the output mode. l For a pin used as RTP, do not change this port for the input mode during real time port operation. l Change RTP output data as required, for example, by using a timer X interrupt. (2) Timer Y n Common to all modes l When reading or writing for timer Y, be sure to execute for both the timer Y (high-order) and the timer Y (low-order). When reading a value from the timer Y, read it in the order of the timer Y (high- order) and the timer Y (low-order). When writing a value to the timer Y, execute in the order of the timer Y (low-order) and the timer Y (high-order). If the following operations are performed for the timer Y, abnormal operation will occur.

• Write operation before execution of timer Y (low-order) reading
• Read operation before execution of timer Y (high-order) writing n Period measurement mode l In the period measurement mode, set the bit 5 (corresponding to the P5 5/CNTR 1) of the port P5 direction register (address 000B16) to “0” (input mode). l Setting the CNTR1 active edge switch bit effects on the active edge of an interrupt. Consequently, the CNTR 1 interrupt request may be caused by setting the CNTR1 active edge switch bit. As a countermeasure, switch the active edge after disabling the CNTR1 interrupt, then set the CNTR 1 interrupt request bit to “0.” l The maximum input frequency in the period measurement mode is: The minimum “H” pulse width is: CC = 4.0 V to 5.5 V The minimum “L” pulse is: CC = 4.0 V to 5.5 V n Event counter mode l In the event counter mode, set the bit 5 (corresponding to the P55/CNTR 1) of the port P5 direction register (address 000B16) to “0” (input mode). l Setting the CNTR1 active edge switch bit, the active edge of an interrupt is also affected. Conse- quently, a CNTR1 interrupt request may be caused by setting the CNTR1 active edge switch bit. l The maximum input frequency in the event counter mode is: The minimum “H” pulse width is: 250 V CC – 2 250 V CC – 2 500 V CC – 2 250 V CC – 2 500 V CC – 2

3820 GROUP USER’S MANUAL2–84

The minimum “L” pulse is: n Pulse width HL continuously measurement mode l In the pulse width HL continuously measurement mode, set the bit 5 (corresponding to P55/CNTR 1) of the port P5 direction register (address 000B16) to “0” (input mode). l The CNTR 1 interrupt request occurs at both edges of input pulses regardless of the value of the CNTR 1 active edge switch bit. l The minimum “H” pulse width in the pulse width HL continuously measurement mode is: The minimum “L” pulse is: 250 V CC – 2 250 V CC – 2 250 V CC – 2

2–853820 GROUP USER’S MANUAL

2.4.1 Explanation of operations

Timer 1 to timer 3 are 8-bit timers that operate in the timer mode. The timer mode is a count-down system, so the value of the counter is decremented each time a count source is input. When the counter underflows, an interrupt request occurs. The timer 2 can also output a pulse whose polarity is reversed at each underflow. (1) Timer mode Operation of the timers 1 to 3 in the timer mode are described below. ‹ Start of count operation A count operation is automatically started after reset release. The value of the counter is decremented by 1 each time a count source is input. \` Reload operation The counter underflows at the first count pulse after the value of the counter reaches “00 16.” At this time, the value of the corresponding timer latch is transferred (reloaded) to the counter. ´ Interrupt operation An interrupt request occurs at the counter underflow. At the same time, the corresponding interrupt request bit is set to “1.” The occurrence of each interrupt is controlled by the interrupt enable bit. The acceptance of the interrupt request causes the interrupt request bit which has been set to “1” to be automatically cleared to “0.” It can also be cleared to “0” by software. An interrupt request occurs each time the counter underflows. In other words, an interrupt request occurs every “the counter initial value + 1” count of the rising edge of the count source. Figure 2.4.1 shows a timer mode operation example.

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Fig. 2.4.1 Timer mode operation example Value of counter Interrupt request bit n16 0016 Time RL Interrupt enable bit Count source Operation example in timer mode

• UF : Underflow
• RL : Reload
• n : The counter initial value Count period Count period T (s) = 1 ÷ count source frequency 5 (the counter initial value + 1) RLRLRL UF UF UF UF T 1111 1 : •Clearing by writing “0” to the corresponding interrupt request bit of the timers 1 to 3.
• Clearing by accepting the corresponding interrupt request of the timers 1 to 3 when the corresponding interrupt enable bit is “1.”

2–873820 GROUP USER’S MANUAL Fig. 2.4.2 Rewriting example of counter and latch corresponding to timers 1 or 3 (2) Rewriting the value of the counter and the latch When data is written to the timer, the values of the counter and the latch are rewritten. For rewriting the values of the counters and the latches corresponding to each timer is described below. n Timer 1 and timer 3 By writing a value to the timer, the value is set simultaneously in both the counter and the latch. Accordingly, the counter period, when a value is written to the timer during counting, becomes inac- curate. Figure 2.4.2 shows an rewriting example of the counter and the latch corresponding to the timers 1 or 3. Value of counter Interrupt request bit n16 0016 Time Interrupt enable bit Rewriting example of counter

• UF : Underflow
• RL : Reload
• n : The counter initial value before rewriting
• m : The counter initial value after rewriting RL RLRL UF UF UF Inaccurate count period Write “m16” to timer m 16 11 1 1 : •Clearing by writing “0” to the interrupt request bit corresponding to the timers 1 or 3.
• Clearing by accepting the interrupt request corresponding to the timers 1 or 3 when the corresponding interrupt enable bit is “1.”

3820 GROUP USER’S MANUAL2–88

The write operation to the timer 2 counter is controlled by the timer 2 write control bit (bit 2 at address 002916). (bit 2 = “0”) As the write operation is the same as that to the timer 1 and the timer 3, refer to the previous section, “n Timer 1 and timer 3.” (bit 2 = “1”) When a value is written to the timer 2, the value is set in the timer 2 latch only. The rewritten value is reloaded onto the timer 2 counter at the first underflow after rewriting. Figure 2.4.3 shows an rewriting example of the timer 2 counter and the timer 2 latch. Fig. 2.4.3 Rewriting example of timer 2 counter and timer 2 latch (Writing in timer 2 latch only) n16 0016 Time RLRL UF UF RL UF m 16 Interrupt request bit Interrupt enable bit RL Timer 2 write control bit UF 111 1 1 : •Clearing by writing “0” to the timer 2 interrupt request bit.

• Clearing by accepting the timer 2 interrupt request when the timer 2 interrupt request bit is “1.” Value of counter Rewriting example of timer 2 counter
• UF : Underflow
• RL : Reload
• n : The counter initial value before rewriting
• m : The counter initial value after rewriting Write “m 16” to timer

2–893820 GROUP USER’S MANUAL (3) Pulse output by timer 2 The timer 2 can output a pulse whose polarity is reversed at each the timer 2 counter underflow. Figure 2.4.4 shows a pulse output example. From the moment that the T OUT output control bit is set to “1,” pulses are output from the P56/TOUT output pin. The polarity is reversed every the timer 2 counter underflow. To output pulses, set bit 6 of the port P5 direction register for the output mode by setting it to “1.” Fig. 2.4.4 Pulse output example n16 Pulse output example by timer 2

• UF : Underflow
• RL : Reload
• n : The timer 2 counter initial value FF16 Value of timer 2 counter 0016 UF Timer RL /LiteDiagLines/LiteDiagLines/LiteDiagLinesP56/TOUT pin Programmable I/O port TOUT output control bit Timer 2 interrupt request bit Timer 2 interrupt enable bit Write “1” TOUT output active edge switch bit 1 111111111 1 : •Clearing by writing “0” to the timer 2 interrupt request bit.
• Clearing by accepting the timer 2 interrupt request when the timer 2 interrupt enable bit is “1.”

3820 GROUP USER’S MANUAL2–90

2.4.2 Related registers

Figure 2.4.5 shows memory allocation of timer-related registers. Each of these registers is described below. Fig. 2.4.5 Memory allocation of timer-related registers Address Timer 123 mode register (T123M) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 002516 002616 002416 003C 16 003D 16 003E16 003F16 Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) 002916

2–913820 GROUP USER’S MANUAL (1) Timer latches and timer counters (corresponding to timers 1 to 3) The latches and the counters each consist of 8 bits and are allocated at the same address for each timer. To access a latch and a counter, access the corresponding timer. When the timer is read out, the value of the counter (count value) is read out. n Latch The latch is a register which holds the value to be transferred (reloaded) automatically to the counter as the initial value of the counter at the counter underflow. It is impossible to read out the value of the latch. Figure 2.4.6 the structure of the latches. For the rewrite operation of the value of the latch, refer to “2.4.1 Explanation of operations, (2) Rewriting the value of the counter and the latch.” Fig. 2.4.6 Structure of latches b7b6 b5b4b3 b2b1b0 Timer 1 and timer 3 (T1,T3) [Address 2416, 2616] B Functions At reset R W Timer 1 and timer 3 to

• Set “0016 to FF16” as timers 1 or 3 count value.
• The values of each timer are set to the respective latches and transferred auto- matically to the respective counters at the counter underflow. l Timer 1 latch and timer 3 latch b7b6 b5b4b3 b2b1b0 Timer 2 (T2) [Address 2516] B Functions At reset R W Timer 2 0 •Set “0016 to FF16” as timer 2 count value.
• The value of timer 2 is set to the timer 2 latch and transferred automatically to the timer 2 counter at the timer 2 counter underflow. l Timer 2 latch to 0 ×

3820 GROUP USER’S MANUAL2–92

The counters count the count source] 1. Figure 2.4.7 shows the structure of the timer counters. The value of the counter is decremented by 1 each time a count source is input. The division ratio of the counters is represented by the following expression. Division ratio of the counter = When the timer is read out, the value of the counter (count value) is read out. For the rewriting operation for the value of the counter, refer to “2.4.1 Explanation of operations, (2) Rewriting the value of the counter and the latch.” ] 1: For count source selection, refer to “2.4.2 Related registers, (2) Timer 123 mode register.” Fig. 2.4.7 Structure of timer counters the counter initial value + 1 b7b6 b5b4b3 b2b1b0 Timer 1 and timer 3 (T1, T3) [Address 2416, 2616] B Functions At reset R W Timer 1 and timer 3 to

• Set “0016 to FF16” as timers 1 or 3 count value.
• The value of the counter is decremented by 1 each time a count source is input.
• The values of each timer are set to the respective counters.
• The respective count values are read out by reading each timer. l Timer 1 counter and timer 3 counter b7b6 b5b4b3 b2b1b0 Timer 2 (T2) [Address 2516] B Functions At reset R W Timer 2 0 •Set “0016 to FF16” as timer 2 count value.
• The value of the counter is decremented by 1 each time a count source is input.
• When timer 2 write control bit is “0,” the value of the timer 2 is set to the timer 2 counter.
• The timer 2 count value is read out by reading the timer 2. l Timer 2 counter to

2–933820 GROUP USER’S MANUAL (2) Timer 123 mode register (T123M) The timer 123 mode register (address 002916) consists of TOUT output control bit, the count source selection bits, and others. Figure 2.4.8 shows the structure of the timer 123 mode register. Each bit is described below. Fig. 2.4.8 Structure of timer 123 mode register b7b6 b5b4b3 b2b1b0 Timer 123 mode register (T123M) [Address 2916] B Name Functions At reset R W Timer 123 mode register 6, 7 TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT output control bit Timer 2 write control bit Timer 2 count source selection bit Timer 3 count source selection bit Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. 0 : TOUT output disabled 1 : TOUT output enabled 0 : Write value in latch and counter 1 : Write value in latch only 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Timer 1 count source selection bit 0 : f(XIN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 1 : f(X CIN) 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.

3820 GROUP USER’S MANUAL2–94

n TOUT output active edge switch bit (bit 0) The TOUT output active edge switch bit selects an initial level of the TOUT output. When bit 0 is “0,” the output pulse from the P56/TOUT pin is started at the “H” level. When bit 0 is “1,” the output pulse from the P56/TOUT pin is started at the “L” level. n TOUT output control bit (bit 1) The TOUT output control bit controls the TOUT output. When bit 1 is “0,” the TOUT output is disabled. When bit 1 is “1,” the TOUT output is enabled. n Timer 2 write control bit (bit 2) The timer 2 write control bit controls writing to the timer 2. When bit 2 is “0,” a simultaneous write operation to both the timer 2 latch and the timer 2 counter is set. When a value is written to the timer 2, the value is set into both the timer 2 latch and the timer 2 counter at the same time. When bit 2 is “1,” a write operation to the latch only is set. When a value is written into the timer 2, the value is set into the timer 2 latch only. When a value is written into the timer 2 latch only, this rewritten value is transferred to the timer 2 counter at the first timer 2 counter underflow after rewriting. n Timer 2 count source selection bit (bit 3) The timer 2 count source selection bit selects a count source of the timer 2. Table 2.4.1 shows the relation between the timer 2 count source selection bit and count sources. n Timer 3 count source selection bit (bit 4) The timer 3 count source selection bit selects a count source of the timer 3. Table 2.4.2 shows the relation between the timer 3 count source selection bit and count sources. Table 2.4.1 Relation between timer 2 count source selection bit and count sources bit 3 Timer 2 count source Timer 1 underflow f(X IN)/16 (In low speed mode; f(XCIN)/16) Table 2.4.2 Relation between timer 3 count source selection bit and count sources bit 4 Timer 3 count source Timer 1 underflow f(X IN)/16 (In low speed mode; f(XCIN)/16) n Timer 1 count source selection bit (bit 5) The timer 1 count source selection bit selects a count source of the timer 1. Table 2.4.3 shows the relation between the timer 1 count source selection bit and count sources. Table 2.4.3 Relation between timer 1 count source selection bit and count sources Count source examples f(XIN) = 8 MHz 500 kHz f(XCIN) = 32.768 kHz 2.048 kHz 32.768 kHz bit 5 f(XIN)/16 (In low speed mode; f(XCIN)/16) f(XCIN) Timer 1 count source

2–953820 GROUP USER’S MANUAL (3) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2) The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16) indicate whether an interrupt request has occured or not. Figure 2.4.9 shows the structure of the interrupt request register 1 and Figure 2.4.10 shows the structure of the interrupt request register 2. The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0” by the acceptance of the interrupt request. The interrupt request bit can be cleared to “0” by software, but it cannot be set to “1” by software. The occurrence of each interrupt is controlled by the interrupt enable bit (refer to the next item). For details of interrupts, refer to “2.2 Interrupts.” Fig. 2.4.9 Structure of interrupt request register 1 b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 3C16] B Name Functions At reset R W Interrupt request register 1 0 0 : No interrupt request issued 1 : Interrupt request issued 0 ]INT0 interrupt request bit ] : “0” can be set by software, but “1” cannot be set. 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

3820 GROUP USER’S MANUAL2–96

Fig. 2.4.10 Structure of interrupt request register 2 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 3D16] B Name Functions At resetRW Interrupt request register 2 0 : No interrupt request issued 1 : Interrupt request issued ] : “0” can be set by software, but “1” cannot be set. 7 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

2–973820 GROUP USER’S MANUAL Fig. 2.4.11 Structure of interrupt control register 1 (4) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2) The interrupt control register 1 (address 003E16) and the interruot contorol register 2 (address 003F16) control each interrupt request source. Figure 2.4.11 shows the structure of the interrupt control register 1 and Figure 2.4.12 shows the structure of the interrupt control register 2. When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit only is set to “1,” and the interrupt request is not accepted. When the interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt request occurs when this bit is “1,” the interrupt request is accepted (interrupt disable flag = “0”). Each interrupt enable bit can be set to “0” or “1” by software. For details of interrupts, refer to “2.2 Interrupts.” b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 3E16] B Name Functions At resetRW Interrupt control register 1 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

3820 GROUP USER’S MANUAL2–98

Fig. 2.4.12 Structure of interrupt control register 2 b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 3F16] B Name Functions At resetRW Interrupt control register 2 0 : Interrupts disabled 1 : Interrupts enabled 7 Fix this bit to “0.” 0 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

2–993820 GROUP USER’S MANUAL

2.4.3 Register setting example

Figure 2.4.13 shows an example of setting registers for timers 1, 2, and 3. Fig. 2.4.13 Example of setting registers for timers 1, 2, and 3 [Notes on use] Notes 1: For using interrupt processing, set the following :

• Before setting À below, clear the respective timer interrupt enable bits and the timer respective interrupt request bits to “0.”
• After setting ˆ below, set the respective timer interrupt enable bits to “1” (interrupts enabled). 2: The values written in the timers 1 and 3 are set into both the respective latches and the respective counters at the same time. 3: To enable the T OUT output when the timer 2 is used, set port P56 (this port is also used the TOUT pin) for the output mode. 4: Write values in the order of the timer 1, timer 2, and timer 3. \` Set count value to timer 1 (T1) [Address 2416] ˆ Set count value to timer 3 (T3) [Address 2616] ´ Set count value to timer 2 (T2) [Address 2516] À Setting of timer 123 mode register Select count source or others b7 b0 T123M : Timer 123 mode register [Address 2916] b0 : TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output b1 : T OUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled b2 : Timer 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only b3 : Timer 2 count source selection bit 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) b4 : Timer 3 count source selection bit 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) b5 : Timer 1 count source selection bit 0 : f(X IN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode) 1 : f(XCIN)

3820 GROUP USER’S MANUAL2–100

2.4.4 Application example

Timer mode: Clock function (measurement of one second) Outline: The input clock is divided by timer, with a timer 1 interrupt caused every 0.4 ms, 1 second is counted. Thus, the clock is counted up every second. Specification: •Division of f(XCIN ) = 32 kHz by timer 1 causes an interrupt.

• The counter value counted by the timer 1 interrupt is checked in the main routine. If 1 second has elapsed, the clock counts up. Fig. 2.4.14 Setting of related registers : Noting is allocated T123M : Timer 123 mode register [Address 2916] b5 : Timer 1 count source selection bit 1 : f(XCIN) b7 b0 1X XXX T1 : Timer 1 [Address 2416]7F16 Set “division ratio – 1 (127 : 7F16) ” in the timer 1 Notes 1 : 1 second = 1/32 kHz 5 (127 + 1) 5 250 2 : Write values in the order of the timer 1, timer 2, and timer 3. ICON2 : Interrupt control register 2 [Address 3F16] b7 b0 b2 : Timer 1 interrupt enable bit 1 : Interrupt enabled XX 1XXXX Division ratioCounted in interrupt processing X

2–1013820 GROUP USER’S MANUAL Fig. 2.4.15 Control procedure Clear 1 second counter Count up clock (Second—Year) Main processing Check if the clock has already been set Check a lapse of 1 second Clear the counter counted by interrupt processing Specify so that all processing within the loop marked] is repeated in a cycle of 1 second or less Timer 1 interrupt processing routine Interrupts every 0.4 ms 1 second counter + 1 RTI Y N N Y CLI SEI ICON2 (Address 3F16) T123M (Address 2916) T1 (Address 2416) ICON2 (Address 3F16) ← 0XXXX0XX 2 ← XX1XXXXX 2 ← 7F16 (128 – 1) ← 0XXXX1XX 2 All interrupts; Disabled Timer 1 interrupt; Disabled Connect timer 1 Set “division ratio – 1” to timer 1 (Set in the order of timer 1, timer 2, and timer 3) Timer count start Timer 1 interrupt; Enabled Interrupts; Enabled <Processing for completion of setting clock > (Note) T1 (Address 24 16) IREQ2 (Address 3D16), bit 2 1 second counter ← 7F16 ← 0 ← 0 Clock stop ? When restarting the clock from zero second after completing to set the clock, set timers again. Note : This processing is performed only at completing to set the clock 1 second has elapsed ? (1 second counter = 250 ?) RESET Initialization CLT CLD

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2.4.5 Notes on use

(1) Notes on using timer 1 to timer 3 n When the count sources of timers 1 to 3 are switched, a short pulse occurs in counted input signals, so the timer count value may change greatly. n When the timer 1 output is selected as a count source of timer 2 or timer 3, a short pulse occurs in the output signal at writing value into the timer 1, so the count value of the timer 2 or timer 3 may change greatly. n For the above reasons, set values in the order of timer 1, timer 2, and timer 3 after setting their count sources. (2) Timer 2 write control When writing to the latch only is selected, the value written into the timer 2 (address 002516) is written only in the latch for reloading. This rewritten value is transferred to the timer 2 counter at the first underflow after rewriting. Usually, a value is written in both the latch and the counter at the same time. That is, when a value is written to timer, it is set in both the latch and the counter. (3) Timer 2 output control In the timer 2 (T OUT ) output enable state, a signal whose polarity is reversed each time the timer 2 counter underflows is output from the TOUT pin. In this case, set the port P56 (this is used as the TOUT pin) for the output mode.

3820 GROUP USER’S MANUAL 2–103

2.5.1 Explanation of operations

As a serial I/O1, it is possible to select either the clock synchronous serial I/O1 mode or the clock asynchronous serial I/O1 (UART) mode. This section describes operations in both the clock synchronous mode and the clock asynchronous (UART) mode. When serial I/O1 is actually used, refer to “2.5.4 Reg- ister setting example.” (1) Clock synchronous serial I/O1 mode In the clock synchronous mode, 8 shift clocks generated in the clock control circuit are used as synchronizing clocks for transfer. In synchronization with these shift clocks, the transmit operation on the transmitter and the receive operation on the receiver are simultaneously executed. The transmitter transmits each 1-bit data from the P4 5/TxD pin in synchronization with the falling of the shift clocks. The receiver receives each 1-bit data from the P4 4/RxD pin in synchronization with the rising of the shift clocks. Figure 2.5.1 shows an external connection example in the clock synchronous mode. Fig. 2.5.1 External connection example in clock synchronous mode 1/(n+1) BRG XIN SCLK TxD RxD RxD TxD 3820 group À Internal clock is selected External clock is selected Receive buffer register Receive shift register Transmit shift register Transmit buffer register Clock control circuit 3820 group \` Receive shift register Receive buffer register Transmit buffer register Transmit shift register 1/4 SCLKClock control circuit

3820 GROUP USER’S MANUAL2–104

Ordinarily, when clock synchronous transfer is performed between microcomputers, an internal clock is selected for one of them, and it outputs 8 shift clocks generated by a start of transmit operation from the P46/SCLK1 pin. An external clock is selected for the other microcomputer, and it uses the clock input from the P46/SCLK1 pin as a shift clock. Figure 2.5.2 shows a shift clock. Fig. 2.5.2 Shift clock 1/(n+1) BRG XIN SCLK1 TxD RxD RxD TxD 3820 group À Internal clock is selected External clock is selected Receive buffer register Receive shift register Transmit shift register Transmit buffer register Clock control circuit 3820 group \` Receive shift register Receive buffer register Transmit buffer register Transmit shift register 1/4 SCLK1Clock control circuit Shift clock

3820 GROUP USER’S MANUAL 2–105

n Data transfer rate (baud rate) When an internal clock is used, the data transfer rate (baud rate), which is a shift clock frequency in the clock synchronous mode, is determined by baud rate generator (BRG). When the BRG count source selection bit (bit 0) of the serial I/O1 control register (address 001A16) is “0,” XIN pin input clock is input to the BRG, when this bit is “1,” XIN pin input clock divided by 4 is input to the BRG. The expression for baud rate is shown below. l When selecting an internal clock (Using BRG) l When selecting an external clock Baud rate = [bps] Division ratio ] 1 5 (BRG setting value ] 2 + 1) 5 4 ] 1 Division ratio; Select “1,” or “4” ] 2 BRG setting value; 0 to 255 (0016 to FF16) Baud rate = [bps] X IN pin input Frequency of input clock to P46/SCLK1 pin

3820 GROUP USER’S MANUAL2–106

n Transmit operation in the clock synchronous mode Transmit operation in the clock synchronous mode is described below. l Start of transmit operation A transmit operation is started by writing transmit data into the transmit buffer register (address 001816) in the transmit enable state.] 1 l Transmit operation À By writing transmit data into the transmit buffer register, the transmit buffer empty flag (bit 0) of the serial I/O1 status register (address 001916) is cleared to “0.” \ The transmit data written in the transmit buffer register is transferred to the transmit shift register. ] 2 ´ When a data transfer from the transmit buffer register to the transmit shift register is com- pleted, the transmit buffer empty flag is set to “1.”] 3 ˆ The transmit data transferred to the transmit shift register is output from the P45/TxD pin in synchronization with the falling of the shift clocks. ˜ The data is output from the least significant bit of the transmit shift register. Each time 1- bit data is output, the data of the transmit shift register is shifted by 1 bit toward the least significant bit. ] 1: Initialization of register or others for a trans- mit operation. Refer to “2.5.4 Register set- ting example.” ] 2: When the transmit interrupt source selec- tion bit (bit 3) of the serial I/O1 control register (address 001A 16) is set to “0,” a serial I/O1 transmit interrupt request occurs immediately after transfer in \ . When this bit is set to “1,” a transmit interrupt re- quest occurs at the time of ˘ . ] 3: While the transmit buffer empty flag is “1,” it is possible to write the next transmit data into the transmit/receive buffer register. Serial I/O1 status register [Address 1916] 1 Transmit buffer register Write transmit data Data bus Serial I/O1 status register [Address 1916] 0 [Address 1816] Transmit shift register Transfer transmit data Transmit buffer register Transmit shift register P45/TxD D 0D 1D 2D 3D 4D 5D 6D 7 Transmit shift register P45/TxD D 1 D 2D 3D 4D 5D 6D 7

3820 GROUP USER’S MANUAL 2–107

¯ At the time when a transmit shift operation starts, the transmit shift register shift com- pletion flag (bit 2) of the serial I/O1 status register is cleared to “0.” ] 4 ˘ At the time when the transmit shift operation completes, the transmit shift register shift com- pletion flag is set to “1.” ] 2 ] 4 ] 4: When an internal clock is used as a syn- chronizing clock, supplying the shift clock to the transmit shift register stops auto- matically at the completion of 8-bit trans- mission. However, when the next transmit data is written to the transmit buffer regis- ter while the transmit shift register shift com- pletion flag is “0,” supplying the shift clock is continued. Fig. 2.5.3 Transmit operation in clock synchronous mode Transmit shift registerShift clock D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 7 Transmit shift register P45/TxD D 0D 1D 2D 3D 4D 5D 6D 7 Serial I/O1 status register [Address 1916] 0 Transmit shift register P45/TxD D 7 Serial I/O1 status register [Address 1916] 1

3820 GROUP USER’S MANUAL2–108

Fig. 2.5.4 Transmit timing example in clock synchronous mode Transmit enable bit Transmit buffer empty flag Transmit shift register shift completion flag Write next transmit data Write “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0TxD Shift clock Write transmit data to transmit buffer register D 1

3820 GROUP USER’S MANUAL 2–109

n Receive operation in the clock synchronous mode Receive operation in the clock synchronous mode is described below. l Start of receive operation A receive operation is started by writing the following data into the receive buffer register (address 001816) in the receive enable state.] 1

• Transmit data in the full duplex data transfer mode
• Arbitrary dummy data in the half duplex data transfer mode l Receive operation À Each 1-bit data is read into the receive shift register from the P4 4/RxD pin in synchroni- zation with the rising of the shift clocks. \` The data enters first into the most significant bit of the receive shift register. Each time 1- bit data is received, the data of the receive shift register is shifted by 1 bit toward the least significant bit. ´ When 1-byte data has been input into the receive shift register, the data of the receive shift register is transferred to the receive buffer register (address 0018 16).] 2 ˆ When a data transfer to the receive buffer register is completed, the receive buffer full flag (bit 1) of the serial I/O1 status register (address 0019 16) is set to “1,”] 3 a serial I/O1 receive interrupt request occurs. ] 1: Initialization of register or others for a re- ceive operation. Refer to “2.5.4 Register setting example.” ] 2: When data remains without reading out the data of the receive buffer register (the receive buffer full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun error flag of the serial I/O1 status register is set to “1.” At this time, the data of the receive shift register is not transferred to the receive buffer register, but the former data of the receive buffer register is held. ] 3: The receive buffer full flag is cleared to “0” by reading out the receive buffer register. Receive shift registerP44/RxD D 1 D 0 Receive shift register D 4 P44/RxD D 3 D 0D 1D 2 Transfer receive data Receive buffer register Receive shift register [Address 1816] D 7 D 4D 5D 6 Serial I/O1 status register [Address 1916] D 3 D 0D 1D 2

3820 GROUP USER’S MANUAL2–110

Fig. 2.5.5 Receive operation in clock synchronous mode Fig. 2.5.6 Receive timing example in clock synchronous mode Shift clock Receive shift register D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 2 D 1 D 0 D 0 D 1 D 0 D 1D 0 Receive enable bit Write “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7RxD Shift clock Receive buffer full flag Read out receive buffer register Write data to receive buffer register

3820 GROUP USER’S MANUAL 2–111

Fig. 2.5.7 Transmit/receive timing example in clock synchronous mode n Transmit/receive timing example in the clock synchronous mode Figure 2.5.7 shows a data transmit/receive timing example in the clock synchronous mode. TXD R XD SCLK1 TXD R XD SCLK1 Transmit enable bit Transmit buffer empty flag Transmit shift register shift completion flag Write next transmit data Write “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1TXD Shift clock Write transmit data to transmit buffer register Receive enable bit Receive buffer full flag D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1R XD Write “1” D 0 D 0 Read out receive buffer register 3820 group À 3820 group \`

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(2) Clock asynchronous serial I/O1 (UART) mode As the clock asynchronous mode (UART mode), data is transmitted and received in asynchronous form unifying the data transfer rate and the transfer data format between the transmitter and the receiver. Figure 2.5.8 shows an external connection example in the UART mode. Fig. 2.5.8 External connection example in UART mode 1/(n+1) BRG XIN TxD RxD RxD TxD 3820 group À Receive buffer register Receive shift register Transmit shift register Transmit buffer register Clock control circuit 3820 group \` Receive shift register Receive buffer register Transmit buffer register Transmit shift register 1/4 Clock control circuit XIN 1/(n+1) BRG RxD TxD Clock control circuit 3820 group ´ Receive shift register Receive buffer register Transmit buffer register Transmit shift register XIN 1/(n+1) BRG

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n Data transfer rate (baud rate) When an internal clock is used, the data transfer rate (baud rate), which is a shift clock frequency in the UART mode, is determined by baud rate generator (BRG). When the BRG count source selection bit (bit 0) of the serial I/O1 control register (address 001A16) is “0,” XIN pin input clock is input to the BRG, when this bit is “0,” XIN pin input clock divided by 4 is input to the BRG. The expression for baud rate is shown below. l When selecting an internal clock (Using BRG) l When selecting an external clock Baud rate = [bps] Division ratio ] 1 5 (BRG setting value ] 2 + 1) 5 16 ] 1 Division ratio; Select “1,” or “4” ] 2 BRG setting value; 0 to 255 (0016 to FF16) Baud rate = [bps] X IN pin input Table 2.5.1 Baud rate selection table (reference values) Baud rates [bps] At XIN input = 4.9152 MHz At XIN input = 8 MHz 600 2400 1200 4800 9600 38400 19200 307200 153600 76800 976.5625 3906.25 1953.125 7812.5 15625 62500 31250 500000 250000 125000 BRG count source BRG setting value 127 (7F16) 0 (0016) 300 488.28125 X IN input/4 X IN input/4 X IN input/4 X IN input/4 X IN input/4 X IN input 1 (0116) 0 (0016) 1 (0116) 3 (0316) 7 (0716) 15 (0F16) 63 (3F16) 31 (1F16) 255 (FF16)X IN input/4 X IN input/4 X IN input/4 X IN input/4 Frequency of input clock to P46/SCLK1 pin X IN input

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Fig. 2.5.9 Transfer data format in UART mode Bit Functions Indicates a start of data transmission. A “L” signal for one bit is added just before transmit data. Indicates the transmit data written in the transmit buffer register, “02” data is a “L” signal and “12” data is a “H” signal. These bits are called as character bits. ST (Start bit) Table 2.5.2 Each bit function of UART transmit data DATA (Data bit) To improve the reliability of data, this bit is added just after the last data bit. The value of this bit changes in accordance with the value of the parity selection bit so that the number of “1” in the transmit/receive data (including the parity bit) can always be an even or an odd number. PA (Parity bit) SP (Stop bit) Indicates an completion of data transmission. This bit is added just after the last data bit (or just after a parity bit in the parity checking enabled). As a stop bit, a “H” signal for 1 bit or 2 bits is output. n Transfer data format Data transfer format is set by the UART control register (address 001B16). Figure 2.5.9 shows a transfer data format in the UART mode, Table 2.5.2, the each bit function of UART transmit data, Figure 2.5.10, all transfer data formats in the UART mode. D 0 D 1 D 6 D 7 PA l For 1ST–8DATA–1PA–2SP ST STSP SP D 0 D 1 Next transmit data (at continuous output)Transmit data Data bit (8 bits) LSB MSB

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Fig. 2.5.10 All transfer data formats in UART mode ST Di PA SP : Start bit : Data bit : Parity bit : Stop bit D 0 D 1 D 4 D 5 l For 7-bit UART mode ST SP LSB MSB D 2 D 3 D 6 SP ST LSB MSB SP SPST LSB MSB PA SPST LSB MSB PA SP D 0 D 1 D 4 D 5D 2 D 3 D 6 D 0 D 1 D 4 D 5D 2 D 3 D 6 D 0 D 1 D 4 D 5D 2 D 3 D 6 l For 8-bit UART mode ST SP LSB MSB D 7 SP ST LSB MSB SP SPST LSB MSB PA SPST LSB MSB PA SP D 0 D 1 D 4 D 5D 2 D 3 D 6 D 7D 0 D 1 D 4 D 5D 2 D 3 D 6 D 7D 0 D 1 D 4 D 5D 2 D 3 D 6 D 7D 0 D 1 D 4 D 5D 2 D 3 D 6

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n Transmit operation in the UART mode Transmit operation in the UART mode is described below. l Start of transmit operation A transmit operation is started by writing transmit data into the transmit buffer register (address 001816) in the transmit enable state.] 1 l Transmit operation À By writing transmit data into the transmit buffer register, the transmit buffer empty flag (bit 0) of the serial I/O1 status register (address 0019 16) is cleared to “0.” \ The transmit data written in the transmit buffer register is transferred to the transmit shift register.] 2 ´ When a data transfer from the transmit buffer register to the transmit shift register is com- pleted, the transmit buffer empty flag is set to “1.”] 3 ˆ The transmit data transferred to the transmit shift register is output from the P45/TxD pin in synchronization with the falling of the shift clock, beginning with the start bit. A start bit, a parity bit and a stop bit are automatically generated and output in accordance with the contents set in the UART control register. ˜ The data is output from the least significant bit of the transmit shift register. Each time 1- bit data is output, the data of the transmit shift register is shifted by 1 bit toward the least significant bit. ] 1: Initialization of register or others for a trans- mit operation. Refer to “2.5.4 Register set- ting example.” ] 2: When the transmit interrupt source selection bit (bit 3) of the serial I/O1 control register (address 001A 16) is set to “0,” a serial I/O1 transmit interrupt request occurs immediately after transfer in \ . When this bit is set to “1,” a transmit interrupt request occurs at the time of ˘ . ] 3: While the transmit buffer empty flag is “1,” it is possible to write the next transmit data into the transmit/receive buffer register. Transmit shift register P45/TxD STD 1D 2D 3D 4D 5D 6D 7 D 0 Serial I/O1 status register [Address 1916] Transmit buffer register Write transmit data Data bus Serial I/O1 status register [Address 1916] [Address 1816] Transmit shift register Transfer transmit data Transmit buffer register Transmit shift register P45/TxD D 0 D 2D 3D 4D 5D 6D 7 D 1

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¯ At the time when a transmit shift operation starts, the transmit shift register shift com- pletion flag (bit 2) of the serial I/O1 status register is cleared to “0.” ] 4 ˘ After the lapse of a 1/2 period ] 5 of the shift clock from a transmission start of stop bit, the transmit shift register shift completion flag is set to “1.” ] 2 ] 4 ] 4: When an internal clock is used as a syn- chronizing clock, supplying the shift clock to the transmit shift register stops auto- matically at the completion of 8-bit transmission. However, when the next transmit data is written to the transmit buffer register while the transmit shift register shift completion flag is “0,” supplying the shift clock is continued. ] 5: In the case of 2 stop bits, after the lapse of a 1/2 period of the shift clock from a start of the second stop bit transmission. Fig. 2.5.11 Transmit timing example in UART mode Transmit shift register shift completion flag Transmit buffer empty flag D 0 D 1 D 2 Shift clock TXD ST D 6 PAR SP SP D 0ST Write next transmit data Write transmit data to transmit buffer register SP Transmit shift register P45/TxD Serial I/O1 status register [Address 1916] P45/TxD Serial I/O1 status register [Address 1916] STD 1D 2D 3D 4D 5D 6D 7 D 0

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n Receive operation in the UART mode Receive operation in the UART mode is described below. l Start of receive operation In the receive enable state,] 1 set the receive enable bit (bit 5) of the serial I/O1 control register (address 001A16) into the enabled state (“1”). With this operation, a start bit is detected and a receive operation of serial data is started. l Receive operation À With the lapse of a 1/2 period of the shift clock from detection of the falling of the P44/ RxD pin input, the P44/RxD pin level is checked. When it is “L” level, the bit is judged as a start bit. When it is “H” level, the bit is judged as noise, so the receive operation is stopped, being put into wait status for a start bit again. \` Each 1-bit data is read into the receive shift register from the P4 4/RxD pin in synchroni- zation with the rising of the shift clocks. ´ The data after the detection of the start bit enters first into the most significant bit of the receive shift register. Each time 1-bit data is received, the data of the receive shift regis- ter is shifted by 1 bit toward the least signifi- cant bit. ˆ When a specified number of bits has been input into the receive shift register, the data of the receive shift register are transferred to the receive buffer register (address 0018 16).] 2] 3 ] 1: Initialization of register or others for a receive operation. Refer to “2.5.4 Register setting exam- ple.” ] 2: When the data bit length is 7 bits, bits 0 to 6 of the receive buffer register are receive data, and bit 7 (MSB) is cleared to “0.” ] 3: When data remains without reading out the data of the receive buffer register (the receive buffer full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun error flag of the serial I/O1 status register is set to “1.” At this time, the data of the receive shift register is not transferred to the receive buffer register, but the former data of the receive buffer register is held. Shift clock R XD (Noise) R XD (ST) Receive shift register D 4 P44/RXD D 2D 3 D 1 D 0 Transfer receive data Receive buffer register Receive shift register [Address 1816] D 6D 7 D 5 D 4 D 2D 3 D 1 D 0 Receive shift registerP44/RXD D 1 D 0

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˜ After the lapse of a 1/2 period of the shift clock from a reception start of stop bit, the receive buffer full flag (bit 1) of the serial I/O1 status register is set to “1.” And a serial I/O1 receive interrupt request occurs. ¯ Error flag detection is performed concurrently with the occurrence of a serial I/O1 receive interrupt request. ] 4: The receive buffer full flag is cleared to “0” by reading out the receive buffer register. Fig. 2.5.12 Receive timing example in UART mode (3) Processing upon occurrence of errors n Parity error, framing error, or summing error When a parity error, a framing error, or a summing error occurs, the flag corresponding to each error in the serial I/O1 status register is set to “1.” These flags are not cleared to “0” automatically, so set them to “0” by software. These flags are set to “0” by one of the following operations.

• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register n Overrun error An overrun error occurs when data is already input in the receive buffer register and yet all data is input in the receive shift register. If an overrun error occurs, the data of the receive shift register is not transferred and the data of the receive buffer register is held. At this time, even if the data of the receive buffer register is read out, the data of the receive shift register is not transferred. Consequently, the data of the receive shift register becomes unreadable, so that the receive data becomes invalid. If an overrun error occurs, after set the overrun error flag of the serial I/O1 status register to “0,” perform a receive operation again. The overrun error flag is set to “0” by one of the following operations.
• Set the serial I/O1 enable bit to “0”
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register D 6 PAR SP SP D 0ST Write “1” D 0 D 1 D 2 Shift clock Receive enable bit R XD ST Start receiving at falling of ST Check that ST is “L” level Serial I/O1 status register [Address 1916] Shift clock R XD (SP)

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2.5.2 Pins

The serial I/O1 uses 4 pins, namely, pins for data transmit, data receive, shift clock transmit/receive, and receive enable signal output. All these pins are also used as port P4 and switched their functions by the serial I/O1 enable bit (bit 7) and S RDY1 output enable bit (bit 2) of the serial I/O1 control register (address 001A 16). The function of each pin is described below. (1) Data transmit pin [TxD] This pin outputs each bit of transmit data and is used as port P45. When the serial I/O1 enable bit of the serial I/O1 control register is set to “1,” this pin functions as a serial I/O1 data output pin. (2) Data receive pin [RxD] This pin inputs each bit of receive data and is used as port P44. When the serial I/O1 enable bit of the serial I/O1 control register is set to “1,” this pin functions as a serial I/O1 data input pin. (3) Shift clock transmit/receive pin [SCLK1 ] n Clock synchronous mode This pin inputs (receives from the outside) or outputs (supplies to the outside) a shift clock used for transmission and reception. When the serial I/O1 synchronization clock selection bit (bit 1) of the serial I/O1 control register is set to “0” (use of internal clock), a shift clock is output to the outside. When this bit is set to “1” (use of external clock), a shift clock is input from the outside. n UART mode When the serial I/O1 synchronization clock selection bit (bit 1) of the serial I/O1 control register is set to “1” (use of external clock), a shift clock is supplied from the outside. When this bit is set to “0” (use of internal clock), this pin does not function. (4) Receive enable signal output pin [ S RDY1 ] This pin notifies the outside of the receive enable state in the clock synchronous mode. This pin does not function in the UART mode.

• The S RDY1 output enable bit (bit 2) of the serial I/O1 control register is set to “1.”
• The transmit enable bit (bit 4) of the serial I/O1 control register is set to “1.” When the above two conditions are satisfied, the pin level changes from “H” to “L” at the timing which data is written into the receive buffer register, notifying the outside of the receive enable state.

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Fig. 2.5.13 Memory allocation of serial I/O1-related registers Fig. 2.5.14 Structure of transmit/receive buffer register

2.5.3 Related registers

Figure 2.5.13 shows the memory allocation of serial I/O1-related registers. They are the transmit/receive buffer register, serial I/O1 status register, serial I/O1 control register, and UART control register. (1) Transmit/receive buffer register (TB/RB) This register (address 0018 16) is used to write serial I/O1 transmit data or to read receive data (used for both the clock synchronous mode and the UART mode). For data transmission, transmit data is written into this register. Received data is obtained by reading out this register. Transmit/receive buffer register (TB/RB) Address 001B16 001816 001A16 001916 Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) b7b6 b5b4b3 b2b1b0 Transmit/receive buffer register (TB/RB) [Address 1816] B Functions At reset R W Transmit/receive buffer register to ?At transmit

• Set “0016 to FF16” as transmit data.
• The transmit data is transferred automatically to transmit shift register by writing transmit data. At receive
• When all receive data has been input into the receive shift register, the receive data is auto- matically transferred to this register.

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(2) Serial I/O1 status register (SIO1STS) This register (address 001916) consists of the following flags:

• flags representing the states of the registers used for transmission/reception
• error flags. This is a read-only register. Bit 7 is unused and set to “1” at reading. Fig. 2.5.15 Structure of serial I/O1 status register n Transmit buffer empty flag (bit 0) This flag is automatically cleared to “0” by writing transmit data into the transmit buffer register. After the transmit data is written in the transmit buffer register, it is transferred to the transmit shift register. When this transfer is completed and the transmit buffer register becomes empty, this flag is automatically is set to “1.” It is possible to write transmit data into the transmit buffer register only while the transmit buffer empty flag is “1.” This flag is valid in both the clock synchronous mode and the UART mode. n Receive buffer full flag (bit 1) When all receive data has been input to the receive shift register and then this receive data is transferred to the receive buffer register, this flag is automatically is set to “1.” When the transferred receive data is read out from the receive buffer register, the flag is automatically is cleared to “0.” If all the next receive data is input to the receive shift register when the receive buffer flag is “1” (the receive buffer register is not yet read out), the overrun error flag is set to “1.” This flag is valid in both the clock synchronous mode and the UART mode. b7b6 b5b4b3 b2b1b0 Serial I/O1 status register (SIO1STS) [Address 1916] B At reset R W Serial I/O1 status register Name Functions Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading. Summing error flag (SE) 0: (OE) U (PE) U (FE) = 0 1: (OE) U (PE) U (FE) = 1

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n Transmit shift register shift completion flag (bit 2) When a shift operation (transmission of the first data bit) is started by shift clock after transmit data is transferred to the transmit shift register, this flag is cleared to “0.” When the shift operation is completed (completion of transmission of the last data bit), the flag is set to “1.” This flag is valid in both the clock synchronous mode and the UART mode. n Overrun error flag (bit 3) If all the next receive data is input to the receive shift register when data has been input (not read out) in the receive buffer register, this flag is set to “1” (occurrence of an overrun error). This flag is set to “0” by one of the following operations.

• Set the serial I/O1 enable bit to “0”
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register This flag is valid in both the synchronous mode and the UART mode. n Parity error flag (bit 4) In the UART mode, this flag checks an even parity or odd parity by hardware. When the parity of received data is different from the set parity, this flag is set to “1.” This flag is set to “0” by one of the following operations.
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register This flag is valid only in the parity enable state in the UART mode. n Framing error flag (bit 5) In the UART mode, this flag judges whether frame synchronization is abnormal. When the stop bit of receive data cannot be received at the set timing, this flag is set to “1.” This flag is set to “0” by one of the following operations.
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register This flag is valid only in the UART mode. n Summing error flag (bit 6) This flag is set to “1” when an overrun error, parity error, or framing error occurs. This flag is set to “0” by one of the following operations.
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register This flag is valid in both the clock synchronous mode and the UART mode.

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(3) Serial I/O1 control register (SIO1CON) This register (address 001A16) controls various functions related to the serial I/O1, such as transmit/ receive modes, clocks, and pin functions. All the bits of this register are read and written by software. Fig. 2.5.16 Structure of serial I/O1 control register b7b6 b5b4b3 b2b1b0 Serial I/O1 control register (SIO1CON) [Address 1A16] B At reset R W Serial I/O1 control register Name Functions BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronization clock selection bit (SCS)

• In clock synchronous mode 0: BRG output/4 1: External clock input
• In UART mode 0: BRG output/16 1: External clock input/16 Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 enable bit (SIOE) Serial I/O1 mode selection bit (SIOM) S RDY1 output enable bit (SRDY) 0: P47/SRDY1 pin operates as I/O port P47 1: P47/SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) 0: When transmit buffer has emptied 1: When transmit shift operation is completed 0: Transmit disabled 1: Transmit enabled Clock asynchronous serial I/O1 (UART) mode 1: Clock synchronous serial I/O1 mode 0: Serial I/O1 disabled (pins P44–P47 operate as I/O pins) 1: Serial I/O1 enabled (pins P44–P47 operate as serial I/O1 pins) 0: Receive disabled 1: Receive enabled

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n BRG count source selection bit (bit 0) This bit selects a count source to be input to the BRG. In the “0” state, an undivided XIN input signal is input to the BRG. In the “1” state, an XIN input signal divided by 4 is input to the BRG. n Serial I/O1 synchronization clock selection bit (bit 1) This bit selects a synchronizing clock to be used in the serial I/O1. l Clock synchronous mode When this bit is set to “0,” a BRG output divided by 4 becomes a shift clock. In the “1” state, an external clock (P46/SCLK1 pin input) becomes a shift clock as it is. l UART mode In the “0” state, a BRG output divided by 16 becomes a shift clock. In the “1” state, an external clock (P4 6/SCLK1 pin input) divided by 16 becomes a shift clock. n S RDY1 output enable bit (bit 2) When the S RDY1 function is used in the clock synchronous mode, set this bit to “1.” In the “0” state, the P47/SRDY1 pin functions as an I/O port P47. In the UART mode, the value of this bit is invalid, so that the P47/SRDY1 pin functions as an I/O port P4 7. n Transmit interrupt source selection bit (bit 3) This bit determines a source which generates a serial I/O1 transmit interrupt request. In the “0” state, a serial I/O1 transmit interrupt request occurs at the time when the values of the transmit buffer register are transferred to the transmit shift register. In the “1” state, a serial I/O1 transmit interrupt request occurs at the time when the shift operation of the transmit shift register is completed. n Transmit enable bit (bit 4) This bit controls a transmit operation. This bit controls as shown in Table 2.5.3 only when the serial I/O1 enable bit is “1” (serial I/O1 enabled). When the serial I/O1 enable bit is “0” (serial I/O1 disabled), this bit is invalid. Transmit buffer empty flag ] 1Transmit enable bit Table 2.5.3 Control contents of transmit enable bit Flag function is valid Transmit shift register shift completion flag] 2P4 5/TXD pin function

0 Port P4 5 Set to “0”

] 1: Bit 0 of serial I/O1 status register ] 2: Bit 2 of serial I/O1 status register

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1 Data receive pin R XD Flag function is valid

0 Set to “0”Port P44

Table 2.5.4 Control contents of receive enable bit ] 1: Bit 1 of serial I/O1 status register ] 2: Bits 3, 4, 5, and 6 of serial I/O1 status register Each error flag] 2Receive buffer full flag ] 1P4 4/RX D pin functionReceive enable bit n Receive enable bit (bit 5) This bit controls receive operation. This bit controls as shown in Table 2.5.4 only when the serial I/O1 enable bit (bit 7) is “1” (serial I/O1 enabled). When the serial I/O1 enable bit is “0” (serial I/O1 disabled), this bit is invalid. n Serial I/O1 mode selection bit (bit 6) This bit selects a transmit/receive mode of the serial I/O1. In the UART mode, set this bit to “0.” In the clock synchronous mode, set it to “1.” n Serial I/O1 enable bit (bit 7) When the serial I/O1 function is used, set this bit to “1.” When the bit is set to “1,” the pins P4 4/RxD, P45/TxD, and P46/SCLK1 function as RxD, TxD, and SCLK1 respectively (Furthermore, when the SRDY1 output enable bit is set to “1,” the P47/SRDY1 pin functions as an SRDY1 pin). In the “0” state, they function as ports P44–P4 7 respectively.

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(4) UART control register (UARTCON) This register (address 001B16) controls the transfer data format in the UART mode and the output format of the P45/TxD pin. Fig. 2.5.17 Structure of UART control register n Character length selection bit (bit 0) This bit selects data bit length of the UART transfer data format. In the “0” state, the data bit length is 8 bits. In the “1” state, the data bit length is 7 bits. n Parity enable bit (bit 1) This bit is set to “1” to make a parity check and to “0” to make no parity check. In the “1” state, the parity error flag becomes valid. n Parity selection bit (bit 2) This bit selects a parity type of the UART transfer data format. In the “0” state, the parity type is an even parity. In the “1” state, it is an odd parity. n Stop bit length selection bit (bit 3) This bit selects a stop bit length of the UART transfer data format. In the “0” state, the stop bit length is 1 stop bit. In the “1” state, the stop bit length is 2 stop bits. n P4 5/TxD P-channel output disable bit (bit 4) This bit controls the output type of the P45/TxD pin. In the “0” state, the output type is CMOS output in the output mode. In the “1” state, the output type is N-channel open-drain output in the output mode. The 5 low-order bits of the UART control register can be read and written. The 3 high-order bits are unused and read-only bits. At reading, all the bits are set to “1.” b7b6 b5b4b3 b2b1b0 UART control register (UARTCON) [Address 1B16] B At reset R W UART control register to Name Functions Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TxD P-channel output disable bit (POFF) CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Nothing is allocated. These bits cannot be written to and are fixed to “1” at reading. Parity selection bit (PARS) 0: Even parity 1: Odd parity

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1 X00

1 X10

1 ST–8 DATA–1 SP

1 ST–7 DATA–1 SP

1 ST–8 DATA–1 PA–1 SP

1 ST–7 DATA–1 PA–1 SP

1 ST–8 DATA–2 SP

1 ST–7 DATA–2 SP

1 ST–8 DATA–1 PA–2 SP

1 ST–7 DATA–1 PA–2 SP

X: “0” or “1” ST: Start bit DATA: Data bit PA: Parity bit SP: Stop bit X Table 2.5.5 Relation between UART control register and transfer data formats

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2.5.4 Register setting example

(1) Clock synchronous serial I/O mode Fig. 2.5.18 Transmitting method in clock synchronous mode (1) SIO1CON: Serial I/O1 control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b7 b0 b2: SRDY1 output enable bit 0: P47/SRDY1 pin operates as I/O port P47 1: P47/SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) b4: Transmit enable bit 1: Transmit enabled b5: Receive enable bit 0: Receive disabled 1: Receive enabled b6: Serial I/O1 mode selection bit 1: Clock synchronous serial I/O1 mode ´ Setting of serial I/O1 control register Selection of clock synchronous, transmit, or others À Disable Serial I/O1 transmit interrupt ICON1: Interrupt control register 1 [Address 3E16] b3: Serial I/O1 transmit interrupt enable bit 0: Interrupts disabled b7 b0 \ Set the value to baud rate generator (BRG) [Address 1C16] b1: Serial I/O1 synchronization clock selection bit (In clock synchronous mode) 0: BRG output/4 1: External clock input b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b7: Serial I/O1 enable bit 1: Serial I/O1 enabled (pins P4 4–P47 operate as serial I/O1 pins) Continued to Figure 2.5.19 [Notes on use] Notes 1: To use an INT pin or input port for watching SRDY1 , set as required. 2: When an external clock is selected in setting ´ below, BRG setting is not required in setting \ below. 3: In the full duplex data transfer mode, set the receive enable bit (bit 5) to “1” (receive enabled) in setting ´ below. 4: To use a serial I/O1 transmit interrupt, set in the following sequence. 5: When no serial I/O1 transmit interrupt is used, omit settings À , ˆ , ˜ , ¯ and ˙ below.

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Fig. 2.5.19 Transmitting method in clock synchronous mode (2) Continued from Figure 2.5.18 ˜ Set the serial I/O1 transmit interrupt request to “0” ˆ One or more instructions (e.g., NOP ) after ´ IREQ1: Interrupt request register 1 [Address 3C16] b7 b0 b3: Serial I/O1 transmit interrupt request bit 0: No interrupts request issued ¯ Enable serial I/O1 transmit interrupt ICON1: Interrupt control register 1 [Address 3E16] b7 b0 b3: Serial I/O1 transmit interrupt enable bit 1: Interrupts enabled ˘ Set transmit data to transmit buffer register (TB) [Address 1816] ˙ Processing of serial I/O1 transmit interrupt

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Fig. 2.5.20 Receiving method in clock synchronous mode (1) SIO1CON: Serial I/O1 control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b7 b0 b2: SRDY1 output enable bit 0: P47/SRDY1 pin operates as I/O port P47 1: P47/SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) b4: Transmit enable bit 0: Transmit disabled 1: Transmit enabled b5: Receive enable bit 1: Receive enabled b6: Serial I/O1 mode selection bit 1: Clock synchronous serial I/O1 mode ´ Setting of serial I/O1 control register Selection of clock synchronous, receive, or others À Disable Serial I/O1 receive interrupt ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O1 receive interrupt enable bit 0: Interrupts disabled b7 b0 \ Set the value to baud rate generator (BRG) [Address 1C16] b1: Serial I/O synchronization clock selection bit (In clock synchronous mode) 0: BRG output/4 1: External clock input b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b7: Serial I/O1 enable bit 1: Serial I/O1 enabled (pins P4 4–P47 operate as serial I/O1 pins) Continued to Figure 2.5.21 [Notes on use] Notes 1: To use an INT pin or input port for watching SRDY1 , set as required. 2: When an external clock is selected in setting ´ below, BRG setting is not required in setting \ below. 3: In the full duplex data transfer mode, set the receive enable bit (bit 4) to “1” (receive enabled) in setting ´ below. 4: To use a serial I/O1 receive interrupt, set in the following sequence. 5: When no serial I/O1 receive interrupt is used, omit setting À , ˆ , ˜ , ¯ and ˙ below.

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Fig. 2.5.21 Receiving method in clock synchronous mode (2) Continued from Figure 2.5.20 ˜ Set the serial I/O1 receive interrupt request to “0” ˆ One or more instructions (e.g., NOP ) after ´ IREQ1: Interrupt request register 1 [Address 3C16] b7 b0 b2: Serial I/O1 receive interrupt request bit 0: No interrupt request issued ¯ Enable serial I/O1 receive interrupt ICON1: Interrupt control register 1 [Address 3E16] b7 b0 b2: Serial I/O1 receive interrupt enable bit 1: Interrupts enabled 1˘ Set transmit data to receive buffer register (RB) [Address 1816] In full duplex data transfer mode, set transmit data. In half duplex data transfer mode, set arbitrary dummy data. ˙ Processing of serial I/O1 receive interrupt

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(2) Clock asynchronous serial I/O (UART) mode Figure 2.5.25 show a receiving method in the UART mode. Fig. 2.5.22 Transmitting method in UART mode (1) SIO1CON: Serial I/O1 control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b7 b0 b2: SRDY1 output enable bit Invalied in UART mode b4: Transmit enable bit 1: Transmit enabled b5: Receive enable bit 0: Receive disabled 1: Receive enabled b6: Serial I/O1 mode selection bit 0: Clock asynchronous serial I/O1 (UART) mode 1 0 ´ Setting of serial I/O1 control register Selection of clock asynchronous mode, transmit, or others À Disable Serial I/O1 transmit interrupt ICON1: Interrupt control register 1 [Address 3E16] b3: Serial I/O1 transmit interrupt enable bit 0: Interrupts disabled b7 b0 \ Set the value to baud rate generator (BRG) [Address 1C16] b1: Serial I/O1 synchronization clock selection bit (In UART mode) 0: BRG output/16 1: External clock input/16 b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b7: Serial I/O1 enable bit 1: Serial I/O1 enabled (pins P4 4–P47 operate as serial I/O1 pins) Continued to Figure 2.5.23 [Notes on use] Notes 1: When an external clock is selected in setting ´ below, BRG setting is not required in setting \ below. 2: In the full duplex data transfer mode, set the receive enable bit (bit 5) to “1” (receive enabled) in setting ´ below. 3: To use a serial I/O1 transmit interrupt, set in the following sequence. 4: When no serial I/O1 transmit interrupt is used, omit setting À , ˜ , ¯ and ˙ below.

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Fig. 2.5.23 Transmitting method in UART mode (2) UARTCON: UART control register [Address 1B16] b0: Character length selection bit 0: 8 bits 1: 7 bits b7 b0 b2: Parity selection bit 0: Even parity 1: Odd parity b4: P45/TxD P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) ˆ Setting of UART control register b1: Parity enable bit 0: Parity checking disabled 1: Parity checking enabled b3: Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits Continued from Figure 2.5.22 ˜ Set the serial I/O1 transmit interrupt request to “0” (Allow an interval of one or more instructions after ´ ) IREQ1: Interrupt request register 1 [Address 3C16] b7 b0 b3: Serial I/O1 transmit interrupt request bit 0: No interrupt request issued ¯ Enable serial I/O1 transmit interrupt ICON1: Interrupt control register 1 [Address 3E16] b7 b0 b3: Serial I/O1 transmit interrupt enable bit 1: Interrupts enabled ˘ Set transmit data to transmit buffer register (TB) [Address 1816] ˙ Processing of serial I/O1 transmit interrupt : Nothing is allocated

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Fig. 2.5.24 Receiving method in UART mode (1) SIO1CON: Serial I/O1 control register [Address 1A16] b0: BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 b7 b0 b2: SRDY1 output enable bit Invalied in UART mode b4: Transmit enable bit 0: Transmit disabled 1: Transmit enabled b5: Receive enable bit 1: Receive enabled b6: Serial I/O1 mode selection bit 0: Clock asynchronous serial I/O1 (UART) mode 1 0 ´ Setting of serial I/O1 control register Selection of clock asynchronous, receive, or others À Disable Serial I/O1 receive interrupt ICON1: Interrupt control register 1 [Address 3E16] b2: Serial I/O1 receive interrupt enable bit 0: Interrupts disabled b7 b0 \ Set the value to baud rate generator (BRG) [Address 1C16] b1: Serial I/O1 synchronization clock selection bit (In UART mode) 0: BRG output/16 1: External clock input/16 b3: Transmit interrupt source selection bit 0: When transmit buffer has emptied 1: When transmit shift operation is completed b7: Serial I/O1 enable bit 1: Serial I/O1 enabled (pins P4 4–P47 operate as serial I/O1 pins) Continued to Figure 2.5.25 [Notes on use] Notes 1: When an external clock is selected in setting ´ below, BRG setting is not required in setting \ below. 2: In the full duplex data transfer mode, set the receive enable bit (bit 4) to “1” (receive enabled) in setting ´ below. 3: To use a serial I/O1 receive interrupt, set in the following sequence. 4: When no serial I/O1 receive interrupt is used, omit setting À , ˜ , ¯ and ˘ below.

3820 GROUP USER’S MANUAL2–136

Fig. 2.5.25 Receiving method in UART mode (2) UARTCON: UART control register [Address 1B16] b0: Character length selection bit 0: 8 bits 1: 7 bits b7 b0 b2: Parity selection bit 0: Even parity 1: Odd parity b4: P45/TxD P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) ˆ Setting of UART control register b1: Parity enable bit 0: Parity checking disabled 1: Parity checking enabled b3: Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits Continued from Figure 2.5.24 ˜ Clear the serial I/O1 receive interrupt request (Allow an interval of one or more instruction after ´ ) IREQ1: Interrupt request register 1 [Address 3C16] b7 b0 b2: Serial I/O1 receive interrupt request bit 0: No interrupt issued ¯ Enable serial I/O1 receive interrupt ICON1: Interrupt control register 1 [Address 3E16] b7 b0 b2: Serial I/O1 receive interrupt enable bit 1: Interrupts enabled 1˘ Processing of serial I/O1 receive interrupt : Nothing is allocated

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(3) Initialization of serial I/O1 operation The operating procedure of the serial I/O1 control register for initialization of the serial I/O1 operation is described below. n Initialization of receive operation By setting the receive enable bit (bit 5 of SIO1CON) to “0” or setting the serial I/O1 enable bit (bit 7 of SIO1CON) to “0,” the receive operation is stopped and initialized as shown below. The initialization items of receive operation are as follows.

• Stopping and initializing the shift clock to the receive shift register.
• Setting the receive shift register to “0.”
• Setting each error flag (overrun error flag, parity error flag, framing error flag, summing error flag) to “0.”
• Setting the receive buffer full flag (RBF) to “0.” n Initialization of transmit operation Basically, the transmit operation is stopped and initialized by setting the transmit enable bit (bit 4 of SIO1CON) to “0.” The initialization items of transmit operation are as follows.
• Stopping and initializing the shift clock to the transmit shift register.
• Setting the receive shift register to “0.” (However, when an external clock is used in the clock synchronous mode, the receive shift register is not set to “0” unless the input clock of the S CLK1 pin is “H.”)
• Setting the transmit buffer empty flag (bit 0 of SIO1STS) and the transmit shift register shift comple- tion flag (bit 2 of SIO1STS) to “0.” (When bit 4 is set to “0,” bits 0 and 2 are cleared to “0” forcibly. After that, when bit 4 is set to “1,” bits 0 and 2 are set to “1.”) When all conditions below are satisfied, initialization is not performed only by setting bit 4 of SIO1CON to “0.” It is also necessary to set bit 5 of SIO1CON to “0.”
• In the full duplex data transfer
• In the clock synchronous mode
• When an internal clock is used
• When bit 5 of SIO1CON is “1” (receive enabled) In the clock synchronous mode of the full duplex data transfer, the same clock is used for transmission and reception. When an internal clock is used, the shift clock is started by writing data into the transmit buffer at both transmission and reception, so both transmit and receive operations use a clock generating circuit of the transmitter. Because of this, the serial I/O1 is designed so that even if only a receive operation is performed, the transmit circuit may be operated internally to generate a shift clock when an internal clock is used in the clock synchronous mode. Accordingly, note that the transmitter may operate even when bit 4 of SIO1CON is “0.” The transmit operation cannot be initialized only by setting the serial I/O1 enable bit (bit 7 of SIO1CON) to “0.”

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(4) Processing upon occurrence of an errors n Parity error, framing error, or summing error If a parity error, a framing error, or a summing error occurs, the flag corresponding to each error in the serial I/O1 status register is set to “1.” These flags cannot be cleared to “0” automatically, so set them to “0” by software. The parity error flag, framing error flag, and summing error flag is set to “0” by setting the receive enable bit to “0” or writing dummy data into the serial I/O1 status register. n Overrun error An overrun error occurs when data is already input in the receive buffer register and yet all data is input in the receive shift register. If an overrun error occurs, the data of the receive shift register is not transferred and the data of the receive buffer register is held. At this time, even if the data of the receive buffer register is read out, the data of the receive shift register is not transferred. Consequently, the data of the receive shift register becomes unreadable, so that the receive data becomes invalid. If an overrun error occurs, after set the overrun error flag of the serial I/O1 status register to “0,” perform a receive operation again. The overrun error flag is set to “0” by one of the following operations.

• Set the serial I/O1 enable bit to “0”
• Set the receive enable bit to “0”
• Write data (arbitrary) into the serial I/O1 status register

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2.5.5 Notes on use

(1) Notes on clock selection The 3820 group can select either internal clock or external clock as a synchronizing clock. When an external clock is selected as an synchronizing clock in the clock synchronous mode, note the follow- ing. n In the clock synchronous mode À For an external clock source, when the duty cycle is 50%, use the following clock. CC = 4.0 V to 5.5 V To change the duty cycle, set the both “H” and “L” widths as follows. CC = 4.0 V to 5.5 V \ The shift operation of the transmit shift register or the receive shift register is continued while synchronizing clocks are input to the serial I/O1 circuit. Accordingly, stop a synchronizing clock input after 8 clocks are input. When the internal clock is selected, the synchronizing clock input is automatically stopped. ´ To select an external clock as a synchronizing clock at data transmission, set the transmit enable bit to “1” and write data into the transmit buffer register while the SCLK1 signal is “H.” When an external clock is selected as a synchronizing clock in the UART mode, note the following. n In the UART mode For an external clock source, when the duty ratio is 50%, use the following clock. CC = 4.0 V to 5.5 V To change the duty cycle, set the “H” and “L” widths as follows. (2) For serial I/O1 transmit or receive interrupts À For a serial I/O1 transmit interrupt, set a value in the serial I/O1 control register, then set the serial I/O1 transmit interrupt request bit (bit 3 at address 003C16) to “0” with the CLB instruction. \ After setting À , set the serial I/O1 transmit enable bit (bit 3 at address 003E16) to “1.” ´ For a serial I/O1 receive interrupt, set a value in the serial I/O1 control register, then set the serial I/O1 receive interrupt request bit (bit 2 at address 003C16) to “0” with the CLB instruction. ˆ After setting ´ , set the serial I/O1 receive interrupt enable bit (bit 2 at address 003E16) to “1.” (3) Transmit interrupt request when the transmit enable bit is “1” When the transmit enable bit is set to “1,” the transmit buffer empty flag and the transmit shift register shift completion flag are set to “1.” Accordingly, even if either timing is selected as transmit interrupt generating timing, an serial I/O1 transmit interrupt request occurs and the serial I/O1 transmit interrupt request bit is set to “1.” To use a serial I/O1 transmit interrupt, set the transmit enable bit to “1,” then set the serial I/O1 transmit interrupt request bit to “0” once. After that, set the serial I/O1 transmit interrupt enable bit to “1” (interrupts enabled).

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(4) For disabling transmission after completion of 1-byte data transmission As a means to know the completion of data transmission, a reference to the transmit shift register shift completion flag (TSC flag) is available in the 3820 group. The TSC flag is cleared to “0” during data transmission. Upon the completion of data transmission, this flag is set to “1.” Accordingly, after confirming that the TSC flag is set to “1,” disable transmission. The transmission can thus be terminated after 1-byte transmission. However, the TSC flag is set to “1” even when the serial I/O1 enable bit is set to “1” (serial I/O1 enabled). After that, it is not cleared to “0” until transmission is started by generating a shift clock. For this reason, if transmission is disabled by referring to the TSC flag at this time, data is not transmitted. After the transmission is started, refer to the TSC flag. (5) When the P4 5/TxD pin is used as an N-channel open-drain output Bit 4 of the UART control register (address 001B16) is the P45/TxD P-channel output disable bit. The bit 4 is valid in an ordinary port, in the clock synchronous mode, or in the UART mode. When this bit is “0,” the ordinary CMOS output is selected. When the bit is “1,” the N-channel open- drain output is selected. However, do not apply to the P45/TX D a voltage of VCC + 0.3 V or more even when it is used as a serial I/O1 function pin of the N-channel open-drain output.

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2.6.1 Explanation of operations

The operations of the serial I/O2 are described below. The serial I/O2 operates only in the clock synchro- nous mode. When serial I/O2 is actually used, refer to “2.6.4 Register setting example.” (1) Clock synchronous serial I/O mode In the clock synchronous mode, 8 shift clocks generated in the synchronization circuit are used as synchronizing clocks for transfer. In synchronization with these shift clocks, the transmit operation on the transmitter and the receive operation on the receiver are simultaneously executed. The transmitter transmits each 1-bit data from the P5 1/SOUT2 pin in synchronization with the falling of the shift clocks. The receiver receives each 1-bit data from the P50/SIN2 pin in synchronization with the rising of the shift clocks. Figure 2.6.1 shows an external connection example of the serial I/O2. Fig. 2.6.1 External connection example of serial I/O2 3820 group À Internal clock is selected External clock is selected 3820 group \` SIN2 SCLK2 SOUT2Serial I/O2 register XIN Divider Synchronization circuit SIN2 SCLK2 SOUT2 Serial I/O2 register Synchronization circuit

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Ordinarily, when clock synchronous transfer is performed between microcomputers, an internal clock is selected for one of them, and it outputs 8 shift clocks generated by a start of transmit operation from the P52/SCLK2 pin. An external clock is selected for the other microcomputer, and it uses the clock input from the P52/SCLK2 pin as a shift clock. Figure 2.6.2 shows a shift clock. Fig. 2.6.2 Shift clock 3820 group À Internal clock is selected External clock is selected 3820 group \` SIN2 SCLK2 SOUT2Serial I/O2 register XIN Divider Synchronization circuit SIN2 SCLK2 SOUT2 Serial I/O2 register Shift clock Synchronization circuit

2–1433820 GROUP USER’S MANUAL n Transmit operation of the serial I/O2 Transmit operation of the serial I/O2 is described below (When LSB first is selected). l Start of transmit operation A transmit operation is started by writing transmit data into the serial I/O2 register (address 001F16) in the transmit enable state.] 1 l Transmit operation À The transmit data written in the serial I/O2 register is output from the P51/SOUT2 pin in synchronization with the falling of the shift clocks. \` The data is output from the least significant bit of the serial I/O2 register. Each time 1-bit data is output, the data of the serial I/O2 register is shifted by 1 bit toward the least significant bit. ´ When 8-bit transmit data has been transferred, the serial I/O2 interrupt request bit is set to “1” in synchronization with the rising of a shift clock. ] 2 ] 1: Initialization of register or others for a trans- mit operation. Refer to “2.6.4 Register set- ting example.” ] 2: When an internal clock is used as a syn- chronizing clock, supplying the shift clock to the serial I/O2 register stops automati- cally at the completion of 8-bit transmis- sion. Serial I/O2 register P51/SOUT2 D 0D 1D 2D 3D 4D 5D 6D 7 Serial I/O2 register P51/SOUT2 D 1 D 2D 3D 4D 5D 6D 7 Serial I/O2 register P51/SOUT2 D 7 Interrupt request register 2 [Address 3D16] 1

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Fig. 2.6.3 Transmit operation of serial I/O2 Fig. 2.6.4 Transmit timing example of serial I/O2 Serial I/O2 registerShift clock D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 7 LSB first (when bit 5 of serial I/O2 control register is “0”) is selected D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SOUT2 Shift clock

2–1453820 GROUP USER’S MANUAL n Receive operation of the serial I/O2 Receive operation of the serial I/O2 is described below (When LSB first is selected). l Start of receive operation A receive operation is started by writing the following data into the serial I/O2 register (address 001F 16) in the receive enable state.] 1

• Transmit data in the full duplex data transfer mode
• Arbitrary dummy data in the half duplex data transfer mode l Receive operation À Each 1-bit data is read into the serial I/O2 register from the P5 0/SIN2 pin in synchroni- zation with the rising of the shift clocks. \` The data enters first into the most significant bit of the serial I/O2 register. Each time 1-bit data is received, the data of the serial I/O2 register is shifted by 1 bit toward the least significant bit. ´ When 8-bit receive data transfer is completed, the serial I/O2 interrupt request bit is set to “1” in synchronization with the rising of a shift clock. ] 2 ] 1: Initialization of register or others for a trans- mit operation. Refer to “2.6.4 Register set- ting example.” ] 2: When an internal clock is used as a syn- chronizing clock, supplying the shift clock to the serial I/O2 register stops automati- cally at the completion of 8-bit transmis- sion. Serial I/O2 registerP50/SIN2 D 1 D 0 Serial I/O2 register D 4 P50/SIN2 D 3 D 0D 1D 2 P50/SIN2 D 7 D 4D 5D 6 Interrupt request register 2 [Address 3D16] Serial I/O2 register D 3 D 0D 1D 2

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Fig. 2.6.5 Receive operation of serial I/O2 Fig. 2.6.6 Receive timing example of serial I/O2 Shift clock Serial I/O2 register D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 2 D 1 D 0 D 0 D 1 D 0 LSB first (when bit 5 of serial I/O2 control register is “0”) is selected D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7RxD Shift clock

2–1473820 GROUP USER’S MANUAL n Transmit/receive timing example of the serial I/O2 Figure 2.6.7 shows a transmit/receive timing example of the serial I/O2 (the P53/SRDY2 pin is used). Fig. 2.6.7 Transmit/receive timing example of serial I/O2 (P53/SRDY2 pin is used) 3820 group À 3820 group \` SCLK2 SIN2 SRDY2 SOUT2 SCLK2 P53(SRDY2 ) Note: When an internal clock is selected, the P51/SOUT2 pin is put into the high-impedance state after the completion of a transmit/receive. Shift clock Serial I/O2 register write signal Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Set an interrupt request bit (Note)

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2.6.2 Pins

The serial I/O2 uses 4 pins, namely, pins for data transmit, data receive, shift clock transmit/receive, and receive enable signal output. All these pins are also used as port P5 and switched their functions by the serial I/O2 port selection bit (bit 3), S RDY2 output enable bit (bit 4) and synchronization clock selection bit (bit 6) of the serial I/O2 control register (address 001D16). The function of each pin is described below. (1) Data transmit pin [SOUT2 ] This pin outputs each bit of transmit data and is used as port P51. When the serial I/O2 port selection bit (bit 3) of the serial I/O2 control register is set to “1,” this pin functions as a serial I/O2 data output pin. (2) Data receive pin [SIN2] This pin inputs each bit of receive data and is used as port P50. There is no register for selecting between port function and data input pin function. Clear bit 5 of the port P5 direction register to “0” (input mode). (3) Shift clock transmit/receive pin [SCLK2 ] This pin inputs (receives from the outside) or outputs (supplies to the outside) a shift clock used for transmission and reception. When the synchronization clock selection bit (bit 6) of the serial I/O2 control register is set to “0” (use of external clock), a shift clock is input from the outside. When this bit is set to “1” (use of internal clock), a shift clock is output to the outside. (4) Receive enable signal output pin [ S RDY2 ] This pin notifies the outside of the receive enable state in the clock synchronous mode. This pin functions as the receive enable signal output pin by setting the SRDY2 output enable bit (bit 4) of the serial I/O2 control register to “1.” The pin level changes from “H” to “L” at the timing which data is written into the serial I/O2 register, notifying the outside of the receive enable state.

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2.6.3 Related registers

Figure 2.6.8 shows the memory allocation of the serial I/O2-related registers. They are the serial I/O2 control register and serial I/O2 register. (1) Serial I/O2 control register (SIO2CON) The serial I/O2 control register (address 001D16) controls the serial I/O2 function. Fig. 2.6.9 Structure of serial I/O2 control register Fig. 2.6.8 Memory allocation of serial I/O2-related registers Serial I/O2 control register (SIO2CON) Address 001D 16 001F16 Serial I/O2 register (SIO2) b7b6 b5b4b3 b2b1b0 Serial I/O2 control register (SIO2CON) [Address 1D16] B At reset R W Serial I/O2 control register Name Functions Internal synchronization clock select bits 0 0 0: f(X IN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: 1 0 1: 1 1 0: f(X IN)/128 1 1 1: f(XIN)/256 SRDY2 output enable bit Transfer direction selection bit Synchronization clock selection bit Serial I/O2 port selection bit I/O port (P51, P52) 1: SOUT2 , SCLK2 signal output 0: I/O port (P53) 1: SRDY2 signal output 0: LSB first 1: MSB first 0: External clock 1: Internal clock b2b1b0 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 1 0 Do not set

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n Internal synchronization clock select bits (bit 2–bit 0) When an internal clock is selected as serial I/O2 synchronization clocks (bit 6 = 1), these bits select an internal clock division ratio. b2 b1 b0 00 0 0 01 0 10 10 0 1 01 11 0 1 11 X IN pin input clock/8 X IN pin input clock/16 X IN pin input clock/32 X IN pin input clock/64 X IN pin input clock/128 X IN pin input clock/256 Do not set. Synchronizing clock of serial I/O2 (when internal clock is selected) n Serial I/O2 port selection bit (bit 3) This bit is used to select the functions of the P51/SOUT2 pin and P52/SCLK2 pin. When this bit is set to “0,” the I/O port P51 and P52 functions are selected. When the bit is set to “1,” the SOUT2 and SCLK2 pin functions for serial I/O2 are selected. n S RDY2 output enable bit (bit 4) This bit is used to select the P53/SRDY2 pin function. When this bit is set to “1,” the I/O port P53 function is selected. When the bit is set to “1,” the SRDY2 pin function for serial I/O2 is selected. n Transfer direction selection bit (bit 5) This bit is used to select a transfer direction for serial data of the serial I/O2. When this bit is set to “0,” LSB first (transfer from the least significant bit) is selected. When the bit is set to “1,” MSB first (transfer from the most significant bit) is selected. n Synchronization clock selection bit (bit 6) This bit is used to select a synchronizing clock of the serial I/O2. When this bit is set to “0,” an external clock is selected. When the bit is set to “1,” an internal clock is selected. Table 2.6.1 Relation between internal synchronization clock selection bit and synchronizing clock

2–1513820 GROUP USER’S MANUAL (2) Serial I/O2 register (SIO2) A transmit/receive operation is started by writing transfer data into the serial I/O2 register (address 001F 16). Figure 2.6.10 shows the structure of the serial I/O2 register. Fig. 2.6.10 Structure of serial I/O2 register b7b6 b5b4b3 b2b1b0 Serial I/O2 register (SIO2) [Address 1F16] B Functions At reset R W Serial I/O2 register to ?At transmit

• Set “0016 to FF16” as transmit data.
• The transmit data is transferred automatically to the serial I/O shift register 2 by writing transmit data. At receive
• When all receive data has been input into the serial I/O shift register 2, the receive data is automatically transferred to this register.

3820 GROUP USER’S MANUAL2–152

2.6.4 Register setting example

Figure 2.6.11 shows a transmitting method of the serial I/O2, Figure 2.6.12 shows a receiving method of the serial I/O2. Fig. 2.6.11 Transmitting method of serial I/O2 SIO2CON: Serial I/O2 control register [Address 1D16] b2–b0: Internal synchronization clock select bits 000: f(XIN)/8 001: f(XIN)/16 010: f(XIN)/32 b7 b0 b4: SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output \ Setting of serial I/O2 control register Selection of serial I/O2, or others À Disable Serial I/O2 interrupt ICON2: Interrupt control register 2 [Address 3F16] b6: Serial I/O2 interrupt enable bit 0: Interrupts disabled b7 b0 b5: Transfer direction selection bit 0: LSB first 1: MSB first [Notes on use] Notes 1: To use an INT pin or input port for SRDY2 watchdog, set as required. 2: To use a serial I/O2 interrupt, set in the following sequence. 3: When no serial I/O2 interrupt is used, omit settings À , ´ , ˆ , ˜ and ˘ below. b3: Serial I/O2 port selection bit 1: S OUT2 , SCLK2 signal output ˆ Set the serial I/O2 interrupt request to “0” ´ One or more instructions (e.g., NOP ) after \ IREQ2: Interrupt request register 2 [Address 3D16] b7 b0 b6: Serial I/O2 interrupt request bit 0: No interrupts request issued ˜ Enable serial I/O2 interrupt ICON2: Interrupt control register 2 [Address 3F16] b7 b0 b6: Serial I/O2 interrupt enable bit 1: Interrupts enabled ¯ Set transmit data to serial I/O2 register SIO2 [Address 1F16] ˘ Processing of serial I/O2 interrupt : Nothing is allocated : Nothing is allocated 011: f(XIN)/64 110: f(XIN)/128 111: f(XIN)/256 b6: Synchronization clock selection bit 0: External clock 1: Internal clock

2–1533820 GROUP USER’S MANUAL Fig. 2.6.12 Receiving method of serial I/O2 SIO2CON: Serial I/O2 control register [Address 1D16] b2–b0: Internal synchronization clock select bits 000: f(XIN)/8 001: f(XIN)/16 010: f(XIN)/32 b7 b0 b4: SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output \ Setting of serial I/O2 control register Selection of serial I/O2, or others À Disable Serial I/O2 interrupt ICON2: Interrupt control register 2 [Address 3F16] b6: Serial I/O2 interrupt enable bit 0: Interrupts disabled b7 b0 b5: Transfer direction selection bit 0: LSB first 1: MSB first Notes 1: When SRDY2 signal output is not used, set the SRDY2 output enable bit (bit 4) to “0” in \ below. 2: In the duplex data transfer mode, write transmit data in ¯ below. 3: To use a serial I/O2 interrupt, set in the following sequence. 4: When no serial I/O2 interrupt is used, omit settings À , ´ , ˆ , ˜ and ˘ below. b3: Serial I/O2 port selection bit 1: S OUT2 , SCLK2 signal output ˆ Set the serial I/O2 interrupt request to “0” ´ One or more instructions (e.g., NOP ) after \` IREQ2: Interrupt request register 2 [Address 3D16] b7 b0 b6: Serial I/O2 interrupt request bit 0: No interrupts request issued ˜ Enable serial I/O2 interrupt ICON2: Interrupt control register 2 [Address 3F16] b7 b0 b6: Serial I/O2 interrupt enable bit 1: Interrupts enabled ¯ Set dummy data to serial I/O2 register SIO2 [Address 1F16] (When SRDY2 is used, “L” is output from the P53/SRDY2 pin) : Nothing is allocated : Nothing is allocated 011: f(XIN)/64 110: f(XIN)/128 111: f(XIN)/256 ˘ Processing of serial I/O2 interrupt b6: Synchronization clock selection bit 0: External clock 1: Internal clock [Notes on use]

3820 GROUP USER’S MANUAL2–154

2.6.5 Notes on use

(1) Notes on synchronizing clock selection Whether an internal clock or an external clock is selected as a serial I/O2 synchronizing clock source, the serial I/O2 interrupt request bit is set to “1” when 8 shift clocks are input. However, while the shift clocks are input to the serial I/O2 synchronization circuit, the contents of the serial I/O2 register are continuously shifted. For this reason, it is necessary to stop the shift clocks at the time when 8 shift clocks have been input. When an internal clock is selected, the shift clocks are automatically stopped at the time when 8 shift clocks have been input. When an external clock is selected, control shift clocks externally. As an external clock, satisfy the following conditions when the duty cycle is 50%. CC = 4.0 V to 5.5 V Furthermore, satisfy the following conditions of both “H” and “L” width when changing the duty cycle. (2) Notes on shift clock source switching When the shift clock of the serial I/O2 has been switched, initialize the serial I/O counter 2 (i.e., write to the serial I/O2 register). (3) Serial I/O counter 2 initialization when an external clock is selected When an external clock is selected, initialize the serial I/O counter 2 (i.e., write to the serial I/O2 register) at “H” level of the external clock. (4) For serial I/O2 interrupts To use a serial I/O2 interrupt, set according to the following procedure. À Set the serial I/O2 interrupt enable bit (bit 6 at address 003F 16) to “0” with the CLB instruction. \` Set a value in the serial I/O2 control register (address 001D16). ´ After executing one or more instructions (e.g., NOP instruction), set the serial I/O2 interrupt request bit (bit 6 at address 003D16) to “0” with the CLB instruction. ˆ Set the serial I/O2 interrupt enable bit to “1” with the SEB instruction. (5) Restart of communication after stopping it during serial transmission or reception To restart communication after stopping it during serial I/O2 transmission or reception, execute from writing into the serial I/O2 control register.

2.7 LCD drive control circuit

2–1553820 GROUP USER’S MANUAL The 3820 group includes the controller/drivers of Liquid Crystal Display (LCD). This section describes an explanation of LCD control circuit operations, pins, related registers, usage and application examples.

2.7.1 Explanation of operations

(1) LCD drive waveform example Refer to “CHAPTER 1 Hardware, LCD drive control circuit.” (2) LCD drive timing The frequency of the internal signal LCDCK and the frame frequency to generate LCD drive timing are as follows. Count source frequency for LCDCK Division ratio of LCD circuit divider f (LCDCK) = Frame frequency = f (LCDCK) Duty ratio number

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2.7.2 Pins

SEG 0–SEG 15 are used as pins for LCD display. The pins P30/SEG 16–P3 7/SEG 23 and P00/SEG 24–P0 7/ SEG 31 and P10/SEG 32–P1 7/SEG 39 are available as segment output pins (SEG16–SEG 39). By switching the corresponding registers, the segment output pin, I/O pin or input pin is selected. Table 2.7.1 shows the pin function by setting segment output enable register and Table 2.7.2 shows the pin functions by setting the corresponding registers when they are not used as segment output pins. Pins Table 2.7.1 Pin functions by setting segment output enable register P3 0/SEG 16 –P3 7/SEG 23 P0 0/SEG 24, P0 1/SEG 25 P1 0/SEG 32, P1 1/SEG 33 P0 2/SEG 26– P0 7/SEG 31 P1 3/SEG 35– P1 7/SEG 39 P1 2/SEG 34 Pin functionRegister Value Note: When the microcomputer is in the reset state, the I/O or segment output pins are pulled down, so that a “L” level is output from segment-only pins. Setting SEG (Address 0038 16) b0 (Bit 0 of segment output enable register) SEG (Address 0038 16) b1 (Bit 1 of segment output enable register) SEG (Address 0038 16) b2 (Bit 2 of segment output enable register) SEG (Address 0038 16) b3 (Bit 3 of segment output enable register) SEG (Address 0038 16) b4 (Bit 4 of segment output enable register) SEG (Address 0038 16) b5 (Bit 5 of segment output enable register) Segment output Input port Segment output I/O port Segment output I/O port I/O port Segment output I/O port Segment output I/O port Segment output

2–1573820 GROUP USER’S MANUAL Table 2.7.2 Pin functions by setting the corresponding registers when they are not used as seg- ment output pins Ports Pins (1) Segment output pins (SEG0–SEG 39) Up to 40 segment outputs can be selected. Table 2.7.3 shows setting of segment output pins for LCD display. Table 2.7.3 Setting of segment output pins for LCD display PULLA (Address 0016 16) b3 (Bit 3 of PULL register A) P1D (Address 000316) b0 (Bit 0 of port P1 direction register) P0D (Address 000116) b0 (Bit 0 of port P0 direction register) PULLA (Address 0016 16) b0 (Bit 0 of PULL register A) PULLA (Address 0016 16) b1 (Bit 1 of PULL register A) Setting Register Value Pin function Output port Input port Output port Pull-down pin SEG 0–SEG 15 Segment output-only pin P0 0–P0 7 P1 0–P1 7 P3 0–P3 7 Setting

0 Input port

(When being set for the input mode) Pull-down pin (When being set for the input mode) Ports P30–P3 7 are used as segment signal output pins (SEG16–SEG 23) by setting bit 0 of the segment output enable register (address 003816) to “1.” Ports P00 and P01 are used as segment signal output pins (SEG24, SEG25) by setting bit 1 of the segment output enable register (address 003816) to “1.” Ports P02–P0 7 are used as segment signal output pins (SEG26–SEG 31) by setting bit 2 of the segment output enable register (address 003816) to “1.” Ports P10 and P11 are used as segment signal output pins (SEG32, SEG33) by setting bit 3 of the segment output enable register (address 003816) to “1.” P1 2/SEG 34 Port P12 is used as segment signal output pins (SEG34) by setting bit 4 of the segment output enable register (address 003816) to “1.” Ports P13–P1 7 are used as segment signal output pins (SEG35–SEG 39) by setting bit 5 of the segment output enable register (address 003816) to “1.” P3 0/SEG 16– P3 7/SEG 23 P0 0/SEG 24, P0 1/SEG 25 P0 2/SEG 26– P0 7/SEG 31 P1 0/SEG 32, P1 1/SEG 33 P1 3/SEG 35– P1 7/SEG 39 No pull-down

0 No pull-down

(When being set for the input mode) (When being set for the input mode)

2–158 3820 GROUP USER’S MANUAL (2) Ports P0, P1 and P3 When pins P3 0/SEG 16–P3 7/SEG 23, P00/SEG 24–P0 7/SEG 31, P10/SEG 32–P1 7/SEG 39 are not used as segment outputs, they can be used as input port P3 and as I/O ports P0 and P1. Table 2.7.4 shows the setting of input port P3 and I/O ports P0, P1. Ports Table 2.7.4 Setting of input port P3 and I/O ports P0, P1 (3) P3, P1 and P0 pull-down pins When pins P30/SEG 16–P3 7/SEG 23, P00/SEG 24–P0 7/SEG 31, P10/SEG 32–P1 7/SEG 39 are not used as ports, it is possible to exert pull-down control. Table 2.7.5 shows the setting of pull-down pins. Pins Table 2.7.5 Setting of pull-down pins P3 0–P3 7 P0 0, P01 P0 2–P0 7 P1 0, P11 P1 2 P1 3–P1 7 Setting By setting bit 0 of the segment output enable register (address 003816) to “0,” then setting bit 3 of PULL register A (address 001616) to “1.” By setting bits 1 and 2 of the segment output enable register (address 003816) to “0,” next setting bit 0 of the port P0 direction register (address 000116) to “0,” then setting bit 0 of PULL register A (address 001616) to “1.” Setting By setting bit 0 of segment output enable register (address 003816) to “0” By setting bit 1 of segment output enable register (address 003816) to “0” By setting bit 2 of segment output enable register (address 003816) to “0” By setting bit 3 of segment output enable register (address 003816) to “0” By setting bit 4 of segment output enable register (address 003816) to “0” By setting bit 5 of segment output enable register (address 003816) to “0” By setting bits 3 to 5 of the segment output enable register (address 003816) to “0,” next setting bit 1 of the port P1 direction register (address 000316) to “0,” then setting bit 1 of PULL register A (address 001616) to “1.” P3 0/SEG 16– P3 7/SEG 23 P0 0/SEG 24– P0 7/SEG 31 P1 0/SEG 32– P1 7/SEG 39

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2.7.3 Related registers

Figure 2.7.1 shows the memory allocation of LCD display-related registers. Fig. 2.7.1 Memory allocation of LCD display-related registers Port P0 direction register (P0D) Port P1 direction register (P1D) PULL register A (PULLA) Segment output enable register (SEG) LCD mode register (LM) 000116 000316 001616 003816 003916 Address

2–160 3820 GROUP USER’S MANUAL (1) Segment output enable register (address 003816) The pins P30/SEG 16–P37/SEG 23, P00/SEG 24–P07/SEG 31, P10/SEG 32–P17/SEG 39 can be used as segment output pins by setting bits 0 to 5 of the segment output enable register (address 003816). The pins corresponding to the bits which are set to “1” among bits 0 to 5 of the segment output enable register (address 003816) are used as segment output pins. The pins corresponding to the bits which are set to “0” are used as I/O ports or input ports. Figure 2.7.2 shows the structure of the segment output enable register. Fig. 2.7.2 Structure of segment output enable register b7b6 b5b4b3 b2b1b0 Segment output enable register (SEG) [Address 3816] B Name Functions At reset R W Segment output enable register Segment output enable bit 0 00 0 Fix these bits to “0.” Segment output enable bit 1 Segment output enable bit 2 Segment output enable bit 3 Segment output enable bit 4 Segment output enable bit 5 0: Input ports P30–P37 1: Segment output SEG16–SEG 23 0: I/O ports P00, P01 1: Segment output SEG24, SEG25 0: I/O ports P02–P07 1: Segment output SEG26–SEG 31 0: I/O port P12 1: Segment output SEG34 0: I/O ports P10, P11 1: Segment output SEG32, SEG33 0: I/O ports P13–P17 1: Segment output SEG35–SEG 39 6,7

2–1613820 GROUP USER’S MANUAL (2) LCD mode register (LM) The LCD mode register (address 003916) controls various functions of the LCD controller/driver. Figure 2.7.3 shows the structure of the LCD mode register. l Bits 0, 1 : Duty ratio selection bits Select a duty ratio number fit for the LCD panel used. l Bit 2 : Bias control bit Select a bias value fit for the LCD panel used. l Bit 3 : LCD enable bit Turns on and off the LCD. When this bit is set to “1,” the bits which are set to “1” in the LCD display RAM are displayed on the LCD. When this bit is set to “0,” the whole LCD display is turned off. l Bit 4 : Unused Always set this bit to “0.” l Bits 5, 6 : LCD circuit divider division ratio selection bits These bits are used to select a division ratio for generating the frequency of the LCDCK, which is the clock for the LCD timing controller. Select a division ratio so as to generate LCDCK fit for the LCD panel used. l Bit 7 : LCDCK count source selection bit This bit is used to select a count source of the above LCDCK. At transition from the high-speed, middle-speed or low-speed mode to the low-power operation, or others, change the count source as required.

2–162 3820 GROUP USER’S MANUAL Fig. 2.7.3 Structure of LCD mode register b7b6 b5b4b3 b2b1b0 LCD mode register (LM) [Address 3916] B Name Functions At reset R W LCD mode register Duty ratio selection bits LCDCK count source selection bit (Note 2) Bias control bit LCD enable bit Fix this bit to “0.” LCD circuit divider division ratio selection bits (Note 1) b1b0 00: Not available 01: 2 (use COM 0, COM1) 10: 3 (use COM0–COM 2) 11: 4 (use COM0–COM 3) 0: 1/3 bias 1: 1/2 bias 0: LCD OFF 1: LCD ON 0: f(X CIN)/32 1: f(XIN)/8192 b6b5 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source Notes 1: Reference values at f(XIN) = 8 MHz 00: 977 Hz 01: 488 Hz 10: 244 Hz 11: 122 Hz 2: LCDCK is a clock for a LCD timing controller.

2–1633820 GROUP USER’S MANUAL (3) Port P0 direction register (P0D) When it is specified that pins P00/SEG 24–P0 7/SEG 31 are used as I/O ports by bits 1 and 2 of the segment output enable register (address 003816), the setting of the port P0 direction register (address 0001 16) is valid. When bit 0 of the port P0 direction register is set to “1,” port P0 is an output port. When this bit is set to “0,” the port is an input port, so that the setting of bit 0 of the PULL register A (address 001616) becomes valid. At reset, bit 0 of the port P0 direction register is set to “0.” Figure 2.7.4 shows the structure of the port P0 direction register. Fig. 2.7.4 Structure of port P0 direction register b7b6 b5b4b3 b2b1b0 Port P0 direction register (P0D) [Address 0116] B Name Functions At reset R W Port P0 direction register to Port P0 direction register 0: All bits are input mode 1: All bits are output mode Nothing is allocated. These bits cannot be written to and be read out.

2–164 3820 GROUP USER’S MANUAL (4) Port P1 direction register (P1D) When it is specified that pins P10/SEG 32–P1 7/SEG 39 are used as I/O ports by bits 3 to 5 of the segment output enable register (address 003816), the setting of the port P1 direction register (address 0003 16) is valid. When bit 0 of the port P1 direction register (address 000316) is set to “1,” port P1 is an output port. When this bit is set to “0,” the port is an input port, so that the setting of bit 1 of the PULL register A (address 001616) becomes valid. At reset, bit 0 of the port P1 direction register is set to “0.” Figure 2.7.5 shows the structure of the port P1 direction register. Fig. 2.7.5 Structure of port P1 direction register b7b6 b5b4b3 b2b1b0 Port P1 direction register (P1D) [Address 0316] B Name Functions At reset R W Port P1 direction register to Port P1 direction register 0: All bits are input mode 1: All bits are output mode Nothing is allocated. These bits cannot be written to and be read out.

2–1653820 GROUP USER’S MANUAL (5) PULL register A (PULLA) When ports P0, P1 and P3 are set for the input mode, the setting of bits 0, 1 and 3 of the PULL register A (address 001616) is valid. The pull-down function of ports P0, P1 and P3 is made effective by setting bits 0, 1 and 3 of the PULL register A to “1.” When ports P0 and P1 are set for output mode by bit 0 of the port P0/P1 direction registers, the setting of the PULL register A is invalid. Figure 2.7.6 shows the structure of the PULL register A. Fig. 2.7.6 Structure of PULL register A b7b6 b5b4b3 b2b1b0 PULL register A (PULLA) [Address 1616] B Name Function At resetR W PULL register A

0 Ports P00–P07 pull-down bit0 : No pull-down

1 : Pull-down Note: For ports set for the output mode, pull-up or pull-down is impossible.

1 Ports P10–P17 pull-down bit0 : No pull-down

1 : Pull-down

2 Ports P20–P27 pull-up bit 0 : No pull-up

1 : Pull-up

3 Ports P30–P37 pull-down bit0 : No pull-down

1 : Pull-down

4 Ports P70, P71 pull-up bit 0 : No pull-up

1 : Pull-up to Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. 0 0

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2.7.4 Register setting example

Fig. 2.7.7 Example of setting registers for LCD display (1) SEG: Segment output enable register [Address 3816] b0: Segment output enable bit 0 0: Input ports P30–P37 1: Segment output SEG16–SEG 23 b7 b0 b3: Segment output enable bit 3 0: Input ports P1 0, P11 1: Segment output SEG32, SEG33 b4: Segment output enable bit 4 0: Input port P1 1: Segment output SEG34 b7, b6: Fix these bits to “0” b5: Segment output enable bit 5 0: Input ports P1 3–P17 1: Segment output SEG35–SEG 39 À Setting of segment output enable register Select segment pins or others b1: Segment output enable bit 1 0: Input ports P0 0, P01 1: Segment output SEG24, SEG25 b2: Segment output enable bit 2 0: Input ports P0 2–P07 1: Segment output SEG26–SEG 31 Continued to Figure 2.7.8 [Note on use] Note : For pulling down ports P0, P1 and P3, refer to “2.7.2 Pins, (3) Ports P3, P1 and P0 pull–down pins”

2–1673820 GROUP USER’S MANUAL Fig. 2.7.8 Example of setting registers for LCD display (2) LM: LCD mode register [Address 3916] b1, b0: Duty ratio selection bits b1b0 00: Not used 01: 2 (use COM 0, COM1) 10: 3 (use COM0–COM 2) 11: 4 (use COM0–COM 3) b7 b0 b3: LCD enable bit 0: LCD OFF 1: LCD ON b4: Fix this bit to “0” b7: LCDCK count source selection bit 0: f(X CIN)/32 1: f(XIN)/8192 \` Setting of LCD mode register Select count source, bias, or others b2: Bias control bit 0: 1/3 bias 1: 1/2 bias Continued from Figure 2.7.7 b6, b5: LCD circuit divider division ratio selection bits b6b5 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source ´ Setting display data into the RAM (Address 4016 to 5316) for LCD display By writing “1” to bits in the RAM for LCD display, the corresponding segments of the LCD panel becomes ready for lighting

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2.7.5 Application examples

(1) LCD panel display pattern example Figure 2.7.9 shows an 8-segment LCD panel display pattern example when the duty ratio number is Fig. 2.7.9 8-segment LCD panel display pattern example when duty ratio number is 4 Display RAM map low-order /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines COM 1 A B CE F G H COM 3 COM 2 COM 0 A B C D E F G H SEG b SEG a Display RAM map high-order (Address) SEG 4B16 SEG SEG 4A16 SEG SEG 4916 SEG SEG 4816 SEG 4716 SEG SEG 4616 SEG SEG SEG 4516 SEG SEG 4416 SEG SEG 4316 SEG SEG 4216 SEG SEG 4116 SEG SEG 4016 SEG LCD display RAM SEG 5316 SEG SEG 4E16 SEG SEG 4D 16 SEG SEG 4C 16 SEG /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines COM 3 COM 0 COM 2 COM 1 D SEG SEG 5116 SEG SEG 5016 SEG SEG 4F16 SEG SEG 5216

2–1693820 GROUP USER’S MANUAL (2) LCD panel example Figure 2.7.10 to Figure 2.7.12 show an LCD panel example and a segment allocation example for it, and an LCD display RAM setting example. Fig. 2.7.10 LCD panel example Fig. 2.7.11 Segment allocation example Fig. 2.7.12 LCD display RAM setting example AUTO SLOW PRINT AUTO SLOW 1 2 345 6 7PRINT a b c d e f gBit Address 765 432 10 004016 004116 004216 004316 004416 004516 004616 gfe d cb a COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 SLOW AUTO PRINT gfe d cb a gfe d cb a gfe d cb a gfe d cb a gfe d cb a

2–170 3820 GROUP USER’S MANUAL (3) Control procedure Figure 2.7.13 shows the setting of related registers to turn on all the LCD display in Figure 2.7.10, and Figure 2.7.14 shows the control procedure. Specifications: •Frame frequency = 122 Hz

• Duty ratio number = 4, Bias value = 1/3
• Segment output; SEG0 to SEG13 are used.
• Ports P0 and P1 are set as I/O ports, port P3 is set as input port. Fig. 2.7.13 Setting of related registers SEG: Segment output enable register [Address 3816] b7 b0 b2: Segment output enable bit 2 0: I/O ports P02–P07 LM: LCD mode register [Address 3916] b7 b0 b1, b0: Duty ratio selection bits b1b0 11: 4 (use COM0–COM 3) 011 000 0 0 0 b0: Segment output enable bit 0 0: Input ports P3 0–P37 b1: Segment output enable bit 1 0: I/O ports P0 0, P01 10 001 b3: Segment output enable bit 3 0: I/O ports P1 0, P11 b4: Segment output enable bit 4 0: I/O port P1 b5: Segment output enable bit 5 0: I/O ports P1 3–P17 b7, b6: Fix these bits to “0” b2: Bias control bit 0: 1/3 bias b3: LCD enable bit 0: LCD OFF (after setting data into the RAM for LCD display, turn on) b4: Fix this bit to “0” b6, b5: LCD circuit divider division ratio selection bits b6b5 01: 2 division of LCDCK count source ] b7: LCDCK count source selection bit 1: f(XIN)/8192 ]
• Frame frequency = f(LCDCK)/duty ratio number From the above, the frame frequency at f(XIN) = 8 MHz is as follows: Frame frequency f = 8 5 10 8192 5 ≈ 122.070 Hz ]: •f(LCDCK) = Count source frequency for LCDCK/LCD circuit division ratio

2–1713820 GROUP USER’S MANUAL Fig. 2.7.14 Control procedure All interrupts; Disabled Set ports/segments Set LCD mode register Set port P0 I/O direction Set port P1 I/O direction Set pull-up, pull-down ]Set in the order of ports P0/P1 direction registers and PULL register A Set values in LCDRAMX (Set it to “1” to turn on or to “0” to turn it off) RESET SEG (Address 3816) LM (Address 3916) P0D (Address 0116) P1D (Address 0316) PULLA (Address 1616) Initialization When switching LCD ON (OFF) segments CLT CLD SEI LCDRAM0 (Address 40 16) LCDRAM1 (Address 4116) LCDRAM2 (Address 4216) LCDRAM3 (Address 4316) LCDRAM4 (Address 4416) LCDRAM5 (Address 4516) LCDRAM6 (Address 4616) LM (Address 3916), bit 3 CLI LCDRAMX (Address XX 16) ← 000000012 ← 101000112 ← XXXXXXXX 2 ← XXXXXXXX 2 ← XXXXXXXX 2 ← 111111112 ← 111111112 ← 111111112 ← 111111112 ← 011111112 ← 011111112 ← 111111112 ← 1 ← XXXXXXXX 2 Turn on LCD Interrupts; Enabled Rewrite bits corresponding to LCD ON (OFF) segments

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2.7.6 Notes on use

(1) For transition from the high-speed or the middle-speed mode to the low-power operation of the low- speed mode: À Select oscillation at 32 kHz (CM4 = 1) \ Count source for LCDCK; select f(XCIN )/32 (LM7 = 0) ´ Internal system clock; select XCIN –X COUT (CM 7 = 1) ˆ Stop main clock XIN–X OUT (CM 5 = 1) In the above order, execute transition. Execute the setting \ after the oscillation at 32 kHz (setting À ) becomes completely stable. (2) If the STP instruction is executed while the LCD is turned on by setting bit 3 of the LCD mode register to “1,” a DC voltage is applied to the LCD. For this reason, do not execute the STP instruction while the LCD is lighting. (3) When the LCD is not used, open the segment and the common pins. Connect VL1–V L3 to VSS .

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2.8.1 Explanation of operations

The watchdog timer is a down-count timer consisting of 14 bits (6 high-order bits and 8 low-order bits). Each time a count source is input, a count value is decremented by 1. The watchdog timer is also available as a 6-bit timer. (1) Basic operations À By executing a write instruction to the watchdog timer control register (address 0037 16), “3F16” and “FF16” are automatically set in the watchdog timer H and watchdog timer L respectively, with the result that a count operation starts. A count source can be selected by the watchdog timer H count source selection bit (bit 7 at address 0037 16) (Refer to “(2) and (3)” on the next page). \` When a specified count value is counted and the watchdog timer H underflows, an internal reset signal is generated, so that a microcomputer is put into the reset status. Table 2.8.1 shows the program runaway detection time ] 1 (maximum) and Figure 2.8.1 shows an internal reset signal output timing diagram. ´ The program starts from the contents of the vector address at reset. 32.768 msf(XIN) = 8 MHz 8.19 sf(XCIN ) = 32 kHz When the watchdog timer H count source selec- tion bit is “0.” Detection time (maximum) Table 2.8.1 Program runaway detection time (maximum)]1: The time from start of count operation until output of internal reset signal. When using the watchdog timer, set by software so that data is written into the watchdog timer control register before the watchdog timer H underflows (within the program runaway detection time shown in Table 2.8.1). If a write instruction has not been executed to the watchdog timer control register because of a program runaway, internal reset occurs, so that the program restores to a normal routine. Fig. 2.8.1 Internal reset signal output timing XIN input signal Approximately 1 ms at f(XIN) = 8 MHz XCIN input signal Internal reset signal Detection of program runaway (Underflow of watchdog timer H)

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(2) Operations when the 14-bit timer is used (bit 7 of watchdog timer control register = “0”) À By executing a write instruction to the watchdog timer control register, a count operation is started. \ The underflow of the watchdog timer L becomes a count source of the watchdog timer H. When the watchdog timer H underflows, a microcomputer is put into reset status. ´ The program starts from the contents of the vector address at reset. (3) Operations when the 6-bit timer is used (bit 7 of watchdog timer control register = “1”) À By executing a write instruction to the watchdog timer control register, a count operation is started. \ f(XIN)/16 or f(XCIN )/16 becomes a count source of the watchdog timer H. When watchdog timer H underflows, a microcomputer is put into the reset status. ´ The program starts from the contents of the vector address at reset. (4) Operations in the stop mode or the wait mode n When the stop mode is provided by executing the STP instruction, the watchdog timer stops its count operation. When the stop mode is released by an interrupt request, the oscillation of a count source is restarted and the watchdog timer restarts its count operation at the same time. Because the count operation is continued even in the wait time for stop release (about 8000 cycles of f(X IN) or f(XCIN )), be careful not to cause watchdog timer H to underflow. n When the wait mode is provided by executing the WIT instruction, the CPU operation stops but the watchdog timer continues to count down.

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2.8.2 Related register

The related register is only the watchdog timer control register (address 003716). The operation of the watchdog timer is started by executing a write instruction to the watchdog timer control register after reset. The watchdog timer being operated is made ineffective by reset. When the watchdog timer is not used, do not execute a write instruction to the watchdog timer control register after reset. Figure 2.8.2 shows the structure of the watchdog timer control register. Fig. 2.8.2 Structure of watchdog timer control register b7b6 b5b4b3 b2b1b0 Watchdog timer control register (WDTCON) [Address 3716] B At reset R W Watchdog timer control register to Name Functions Watchdog timer H bits At reading, the count value of watchdog timer H is read. ×6 Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading.

7 Watchdog timer H

0: Underflow from watchdog timer L (WDT is used as 14-bit timer) 1: f(X IN)/16 or f(XCIN)/16 (WDT is used as 6-bit timer) (Note) Note: When a value is written to address 3716, the following values are set, so that the watchdog timer starts a count operation. Watchdog timer H = “3F16” Watchdog timer L = “FF16”

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The 3820 group is provided with a standby function to stop the CPU by software and put the CPU into the low-power operation. The following two types of standby function are available.

• Stop mode by the STP instruction
• Wait mode by the WIT instruction Table 2.9.1 State in stop mode State in stop modeItem Oscillation CPU I/O ports P0–P7 Timer, serial I/O, LCD display functions, watchdog timer Stop Stop The state where STP in- struction is executed is held

2.9.1 Stop mode

The stop mode is set by executing the STP instruc- tion. In the stop mode, the oscillation of both XIN and XCIN stops and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating. As a result, power dissipation is reduced. (1) State in the stop mode The stop mode is set by executing the STP instruction. ] 1 In the stop mode, the oscillation of both XIN and XCIN stops, so that all the functions stop, providing a low-power operation. Table 2.9.1 shows the state in the stop mode. ] 1: After setting the LCD enable bit (bit 3) of the LCD mode register to “0,” execute the STP instruction. Internal clock φ Stop at “H” level Stop

2–1773820 GROUP USER’S MANUAL (2) Release of stop mode The stop mode is released by reset input or by the occurrence of an interrupt request. There is a difference in restore processing from the stop mode by reset input and by an interrupt request. n Restoration by reset input By holding the “L” input level of the RESET pin in the stop mode for 2 µs or more, the reset state is set, so that the stop mode is released. At the time when the stop mode is released, oscillation is started. At this time, the inside of the microcomputer is in the reset state. After the input level of the RESET pin is returned to the “H,” the reset state is released in approximately 8,000 cycles of the XIN input. The oscillation is unstable at start of oscillation. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. The time to hold the internal reset state is reserved as the oscillation stabilizing time. Figure 2.9.1 shows the oscillation stabilizing time at restoration by reset input. At release of the stop mode, the contents of the internal RAM previous to the reset are held. However, the contents of the CPU register and SFR are not held. For resetting, refer to “2.10 Reset.” Fig. 2.9.1 Oscillation stabilizing time at restoration by reset input RESET XIN VCC Execute STP instructionRestored by reset input Oscillation stabilizing time Stop mode 2 µ s or more Note: No waveform may be input to XIN (in low-speed mode) Time to hold internal reset state = approximately 8000 cycles of XIN input (Note)

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n Restoration by an interrupt request The occurrence of an interrupt request in the stop mode releases the stop mode. As a result, oscil- lation is resumed. The interrupt requests available for restoration are:

• INT 0–INT3
• Serial I/O1 transmit/receive and serial I/O2 using an external clock
• Timer X/Y using an external clock
• Key input (key-on wake up) However, to use the above interrupt requests for restoration from the stop mode, after setting the following, execute the STP instruction in order to enable the interrupt request to be used. [Necessary register setting] À Interrupt disable flag I = “0” (interrupts enabled) \` Both timers 1 and 2 interrupt enable bits = “0” (interrupts disabled) ´ Interrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request issued) ˆ Interrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) For interrupts, refer to “2.2 Interrupts.” The oscillation is unstable at start of oscillation. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. At restoration by an interrupt request, the time to wait for supplying the internal clock φ to the CPU is automatically generated] 1 by timers 1] 2 and 2.] 2 This wait time is reserved as the oscillation stabilizing time on the system clock side. Figure 2.9.2 shows an execution sequence example at restoration by the occurrence of an INT interrupt request. ] 1: At restoration from the stop mode, all bits except bit 4 of the timer 123 mode register (address 0029 16) are set to “0.” As a count source of the timer 1, an f(XIN)/16 or f(XCIN )/16 clock is selected. As a count source of the timer 2, the timer 1 underflow is selected. Immediately after the oscillation is started, the count source is supplied to the timer 1 counter, so that a count operation is started. The supplying the internal clock φ to the CPU is started at the timer 2 underflow. ] 2: When the STP instruction is executed, “FF16” and “0116” are automatically set in the timer 1 counter/latch and timer 2 counter/latch respectively.

2–1793820 GROUP USER’S MANUAL Fig. 2.9.2 Execution sequence example at restoration by occurrence of INT0 interrupt request Timer 2 counter l When restoring from stop mode by using INT0 interrupt (rising edge selected) XIN or XCIN (System clock) “FF16” INT0 pin Peripheral device CPU Stop mode Timer 1 counter “0116” 512 counts

• INT0 interrupt signal input (INT0 interrupt request occurs)
• Oscillation start
• Timer 1 count start
• Execute STP instruction Stopping Operating Stopping Operating Note: As a count source, f(XIN)/16 or f(XCIN)/16 is input. Either f(XIN)/16 or f(XCIN)/16 is selected by bit 7 of CPU mode register. Oscillation stabilizing time (approximately 8000 cycles) XIN; “H” XCIN; in high-impedance state Oper- ating INT0 interrupt request bit
• 512 counts down by timer 1
• Start supplying internal clock φ to CPU
• Accept INT 0 interrupt request Oper- ating

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(3) Notes on using the stop mode n Release sources The release sources of the stop mode are shown below.

• Reset input
• INT0–INT3 interrupts
• Serial I/O1 transmit/receive and serial I/O2 interrupts using an external clock
• Timers X/Y interrupts using an external clock
• Key input interrupt (key-on wake up) Each INT pin (INT0, INT1, INT2, INT3) is also used as ports P42, P43, P57 or P60 and each key input pin is also used as port P2. To use INT0 to INT3 interrupts, after setting the corresponding bits of the following direction registers to “0” to set them for the input mode, execute the STP instruction.
• Port P2 direction register (address 000516)
• Port P4 direction register (address 000916)
• Port P5 direction register (address 000B16)
• Port P6 direction register (address 000D16) n Register setting To use the above interrupt requests for restoration from the stop mode, after setting the following, execute the STP instruction in order to enable the interrupt request to be used. [Necessary register setting] À Interrupt disable flag I = “0” (interrupts enabled) \` Both timers 1 and 2 interrupt enable bits = “0” (interrupts disabled) ´ Interrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request issued) ˆ Interrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled)
• At restoration from the stop mode, the values of the timers 1, 2 and 123 mode registers are auto- matically rewritten. Accordingly, set each of them again.
• To prevent a DC voltage from being applied to the LCD, after setting the LCD enable bit (bit 3) of the LCD mode register to “0,” execute the STP instruction.
• Write to the watchdog timer control register (address 003716) before the STP instruction execution. If the STP instruction is executed without writing, an internal reset may occures. n Clock after restoration After restoration from the stop mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are held. Accordingly, when both XIN and XCIN were oscil- lating before execution of the STP instruction, the oscillation of both XIN and XCIN is resumed at restoration from the stop mode by an interrupt request. In the above case, when the X IN side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode. At this time, note that the oscillation on the XCIN side may not be stabilized even after the lapse of the oscillation stabilizing time (of the XIN side).

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2.9.2 Wait mode

The wait mode is set by execution of the WIT instruction. In the wait mode, the oscillation is continued, but the internal clock φ stops at the “H” level. Since the oscillation is continued regardless of the CPU stop, the peripheral units operate. (1) States in the wait mode By executing the WIT instruction, the wait mode is set. In the wait mode, the internal clock φ which is supplied to the CPU stops at the “H” level. The continuation of oscillation permits clock supply to the peripheral units. Table 2.9.2 shows the state in the wait mode. State in wait modeItem CPU Internal clock φ I/O ports P0–P7 Timer, serial I/O, LCD display functions, watchdog timer Operating Stop Stop at “H” level The state where WIT in- struction is executed is held. Operating Table 2.9.2 State in wait mode Oscillation

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(2) Release of wait mode The wait mode is released by reset input or by the occurrence of an interrupt request. There is a difference in restore processing from the wait mode by use of reset input and by use of an interrupt request. In the wait mode, oscillation is continued, so an instruction can be executed immediately after the wait mode is released. n Restoration by reset input The reset state is provided by holding the input level of the RESET pin at “L” for 2 µs or more in the wait mode. As a result, the wait mode is released. At the time when the wait mode is released, the supplying the internal clock φ to the CPU is started. The reset state is released in approximately 8,000 cycles of the XIN input after the input of the RESET pin is returned to the “H” level. At release of the wait mode, the contents of the internal RAM previous to the reset are held. However, the contents of the CPU mode register and SFR are not held. Figure 2.9.3 shows the reset input time. For reset, refer to “2.10 Reset.” Fig. 2.9.3 Reset input time RESET XIN VCC Execute WIT instruction Restored by reset input Wait mode 2 µs or more Oscillation stabilizing time Note: No waveform may be input to XIN (in low-speed mode) (Note) Time to hole internal reset state = approximately 8000 cycles of XIN input

2–1833820 GROUP USER’S MANUAL n Restoration by an interrupt request In the wait mode, the occurrence of an interrupt request releases the wait mode and the supplying the internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration is accepted, so the interrupt processing routine is executed. However, to use an interrupt for restoration from the wait mode, after setting the following, execute the WIT instruction in order to enable the interrupt to be used. [Necessary register setting] À Interrupt disable flag I = “0” (interrupts enabled) \` Interrupt request bit of the interrupt source to be used for restoration = “0” (no interrupt request issued) ´ Interrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) For interrupts, refer to “2.2 Interrupts.” (3) Notes on the wait mode n Restoration by INT0 to INT3 interrupt requests Each INT pin (INT0, INT1, INT2, INT3) is also used as ports P42, P43, P57 or P60 and each key input pin is also used as port P2. To use INT0 to INT3 interrupts, set the corresponding bits of the following direction registers to “0” for setting the input mode. And then, execute the WIT instruction.

• Port P2 direction register (address 000516)
• Port P4 direction register (address 000916)
• Port P5 direction register (address 000B16)
• Port P6 direction register (address 000D16) n Restoration by key input interrupt request The pins for a key input interrupt is also used as port P2. To use a key input interrupt, set the corresponding bits of the port P2 direction register (address 000516) to “0” for setting the input mode. And then, execute the WIT instruction. n Register setting To use the above interrupt requests for restoration from the stop mode, after setting the following, execute the WIT instruction in order to enable the interrupt request to be used. [Necessary register setting] À Interrupt disable flag I = “0” (interrupts enabled) \` Interrupt request bit of the interrupt source to be used for restoration = “0” (no interrupts request issued) ´ Interrupt enable bit of the interrupt source to be used for restoration = “1” (interrupts enabled) n Operation of the watchdog timer The watchdog timer continues to count down in the wait mode. The CPU stops in the wait mode, however, the watchdog timer cannot be written by software. As a result, an internal reset occurs at an underflow of the watchdog timer, the wait mode is released automatically.

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2.9.3 State transitions of internal clock φ

Figure 2.9.4 shows the state transitions of the internal clock φ when the standby function is used. Fig. 2.9.4 State transitions of internal clock φ RESET CM 6 CM “1” ↔ “0” CM “1” ↔ “0” CM “0” ↔ “1”CM “1” ↔ “0” CM “1” ↔ “0” CM “1” ↔ “0” CM “0” ↔ “1”CM “1” ↔ “0” CPU mode register (CPUM) [Address 3B16] CM 4: Port Xc switch bit 0: I/O port 1: X CIN, XCOUT CM 5: Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) Middle-speed mode (f (φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) High-speed mode (f (φ) = 4 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) CM “1” “0” CM “1” “0” Middle-speed mode (f (φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) High-speed mode (f (φ) = 4 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM6 CM “1” “0” Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM 6 CM “1” “0” Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM “1” “0” CM “1” “0” CM 6 Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) b4b7 Notes 1: Switch the mode by the allows shown between the mode blocks.( Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is released. 3: Timer and LCD operate in the wait mode. 4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2. 6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to the middle-/high-speed mode. 7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

2–1853820 GROUP USER’S MANUAL Fig. 2.10.1 Internal reset state hold/release timing The internal reset state is provided by applying a “L” level to the RESET pin. After that, the reset state is released by applying a “H” level to the RESET pin, so that the program is executed in the middle-speed mode starting from the contents at the reset vector address.

2.10.1 Explanation of operations

Figure 2.10.1 shows the internal reset state hold/release timing. Internal clock φ Internal processing sequence Hold reset state2 µs or more RESET Middle-speed = approximately 8000 cycles of XIN input

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Table 2.10.1 Timers 1 and 2 at resetThe reset state is provided by applying a “L” level to the RESET pin at power source voltage of 2.5 V to 5.5 V. Allow 2 µs or more as “L” level applying time. By applying a “H” level to the RESET pin in the internal reset state, the timers and their count source shown in Table 2.10.1 is automatically set. After that, the internal reset state is released by the timer 2 underflow. After applying “H” level, only the main clock oscil- lates in the middle-speed mode regardless of the oscillation state previous to internal resetting. The X CIN pin on the sub-clock side becomes the input port. After the internal reset state is released, the pro- gram is run from the address determined with the contents (high-order address) at address FFFD16 and the contents (low-order address) at address FFFC 16. Figure 2.10.2 shows the internal processing sequence immediately after reset release. Value 0116 Count source Timer 2Timer 1Item f (XIN)/16 Timer 1 underflow FF 16 Fig. 2.10.2 Internal processing sequence immediately after reset release Internal clock φ FFFC 16 AHAL AL,AH f(XIN) 2 µs or more RESET Internal reset Address bus Data bus SYNC VCC Internal clock φ AH , AL SYNC 1 µs at f(XIN) = 8 MHz Approximately 8000 cycles of XIN input FFFD 16 : CPU reference clock frequency = f(XIN)/8 (middle-speed mode immediately after reset) : Interrupt jump destination addresses : CPU operation code fetch cycle (This is a internal signal, so that it cannot be observed from the external unit) : Undefined

2–1873820 GROUP USER’S MANUAL Fig. 2.10.3 Internal state of microcomputer immediately after reset release

2.10.2 Internal state of the microcomputer immediately after reset release

Figure 2.9.3 shows the internal state of the microcomputer immediately after reset release. The contents of all other registers except registers in Figure 2.10.3 and internal RAM are undefined at poweron reset. Port P0 direction register Port P1 direction register Port P2 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register PULL register A PULL register B Serial I/O1 status register Serial I/O1 control register UART control register Serial I/O2 control register Timer X (low-order) Timer X (high-order) Timer Y (low-order) Timer Y (high-order) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register φ output control register Watchdog timer control register Segment output enable register LCD mode register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter 0001 000316 000516 000916 000B16 000D 16 000F16 001616 001716 001916 001A16 001B16 001D 16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) Contents of registerAddress 0016 0016 0016 0016 0016 0016 0016 b7 b1 010 11 10 0000 00 11 1000 00 01 1111 11 0016 0016 0016 0016 01 0010 00 XXXXX1XX Contents of address FFFD16 Contents of address FFFC16 Notes X : Undefined The contents of all other registers and internal RAM are undefined at poweron reset, so they must be initialized by software. 0016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0016 0016 0016 0 0 0 0016 0016

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2.10.3 Reset circuit

Design a configuration of the reset circuit so that the reset input voltage may be 0.5 V or less at the time when the power sorce voltage passes 2.5 V. Fig. 2.10.4 Poweron reset conditions Fig. 2.10.5 Poweron reset circuit examples 0 V 0 V VCC RESET Power on 2.5 V 0.5 V VCCRESET 3820 group 27 73 VCCRESET 3820 group 27 73 Power source voltage detection circuit

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2.10.4 Notes on the RESET pin

In case where the reset signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following: l Make the length of the wiring which is connected to a capacitor as short as possible. l Be sure to check the operation of application products on the user side. REASON If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure.

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2.11.1 Oscillation circuit

Two oscillation circuits are included to obtain clocks required for operations. A clock] 1 obtained by dividing the frequency input to the clock input pins XIN or XCIN is an internal clock φ. The internal clock φ is used as a standard for operations. ] 1: The internal clock φ varies with modes. (1) Oscillation circuit using ceramic resonators Figure 2.11.1 shows an oscillation circuit example using ceramic resonators. As shown in the figure, an oscillation circuit can be formed by connecting a ceramic resonator or a quartz-crystal oscillator between the pins X IN and the XOUT and between the pins XCIN and XCOUT . As the XIN–X OUT oscil- lation circuit includes a feedback resistor, an external resistor is omissible. As the X CIN –X COUT oscillation circuit does not include any feedback resistor, connect a feedback resistor externally. Regarding circuit constants for Rf, Rd, CIN, COUT , CCIN and CCOUT , ask the resonator manufacturer for information, and set the values recommended by the resonator manufacturer. Fig. 2.11.1 Oscillation circuit example using ceramic resonators R f C CIN C COUT 3820 group XCIN XCOUT C IN C OUT XIN XOUT R d 28 29 30 31

2–1913820 GROUP USER’S MANUAL (2) External clock input circuit An external clock can also be supplied to the main clock oscillation circuit. Figure 2.11.2 shows an external clock input circuit example. As an external clock to be input to the X IN pin, use a pulse signal with a duty ratio of 50%. At this time, open the XOUT pin. Any clock externally generated cannot be input to the XCIN pin directly. Cause oscillation with an external ceramic resonator. Fig. 2.11.2 External clock input circuit example XIN XOUT External oscillation circuit Open VCC VSS C CIN C COUT R f XCIN XCOUT 3820 group R d 28 29 30 31

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2.11.2 Internal clock φ

The internal clock φ is the standard for operations. (1) Clock generating circuit The clock generating circuit controls the oscillation of the oscillation circuit. The generated clock (internal clock φ) is supplied to the CPU and peripheral units. Figure 2.11.3 shows the clock generating circuit block diagram. Oscillation can be stopped and re- sumed by the clock generating circuit. Fig. 2.11.3 Clock generating circuit block diagram WIT instruction STP instruction Timing φ (Internal clock) S R QS R Q Main clock stop bit S R Q Timer 2Timer 11/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Interrupt disable flag (I) Reset Port Xc switch bit“1” “0” “1” “0” Timer 1 count source selection bit “0” “1” Timer 2 count source selection bit Low-speed mode Middle-/high-speed mode Middle-speed mode High-/low-speed mode Note: When using the low-speed mode, set the port Xc switch bit to “1.” Internal system clock selection bit (Note) Main clock division ratio selection bit “1” “0” “0” “1” STP instruction

2–1933820 GROUP USER’S MANUAL (2) Clock output function The internal clock φ can be output from the φ pin by setting the φ output control bit (bit 0) of the φ output control register (address 002A16) to “1.” The φ pin is also used as port P41. Accordingly, to use it as an φ pin, set bit 1 of the port P4 direction register to “1.” Figure 2.11.4 shows the structure of the φ output control register. Fig. 2.11.4 Structure of φ output control register b7b6 b5b4b3 b2b1b0 φ output control register (CKOUT) [Address 2A16] B Name Functions At reset R W φoutput control register to φ output control bit0: Port function 1: φ clock output (Port direction register = “1”) 0 0 Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading.

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2.11.3 Oscillating operation

The start and stop sources for oscillating operation are described below. (1) Oscillating operation At reset release, the middle-speed mode is provided. At this time, only the main clock oscillates and the XCIN and XCOUT pins function as I/O ports. To use the sub-clock, set the P70, P71 pull-up (bit 4) of the PULL register A (address 001616) to “0” and disconnect each pull-up resistor of the XCIN and XCOUT pins. n Middle-speed mode The internal clock φ after reset release is obtained by dividing f(XIN) by 8 (f(XIN) is the frequency which is input to the XIN pin). When changing to the high-speed mode: Set the main clock division ratio selection bit (bit 6) of the CPU mode register (address 003B16) to “0.” When changing to the low-speed mode: Change the mode according to the following procedure. À Set the port Xc switch bit (bit 4) of the CPU mode register to “1.” \ Generate the oscillation stabilizing time of XCIN input by software. ´ Set the internal system clock selection bit (bit 7) of the CPU mode register to “1.” n High-speed mode The clock obtained by dividing f(XIN) by 2 is an internal clock φ. When changing to the middle-speed mode: Set the main clock division ratio selection bit (bit 6) of the CPU mode register to “1.” When changing to the low-speed mode: Change the mode according to the following procedure. À Set the port Xc switch bit (bit 4) of the CPU mode register to “1.” \ Generate the oscillation stabilizing time of XCIN input by software. ´ Set the internal system clock selection bit (bit 7) of the CPU mode register to “1.”

2–1953820 GROUP USER’S MANUAL n Low-speed mode The clock obtained by dividing the frequency f(XCIN ) input to the XCIN pin by 2 is an internal clock φ. In the low-speed mode, the oscillation of the main clock is stopped by setting the main clock (XIN– X OUT ) stop bit to “1,” so that the low-power operation can be attained. When changing to the middle- or high-speed modes: Change the mode according to the following procedure. À Set the main clock (XIN–X OUT ) stop bit (bit 5) of the CPU mode register to “0.” \` Generate the oscillation stabilizing time of XIN input by software. ´ Set the internal system clock selection bit (bit 7) of the CPU mode register to “0.” ˆ Specify the main clock division ratio selection bit (bit 6) of the CPU mode register. Notes 1: Make a mode change from the middle- or high-speed modes to the low-speed mode after the oscillation of both the main clock and the sub-clock is stabilized (for oscillation stabiliz- ing time, ask the resonator manufacturer for information). 2: For the sub-clock, the stabilizing of oscillation requires much time. When making a change from the middle-speed or high-speed modes to the stop mode and then making a return from the stop mode while the sub-clock oscillates, the oscillation of the sub-clock is not yet stabilized even when the main clock has become stable and the CPU has been restored. 3: For a mode change, set to f(X IN) > f(XCIN ) 5 3. (2) Oscillating operation in the stop mode After the stop mode is provided by executing the STP instruction, every oscillation stops and the internal clock φ stops at the “H” level. At the time when restoration is made from the stop mode by rest input or by the occurrence of an interrupt request for restoration, oscillation starts. For the details of the stop mode, refer to “2.9.1 Stop mode.” (3) Oscillating operation in the wait mode After the wait mode is provided by executing the WIT instruction, the internal clock φ supplied to the CPU stops at the “H” level. As oscillation is continued, the supply of internal clock φ to the peripheral units is continued. At the time when restoration is made from the wait mode by reset input or by the occurrence of an interrupt request for restoration, the supply of internal clock φ to the CPU starts. For the details of the wait mode, refer to “2.9.2 Wait mode.”

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(4) State transitions of internal clock φ Figure 2.11.5 shows the state transitions of the internal clock φ. Fig. 2.11.5 State transitions of internal clock φ RESET CM 6 CM “1” ↔ “0” CM “1” ↔ “0” CM “0” ↔ “1”CM “1” ↔ “0” CM “1” ↔ “0” CM “1” ↔ “0” CM “0” ↔ “1”CM “1” ↔ “0” CPU mode register (CPUM) [Address 3B16] CM 4: Port Xc switch bit 0: I/O port 1: X CIN, XCOUT CM 5: Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) Middle-speed mode (f (φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) High-speed mode (f (φ) = 4 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) CM “1” “0” CM “1” “0” Middle-speed mode (f (φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) High-speed mode (f (φ) = 4 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM6 CM “1” “0” Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM 6 CM “1” “0” Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) CM “1” “0” CM “1” “0” CM 6 Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f (φ) = 16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) b4b7 Notes 1: Switch the mode by the allows shown between the mode blocks.( Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is released. 3: Timer and LCD operate in the wait mode. 4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2. 6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to the middle-/high-speed mode. 7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

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2.11.4 Oscillation stabilizing time

In the oscillating circuit using ceramic resonators, the oscillation is unstable for a certain time when the oscillation of the resonators starts. The time required for stabilizing of oscillation is called oscillation stabilizing time. An appropriate oscillation stabilizing time is required in accordance with the conditions of the oscillation circuit in use. For oscillation stabilizing time, ask the resonator manufacturer for information. (1) Oscillation stabilizing time at poweron In the oscillating circuit using ceramic resonators, oscillation is unstable for a certain time immediately after poweron. At reset release, the oscillation stabilizing time for approximately 8,000 cycles of XIN input is automatically generated. Figure 2.11.6 shows the oscillation stabilizing time at poweron. Fig. 2.11.6 Oscillation stabilizing time at poweron RESET XIN Oscillation stabilizing time VCC 2 µs or more 2.5 V Internal reset l Middle-/high-speed mode Release internal reset state

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(2) Oscillation stabilizing time at restoration from the stop mode In the stop mode, oscillation stops. When restoration is made from the stop mode by reset input or an interrupt request, the oscillation stabilizing time for approximately 8,000 cycles of XIN input or XCIN input is automatically generated as at poweron. At restoration made by reset, XIN input is a clock source of oscillation stabilizing time. At restoration made by an interrupt request, either XIN input or XCIN input set as a system clock immediately before execution of the STP instruction becomes a count source of oscillation stabilizing time. When X IN input is a system clock, the oscillation stabilizing time at restoration becomes approximately 8,000 cycles of XIN input. However, note that the oscillation on the XCIN side may not be stable even after the lapse of this oscillation stabilizing time. For the details of the stop mode, refer to “2.9.1 Stop mode.” (3) Oscillation stabilizing time at reoscillation of X IN When starting the oscillation of XIN which was stopped by setting the main clock (XIN–X OUT ) stop bit of the CPU mode register to “1,” set this bit to “0.” At this time, generate oscillation stabilizing time by software. Figure 2.11.7 shows the oscillation stabilizing time at reoscillation of XIN. Fig. 2.11.7 Oscillation stabilizing time at reoscillation of XIN XIN VCC Oscillation stabilizing time (Note) Note: For oscillation stabilizing time, ask the resonator manufacturer for information. Main clock (XIN–XOUT ) stop bit

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 CHAPTER 3 APPENDIX Built-in PROM version Countermeasures against noise Control registers List of instruction codes Machine instructions Mask ROM ordering method Mark specification form Package outlines SFR allocation Pin configuration

3820 GROUP USER’S MANUAL3–2

In contrast with the mask ROM version, the microcomputer with a built-in programmable ROM is called the built-in programmable ROM version (referred as “the built-in PROM version”). The following two types of built-in PROM version are available. rewritten. deleted and rewritten. The EPROM version has the function of the One Time PROM version and also permits deleting and rewriting the contents of the PROM.

3820 GROUP USER’S MANUAL 3–3

3.1.1 Product expansion

Table 3.1.1 shows the product expansion of the built-in PROM version. Table 3.1.1 Product expansion of built-in PROM version Note: The number in parentheses denotes a user ROM capacity. M38203E4-XXXFP M38203E4FP M38203E4-XXXGP M38203E4GP M38203E4-XXXHP M38203E4HP PROMProduct RAM RemarksPackage 80P6N-A ] 1 PCA4738F-80A Shipped after programming and inspection at plant Shipped in blank] 5 Shipped after programming and inspection at plant Shipped in blank] 5 Shipped after programming and inspection at plant Shipped in blank] 5 EPROM versionM38203E4FS Programming adapter M38207E8-XXXFP M38207E8FP M38207E8-XXXGP M38207E8GP M38207E8-XXXHP M38207E8HP PCA4738F-80A PCA4738G-80 Shipped after programming and inspection at plant Shipped in blank] 5 Shipped after programming and inspection at plant Shipped in blank] 5 Shipped after programming and inspection at plant Shipped in blank] 5 PCA4738L-80A EPROM versionM38207E8FS ] 1 80P6N-A ] 2 80P6S-A ] 3 80P6D-A ] 4 80D0 ] 5 Shipped in blank : 0.8 mm-pitch plastic molded QFP : 0.65 mm-pitch plastic molded QFP : 0.5 mm-pitch plastic molded QFP : 0.8 mm-pitch ceramic LCC : The product is shipped without writing any data in the built-in PROM PCA4738H-80 80P6S-A ] 2 80P6D-A ] 3 80D0 ] 4 80P6N-A ] 1 PCA4738L-80A80D0 ] 4 PCA4738H-8080P6D-A ] 3 PCA4738G-8080P6S-A ] 2 One Time PROM 32768 bytes (32638 bytes) One Time PROM 16384 bytes (16254 bytes)512 bytes 1024 bytes EPROM 16384 bytes (16254 bytes) EPROM 32768 bytes (32638 bytes)

3820 GROUP USER’S MANUAL3–4

0.5 µs (minimum instructions at 8MHz oscillation frequency) M38203E4 16384 bytes (user ROM capacity; 16254 bytes) M38207E8 32768 bytes (user ROM capacity; 32638 bytes) M38203E4 512 bytes M38207E8 1024 bytes

8 MHz (maximum)

32 kHz (standard) to 50 kHz (maximum) 16 sources, 16 vectors (includes key input interrupt) 8-bit 5 3 16-bit 5 2 8-bit 5 1 (operable in clock synchronous mode and UART mode) 8-bit 5 1 (operable only in clock synchronous mode) Select 1/2 or 1/3 Select duty ratio value of 2, 3, or 4 40 (maximum) 4 (maximum) 14-bit 5 1 1-bit output 2 built-in circuits (connect an external ceramic resonator or an external quartz-crystal oscillator) 2.5 V (minimum) to 5.0 V (standard) to 5.5 V (maximum) ] 4.0 V (minimum) in high-speed mode. However, at f(X IN) = (4 5 VCC – 8) MHz, 2.5 V to 4.0 V is possible. 32 mW (at 8 MHz oscillation frequency, VCC = 5 V) 0.045 mW (at 32 kHz oscillation frequency, VCC = 3 V) –20 °C to 85 °C CMOS silicon gate 80D0 (0.8 mm-pitch ceramic LCC) 80P6N-A (0.8 mm-pitch plastic mold QFP) 80P6S-A (0.65 mm-pitch plastic mold QFP) 80P6D-A (0.5 mm-pitch plastic mold QFP)

3.1.2 Performance overview

Table 3.1.2 shows a performance overview of the built-in PROM version. The performance of the built-in PROM version is the same as that of the mask ROM version with the exception that the PROM is built in. Bias Duty ratio Segment output Common output Parameter PROM RAM Main clock f(XIN) Sub-clock f(XCIN) Table 3.1.2 Performance overview of built-in PROM version Basic instructions Instruction execution time Memory sizes Programmable I/O ports Oscillation frequency Interrupts Timers Serial I/O1 Serial I/O2 LCD (Liquid Crystal Display) drive control functions Watchdog timer φ clock output function Clock generating circuit Power source voltage Power dissipation Operating temperature range Device structure Packages EPROM version One Time PROM version High-speed mode Low-speed mode Note: The parts enclosed by thick line denotes performance peculiar to the PROM version.

3820 GROUP USER’S MANUAL 3–5

3.1.3 Pin configuration

The pin configuration of the built-in PROM version is the same as that of the mask ROM version. Figure 3.1.1 shows the pin configuration of the EPROM version. Fig. 3.1.1 Pin configuration of EPROM version (top view) Package Type : 80D0 123456789 1 0 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 011 4160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4261626364 M38203E4FSM38207E8FS 21 22 23 24 JAPAN COM COM COM V V V 1/RTP 0/INT 3/RTP 7/INT 6/T OUT 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 7/S RDY1 3/S RDY2 COM SEG 3/INT 2/INT XIN P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT P70/XCOUT P71/XCIN RESET P4 0 P41/φ 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 1/SEG 0/SEG 6/SEG 7/SEG SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 VCC SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1

3820 GROUP USER’S MANUAL3–6

Fig. 3.1.2 Pin configuration of One Time PROM version (top view) (1) Package type : 80P6N-A 1234 5678 9 1 0 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 011 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/φ SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 VCC SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 4160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4261626364 M38203E4-XXXFP M38203E4FP M38207E8-XXXFP M38207E8FP 21 22 23 24 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 1/SEG 0/SEG 6/SEG 7/SEG COM COM COM V V V 1/RTP 0/INT 3/RTP 7/INT 6/T OUT 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 7/S RDY1 3/S RDY2 COM SEG 3/INT 2/INT

3820 GROUP USER’S MANUAL 3–7

Fig. 3.1.3 Pin configuration of One Time PROM version (top view) (2) Package type : 80P6S-A/80P6D-A 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG M38203E4-XXXGP M38203E4GP M38203E4-XXXHP M38203E4HP M38207E8-XXXGP M38207E8GP M38207E8-XXXHP M38207E8HP COM COM COM V V V 1/RTP 0/INT 3/RTP 7/INT 6/T OUT 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 7/S RDY1 3/S RDY2 4160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 123456789 1 0 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 011 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/φ P43/INT1 P42/INT0 P17/SEG 39 P16/SEG 38 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 VCC SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 P30/SEG 16 P31/SEG 17 COM 3 SEG 0

3820 GROUP USER’S MANUAL3–8

3.1.4 Functional block diagram

Figure 3.1.4 shows the functional block diagram of the built-in PROM version. Fig. 3.1.4 Functional block diagram of built-in PROM version Timer Y(16) Serial I/O2(8) Serial I/O1(8) 1 80 79 78 77 76 75 74 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM 5 4 3 2 VL1 VL2 VL3 8 7 6 LCDdrive control circuit RAM LCDdisplayRAM (20 bytes) PROM Timer X(16)Timer 1(8) P0(8) I/O port P0 P1(8) I/O port P1 P2(8) I/O port P2 Key–on wake up P3(8) Input port P3 P4(8) I/O port P4 P5(8) I/O port P5 A X Y S PC L PS PC H C P U P6(2) P7(2) Watchdog timer Clock generating circuitXCIN Sub–clock input XCOUT Sub–clock output φ Reset XCINXCOUT I/O portP6 I/O portP7 φ INT0, INT1 INT2 Date bus Main clock input XIN Main clock output XOUT Reset inputRESET (5V)VCC (0V)VSS Note : Pin numbers are for package type 80P6N–A. 72 71 70 69 68 67 66 65 Address bus Timer 2(8) Timer 3(8)

3820 GROUP USER’S MANUAL 3–9

3.1.5 Notes on use

Notes on using the built-in PROM version are described below. (1) All products of built-in PROM version n Notes on programming l When programming the contents of the PROM, use the dedicated programming adapter. This per- mits programming with a general-purpose PROM programmer. At that time, set all of SW1, SW2 and SW3 in the above programming adapter to “OFF.” l As a high voltage is used for programming, be careful not to apply overvoltage to pins. Special care must be exercised at poweron. n Notes on reading When reading out the contents of the PROM, use the dedicated programming adapter as in program- ming. This permits reading out with a general-purpose PROM programmer. At that time, set all of SW1, SW2 and SW3 in the programmer to “OFF.” n Notes on using port P4 When using port P40 as an input port in the One Time PROM/EPROM version, connect a resistors of several kΩ externally to port P40 in series. If this pin is not used, connect a resistor of several kΩ externally to VSS in series (for improvement of the value withstand noise operation failure). For details, refer to “3.2 Countermeasures against noise, 3.2.1 Shortest wiring length, (3) Wiring to the VPP pin of the One Time PROM version and the EPROM version.” (2) EPROM Version n Notes on deleting l Sunlight and fluorescent lamps include light which may delete programmed information. For use in the read mode, cover the transparent glass part of the delete window with a seal or others. l The seal to cover the transparent glass part is prepared by us. This seal is metallic (aluminium) for reasons of prevention of information-deleting light and tough- ness. Be careful not to bring this seal into contact with lead pins of the microcomputer. l Before deleting information, clean the transparent glass. Finger marks and seal paste may block ultraviolet rays and effect delete characteristics. n Notes on mounting l To mount the EPROM version for a purpose other than evaluation, use a suitable mounting socket. When mounting a ceramic package on the socket, fix it securely with silicone resin.

3820 GROUP USER’S MANUAL3–10

(3) One Time PROM version n Notes on setting the PROM programmer area l For products shipped in blank, access to the first 128 bytes and addresses FFFE16 and FFFF16 in the built-in PROM user area is inhibited. Note the above point when setting the PROM programmer area. n Notes before actual use The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not performed in the assembly process and the following processes. To ensure reliability after pro- gramming, performing programming and test according to the Figure 3.1.5 before actual use are recommended. Fig. 3.1.5 Programming and testing of One Time PROM version (shipped in blank) Programming with PROM programmer Screening (Caution) (Leave at 150 °C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours.

3.2 Countermeasures against noise

3820 GROUP USER’S MANUAL 3–11

Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.

3.2.1 Shortest wiring length

The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcom- puter. (1) Wiring for the reset input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring (within 20 mm). Reason The reset works to initialize the internal state of a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig. 3.2.1 Wiring for the RESET input pin (2) Wiring for clock input/output pins l Make the length of wiring which is connected to clock I/O pins as short as possible. l Make the length of wiring (within 20 mm) across the grouding lead of a capacitor which is con- nected to an oscillator and the VSS pin of a microcomputer as short as possible. l Separate the VSS pattern only for oscillation from other VSS patterns. Fig. 3.2.2 Wiring for clock I/O pins RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS Noise XIN XOUT VSS XIN XOUT VSS

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A microcomputer’s operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring to the VPP pin of the One Time PROM version and the EPROM version <When the VSS pin is also used as any other pin than the CNVSS ] 1 > l Make the length of wiring which is connected to the VPP pin as short as possible. l Connect an approximately 5 kΩ resistor to the V PP pin in serial (refer to Figure 3.2.3). ] 1 When a microcomputer does not have the CNV SS pin, the VPP pin is also as the input pin adjacent to the RESET input pin. Reason The V PP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writ- ing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.

3.2.2 Connection of a bypass capacitor across

the VSS line and the VCC line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: l Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. l Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. l Use lines with a larger diameter than other signal lines for VSS line and VCC line. Fig. 3.2.4 Bypass capacitor across the VSS line and the VCC line Fig. 3.2.3 Wiring for the VPP pin of the One Time PROM and the EPROM version VSSVCC Chip When the microcomputer does not have the CNVSS pin, the VPP pin is also used as the input pin adjacent to the RESET pin. 3820 P40/VPP Approximately 5 kΩ RESET

3820 GROUP USER’S MANUAL 3–13

3.2.3 Oscillator concerns

Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Installing an oscillator away from large cur- rent signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. 3.2.4 Installing an oscillator away from signal lines where potential levels change frequently Install an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Fig. 3.2.5 Wiring for a large current signal line Fig. 3.2.6 Wiring to a signal line where potential levels change frequently XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross

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3.2.5 Oscillator protection using VSS pattern

As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscilla- tor is mounted. Connect the V SS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, sepa- rate this V SS pattern from other VSS patterns.

3.2.6 Setup for I/O ports

Setup I/O ports using hardware and software as follows: <Hardware> l Connect a resistor of 100 Ω or more to an I/O port in series. <Software> l As for an input port, read data several times by a program for checking whether input levels are equal or not. l As for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. l Rewirte data to direction registers and pull-up con- trol registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. Fig. 3.2.7 VSS pattern on the underside of an oscillator Fig. 3.2.8 Setup for I/O ports XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the VSS line for oscillation from other VSS lines Direction register Data register Data bus I/O port pins Noise Noise

3820 GROUP USER’S MANUAL 3–15

3.2.7 Providing of watchdog timer function by

If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to nor- mal operation. This is equal to or more effective than program runaway detection by a hardware watch- dog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main rou- tine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. <The main routine> l Assigns a single byte of RAM to a software watch- dog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the fol- lowing condition: N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change be- cause of an interrupt processing or others, the initial value N should have a margin. l Watches the operation of the interrupt process- ing routine by comparing the SWDT contents with countsof interrupt processing after the initial value N has been set. l Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: ‹ If the SWDT contents do not change after inter- rupt processing \` If the changed SWDT contents are abnormal (In Figure 3.2.9, the main routine determines that the interrupt processing routine has failed only if the SWDT contents do not change). <The interrupt processing routine> l Decrements the SWDT contents by 1 at each interrupt processing. l Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed inter- rupt processing count). l Detects that the main routine has failed and de- termines to branch to the program initialization routine for recovery processing in the following case: ‹ If the SWDT contents are not initialized to the initial value N but continued to decrement and if they exceed the limit (and reach 0 or less) Fig. 3.2.9 Watchdog timer by software Main routine (SWDT) ← N CLI Main processing (SWDT) Interrupt processing routine errors N = N Interrupt processing routine (SWDT) ← (SWDT) – 1 Interrupt processing (SWDT) Main routine errors > 0 ≤0 RTI Return = N? ≤ 0?

3.3 Control registers

3820 GROUP USER’S MANUAL3–16

Fig. 3.3.1 Structure of port P0 and P1 direction registers Fig. 3.3.2 Structure of port Pi (i = 2, 4 to 7) direction registers b7b6 b5b4b3 b2b1b0 Port P0 direction register (P0D) [Address 0116] Port P1 direction register (P1D) [Address 0316] B Name Functions At reset R W Port P0 direction register, port P1 direction register to Port P0 direction register / Port P1 direction register 0 : All bits are input mode 1 : All bits are output mode Note: In ports P0 and P1, input/output switching is performed by a port unit. By setting bit 0 of the corresponding port direction register to “0”, the port is set for the input mode. By setting to “1”, the port is set for the output mode. Nothing is allocated for bits 1 to 7 of the ports P0 and P1 direction registers, and these bits cannot be written to. Nothing is allocated. These bits cannot be written to and be read out. 0 × 0 ×× Notes 1: Nothing is allocated bit 0 of port P4 direction register and bit 2 to bit 7 of port P7 direction register. These bits cannot be written to. 2: The contents of the port Pi direction register cannot be read out (refer to “2.1.4 Notes on use”). b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 2, 4 to 7) [Address 05 16, 0916, 0B16, 0D16, 0F16] B Name Functions At reset R W Port Pi direction register Port Pi direction register 0 : Port Pi 0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode

3820 GROUP USER’S MANUAL 3–17

Fig. 3.3.4 Structure of PULL register B Fig. 3.3.3 Structure of PULL register A b7 b6b5b4 b3b2b1 b0 PULL register A (PULLA) [Address 1616] B Name Functions At resetR W PULL register A 1 : Pull-down Note: For ports set for the output mode, pull-up or pull-down is impossible. 1 : Pull-down 1 : Pull-up 1 : Pull-down 1 : Pull-up to Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. 0 0 b7b6 b5b4b3 b2b1b0 PULL register B (PULLB) [Address 1716] B Name Functions At resetR W PULL register B 1 : Pull-up Note: For ports set for the output mode, pull-up is impossible. 1 0 : No pull-up 1 : Pull-up 2 0 : No pull-up 1 : Pull-up 3 0 : No pull-up 1 : Pull-up 4 0 : No pull-up 1 : Pull-up Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60, P61 pull-up to ×00

3820 GROUP USER’S MANUAL3–18

Fig. 3.3.5 Structure of serial I/O1 status register b7b6 b5b4b3 b2b1b0 Serial I/O1 status register (SIO1STS) [Address 1916] B At reset R W Serial I/O1 status register Name Functions Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading. Summing error flag (SE) 0: (OE) U (PE) U (FE) = 0 1: (OE) U (PE) U (FE) = 1

3820 GROUP USER’S MANUAL 3–19

Fig. 3.3.6 Structure of serial I/O1 control register b7b6 b5b4b3 b2b1b0 Serial I/O1 control register (SIO1CON) [Address 1A16] B At reset R W Serial I/O1 control register Name Functions BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronization clock selection bit (SCS)

• In clock synchronous mode 0: BRG output/4 1: External clock input
• In UART mode 0: BRG output/16 1: External clock input/16 Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 enable bit (SIOE) Serial I/O1 mode selection bit (SIOM) S RDY1 output enable bit (SRDY) 0: P47/SRDY1 pin operates as I/O port P47 1: P47/SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) 0: When transmit buffer has emptied 1: When transmit shift operation is completed 0: Transmit disabled 1: Transmit enabled Clock asynchronous serial I/O1 (UART) mode 1: Clock synchronous serial I/O1 mode 0: Serial I/O1 disabled (pins P44–P47 operate as I/O pins) 1: Serial I/O1 enabled (pins P44–P47 operate as serial I/O1 pins) 0: Receive disabled 1: Receive enabled

3820 GROUP USER’S MANUAL3–20

Fig. 3.3.7 Structure of UART control register Fig. 3.3.8 Structure of serial I/O2 control register b7b6 b5b4b3 b2b1b0 UART control register (UARTCON) [Address 1B16] B At reset R W UART control register to Name Functions Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TxD P-channel output disable bit (POFF) CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Nothing is allocated. These bits cannot be written to and are fixed to “1” at reading. Parity selection bit (PARS) 0: Even parity 1: Odd parity b7b6 b5b4b3 b2b1b0 Serial I/O2 control register (SIO2CON) [Address 1D16] B At reset R W Serial I/O2 control register Name Functions Internal synchronization clock select bits 0 0 0: f(X IN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: 1 0 1: 1 1 0: f(X IN)/128 1 1 1: f(XIN)/256 SRDY2 output enable bit Transfer direction selection bit Synchronization clock selection bit Serial I/O2 port selection bit I/O port (P51, P52) 1: SOUT2 , SCLK2 signal output 0: I/O port (P53) 1: SRDY2 signal output 0: LSB first 1: MSB first 0: External clock 1: Internal clock b2b1b0 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 1 0 Do not set

3820 GROUP USER’S MANUAL 3–21

Fig. 3.3.9 Structure of timer X mode register b7b6 b5b4b3 b2b1b0 Timer X mode register (TXM) [Address 2716] B Name Functions At reset R W Timer X mode register Timer X write control bit 0 : Count start 1 : Count stop 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit P60 data for real time port P61 data for real time port Timer X operating mode bits CNTR 0 active edge switch bit Timer X stop control bit 0 : Real time port function invalid 1 : Real time port function valid 0 : “L” level output 1 : “H” level output 0 : “L” level output 1 : “H” level output 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode

• CNTR 0 interrupt 0 : Falling edge active 1 : Rising edge active
• Pulse output mode 0 : Start at initial level “H” output 1 : Start at initial level “L” output
• Event counter mode 0 : Rising edge active 1 : Falling edge active
• Pulse width measurement mode 0 : Measure “H” level width 1 : Measure “L” level width b5b4

3820 GROUP USER’S MANUAL3–22

Fig. 3.3.10 Structure of timer Y mode register b7b6 b5b4b3 b2b1b0 Timer Y mode register (TYM) [Address 2816] B Name Functions At reset R W Timer Y mode register to Nothing is allocated. These bits cannot be written and are fixed to “0” at reading. Timer Y operating mode bits CNTR 1 active edge switch bit Timer Y stop control bit 0 : Count start 1 : Count stop 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode

• CNTR 1 interrupt 0 : Falling edge active 1 : Rising edge active
• Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge
• Event counter mode 0 : Rising edge active 1 : Falling edge active b5b4 0 ×

3820 GROUP USER’S MANUAL 3–23

Fig. 3.3.11 Structure of timer 123 mode register Fig. 3.3.12 Structure of φ output control register b7b6 b5b4b3 b2b1b0 Timer 123 mode register (T123M) [Address 2916] B Name Functions At reset R W Timer 123 mode register 6, 7 TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT output control bit Timer 2 write control bit Timer 2 count source selection bit Timer 3 count source selection bit Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. 0 : TOUT output disabled 1 : TOUT output enabled 0 : Write value in latch and counter 1 : Write value in latch only 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Timer 1 count source selection bit 0 : f(XIN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) 1 : f(X CIN) 0 : Timer 1 underflow 1 : f(X IN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode) (Note) Note: Internal clock φ is f(XCIN)/2 in the low-speed mode. b7b6 b5b4b3 b2b1b0 φ output control register (CKOUT) [Address 2A16] B Name Functions At reset R W φ output control register to φ output control bit0: Port function 1: φ clock output (Port direction register = “1”) 0 0 Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading.

3820 GROUP USER’S MANUAL3–24

Fig. 3.3.13 Structure of watchdog timer control register Fig. 3.3.14 Structure of segment output register b7b6 b5b4b3 b2b1b0 Watchdog timer control register (WDTCON) [Address 3716] B At reset R W Watchdog timer control register to Name Functions Watchdog timer H bits At reading, the count value of watchdog timer H is read. ×6 Nothing is allocated. This bit cannot be written to and is fixed to “1” at reading. 0: Underflow from watchdog timer L (WDT is used as 14-bit timer) 1: f(X IN)/16 or f(XCIN)/16 (WDT is used as 6-bit timer) (Note) Note: When a value is written to address 3716, the following values are set, so that the watchdog timer starts a count operation. Watchdog timer H = “3F16” Watchdog timer L = “FF16” b7b6 b5b4b3 b2b1b0 Segment output enable register (SEG) [Address 3816] B Name Functions At reset R W Segment output enable register 6,7 Segment output enable bit 0 00 0 Fix these bits to “0.” Segment output enable bit 1 Segment output enable bit 2 Segment output enable bit 3 Segment output enable bit 4 Segment output enable bit 5 0: Input ports P30–P37 1: Segment output SEG16–SEG 23 0: I/O ports P00, P01 1: Segment output SEG24, SEG25 0: I/O ports P02–P07 1: Segment output SEG26–SEG 31 0: I/O port P12 1: Segment output SEG34 0: I/O ports P10, P11 1: Segment output SEG32, SEG33 0: I/O ports P13–P17 1: Segment output SEG35–SEG 39

3820 GROUP USER’S MANUAL 3–25

Fig. 3.3.15 Structure of LCD mode register b7b6 b5b4b3 b2b1b0 LCD mode register (LM) [Address 3916] B Name Functions At reset R W LCD mode register Duty ratio selection bits LCDCK count source selection bit (Note 2) Bias control bit LCD enable bit Fix this bit to “0.” LCD circuit divider division ratio selection bits (Note 1) b1b0 00: Not available 01: 2 (use COM 0, COM1) 10: 3 (use COM0–COM 2) 11: 4 (use COM0–COM 3) 0: 1/3 bias 1: 1/2 bias 0: LCD OFF 1: LCD ON 0: f(X CIN)/32 1: f(XIN)/8192 b6b5 00: LCDCK count source 01: 2 division of LCDCK count source 10: 4 division of LCDCK count source 11: 8 division of LCDCK count source Notes 1: Reference values at f(XIN) = 8 MHz 00: 977 Hz 01: 488 Hz 10: 244 Hz 11: 122 Hz 2: LCDCK is a clock for a LCD timing controller.

3820 GROUP USER’S MANUAL3–26

Fig. 3.3.17 Structure of CPU mode register Fig. 3.3.16 Structure of interrupt edge selection register b7b6 b5b4b3 b2b1b0 Interrupt edge selection register (INTEDGE) [Address 3A16] B Name Functions At reset R W Interrupt edge selection register 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Nothing is allocated. These bits cannot be written to and are fixed to “0” at reading. to 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7b6 b5b4b3 b2b1b0 CPU mode register (CPUM) [Address 3B16] B At reset R W CPU mode register Name Functions Processor mode bits 00: Single-chip mode 01: 10: Not available 11: Fix this bit to “1.” Main clock (XIN–XOUT ) stop bit Main clock division ratio selection bit Port X C switch bit 0Stack page selection bit Internal system clock selection bit b1b0 0: 0 page 1: 1 page 0: I/O port 1: X CIN, XCOUT 0: Oscillating 1: Stopped 0: f(X IN)/2 (high-speed mode) 1: f(X IN)/8 (middle-speed mode) 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode)

3820 GROUP USER’S MANUAL 3–27

Fig. 3.3.19 Structure of interrupt request register 2 Fig. 3.3.18 Structure of interrupt request register 1 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 3D16] B Name Functions At resetRW Interrupt request register 2 0 : No interrupt request issued 1 : Interrupt request issued ] : “0” can be set by software, but “1” cannot be set. 7 Nothing is allocated. This bit cannot be written to and is fixed to “0” at reading. 0 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 3C16] B Name Functions At reset R W Interrupt request register 1 0 0 : No interrupt request issued 1 : Interrupt request issued 0 ]INT0 interrupt request bit

2 Serial I/O receive

3 Serial I/O transmit

] : “0” is set by software, but not “1.” 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

3820 GROUP USER’S MANUAL3–28

Fig. 3.3.21 Structure of interrupt control register 2 Fig. 3.3.20 Structure of interrupt control register 1 b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 3E16] B Name Functions At resetRW Interrupt control register 1 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 3F16] B Name Functions At resetRW Interrupt control register 2 0 : Interrupts disabled 1 : Interrupts enabled

4 INT3 interrupt enable

7 Fix this bit to “0.” 0 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled

D 7 – D4 D 3 – D0 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F 0000 BRK BPL JSR ABS BMI RTI BVC RTS BVS BRA BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ 0001 ORA IND, X ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y ADC IND, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X LDA IND, Y CMP IND, X CMP IND, Y SBC IND, X SBC IND, Y 0010 JSR ZP, IND CLT JSR SP SET STP (Note) MUL (Note) RRF ZP LDX IMM JMP ZP, IND 0011 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 0100 BIT ZP COM ZP TST ZP STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP CPX ZP 0101 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 0110 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 0111 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 1000 PHP CLC PLP SEC PHA CLI PLA SEI DEY TYA TAY CLV INY CLD INX SED 1001 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y 1010 A ASL A DEC A ROL A INC A LSR A ROR A TXA TXS TAX TSX DEX NOP 1011 B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A 1100 C BIT ABS LDM ZP JMP ABS JMP IND STY ABS LDY ABS LDY ABS, X CPY ABS CPX ABS 1101 D ORA ABS ORA ABS, X AND ABS AND ABS, X EOR ABS EOR ABS, X ADC ABS ADC ABS, X STA ABS STA ABS, X LDA ABS LDA ABS, X CMP ABS CMP ABS, X SBC ABS SBC ABS, X 1110 E ASL ABS ASL ABS, X ROL ABS ROL ABS, X LSR ABS LSR ABS, X ROR ABS ROR ABS, X STX ABS LDX ABS LDX ABS, Y DEC ABS DEC ABS, X INC ABS INC ABS, X 1111 F SEB 0, ZP CLB 0, ZP SEB 1, ZP CLB 1, ZP SEB 2, ZP CLB 2, ZP SEB 3, ZP CLB 3, ZP SEB 4, ZP CLB 4, ZP SEB 5, ZP CLB 5, ZP SEB 6, ZP CLB 6, ZP SEB 7, ZP CLB 7, ZP SLW (Note) WIT FST (Note) DIV

3820 GROUP USER’S MANUAL3-30

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # APPENDIX

3.5 Machine instructions

Adds the carry, accumulator and memory con- tents. The results are entered into the accumulator. Adds the contents of the memory in the ad- dress indicated by index register X, the contents of the memory specified by the ad- dressing mode and the carry. The results are entered into the memory at the address indi- cated by index register X. “AND’s” the accumulator and memory con- tents. The results are entered into the accumulator. “AND’s” the contents of the memory of the ad- dress indicated by index register X and the contents of the memory specified by the ad- dressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit speci- fied in the accumulator or memory is “0”. Branches when the contents of the bit speci- fied in the accumulator or memory is “1”. Branches when the contents of carry flag is “0”. Branches when the contents of carry flag is “1”. Branches when the contents of zero flag is “1”. “AND’s” the contents of accumulator and memory. The results are not entered any- where. Branches when the contents of negative flag is “1”. Branches when the contents of zero flag is “0”. Branches when the contents of negative flag is “0”. Jumps to address specified by adding offset to the program counter. Executes a software interrupt. ADC (Note 1) (Note 5) AND (Note 1) ASL BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA BRK 7 0 C ← ← 0 29 2 2 0A 2 1 03+2i 17+2i 07+2i 06 5 2 25 3 2 65 3 269 2 2 13+2i When T = 0 A ← A + M + C When T = 1 M(X) ← M(X) + M + C When T = 0 A ← A M When T = 1 M(X) ← M(X) M Ab or Mb = 0? Ab or Mb = 1? C = 0? C = 1? Z = 1? A M N = 1? Z = 0? N = 0? PC ← PC ± offset B ← 1 M(S) ← PC H S ← S – 1 M(S) ← PCL S ← S – 1 M(S) ← PS S ← S – 1 PC L ← ADL PC H ← ADH V V V 2

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-313820 GROUP USER’S MANUAL APPENDIX N N N M V M Z Z Z Z C C

3820 GROUP USER’S MANUAL3-32

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # APPENDIX Branches when the contents of overflow flag is “0”. Branches when the contents of overflow flag is “1”. Clears the contents of the bit specified in the accumulator or memory to “0”. Clears the contents of the carry flag to “0”. Clears the contents of decimal mode flag to “0”. Clears the contents of interrupt disable flag to “0”. Clears the contents of index X mode flag to “0”. Clears the contents of overflow flag to “0”. Compares the contents of accumulator and memory. Compares the contents of the memory speci- fied by the addressing mode with the contents of the address indicated by index register X. Forms a one’s complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1’s complement of the remainder on the stack. “Exclusive-ORs” the contents of accumulator and memory. The results are stored in the ac- cumulator. “Exclusive-ORs” the contents of the memory specified by the addressing mode and the contents of the memory at the address indi- cated by index register X. The results are stored into the memory at the address indi- cated by index register X. Connects oscillator output to the X OUT pin. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by Increments the contents of index register Y by BVC (Note 4) BVS (Note 4) CLB CLC CLD CLI CLT CLV CMP (Note 3) COM CPX CPY DEC DEX DEY DIV EOR (Note 1) FST INC INX INY V = 0? V = 1? Ab or Mb ← 0 C ← 0 D ← 0 I ← 0 T ← 0 V ← 0 When T = 0 A – M When T = 1 M(X) – M M ← M X – M Y – M A ← A – 1 or M ← M – 1 X ← X – 1 Y ← Y – 1 A ← (M(zz + X + 1), M(zz + X)) / A M(S) ← 1’s complememt of Remainder S ← S – 1 When T = 0 A ← A V– M When T = 1 M(X) ← M(X) V– M A ← A + 1 or M ← M + 1 X ← X + 1 Y ← Y + 1 CA 1B+2i 1F+2i 21 52

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-333820 GROUP USER’S MANUAL APPENDIX N N N N N N N N N N N DD DE FE Z Z Z Z Z Z Z Z Z Z Z C C C

3820 GROUP USER’S MANUAL3-34

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # APPENDIX Jumps to the specified address. After storing contents of program counter in stack, and jumps to the specified address. Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the ad- dressing mode. Load memory with immediate value. Load index register X with contents of memory. Load index register Y with contents of memory. Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X address- ing mode and stores the high byte of the result on the stack and the low byte in the accumula- tor. No operation. “Logical OR’s” the contents of memory and ac- cumulator. The result is stored in the accumulator. “Logical OR’s” the contents of memory indi- cated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X. JMP JSR LDA (Note 2) LDM LDX LDY LSR MUL (Note 5) NOP ORA (Note 1) If addressing mode is ABS PC L ← ADL PC H ← ADH If addressing mode is IND PC L ← M (ADH , ADL) PC H ← M (ADH , ADL + 1) If addressing mode is ZP, IND PC L ← M(00, ADL) PC H ← M(00, ADL + 1) M(S) ← PCH S ← S – 1 M(S) ← PCL S ← S – 1 After executing the above, if addressing mode is ABS, PC L ← ADL PC H ← ADH if addressing mode is SP, PC L ← ADL PC H ← FF If addressing mode is ZP, IND, PC L ← M(00, ADL) PC H ← M(00, ADL + 1) When T = 0 A ← M When T = 1 M(X) ← M M ← nn X ← M Y ← M M(S) · A ← A 5 M(zz + X) S ← S – 1 PC ← PC + 1 When T = 0 A ← A V M When T = 1 M(X) ← M(X) V M 4A 2 1 EA 2 1 7 0 0→ → C

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-353820 GROUP USER’S MANUAL APPENDIX N N N N Z Z Z Z Z C B6 4 2 BD BC BE

53 B 2

3820 GROUP USER’S MANUAL3-36

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # APPENDIX Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumu- lator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumu- lator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. Returns from an interrupt routine to the main routine. Returns from a subroutine to the main routine. Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the ad- dress indicated by index register X. The results are stored into the memory of the ad- dress indicated by index register X. Sets the specified bit in the accumulator or memory to “1”. Sets the contents of the carry flag to “1”. Sets the contents of the decimal mode flag to “1”. Sets the contents of the interrupt disable flag to “1”. Sets the contents of the index X mode flag to “1”. Disconnects the oscillator output from the X OUT pin. PHA PHP PLA PLP ROL ROR RRF RTI RTS SBC (Note 1) (Note 5) SEB SEC SED SEI SET SLW M(S) ← A S ← S – 1 M(S) ← PS S ← S – 1 S ← S + 1 A ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) When T = 0 A ← A – M – C When T = 1 M(X) ← M(X) – M – C Ab or Mb ← 1 C ← 1 D ← 1 I ← 1 T ← 1 7 0 ← ← C ← 7 0 → → 0B+2i 0F+2i 21 52 7 0 C → →

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-373820 GROUP USER’S MANUAL APPENDIX N N N N V Z Z Z Z C C C FD 3F 95 3 E 16 2F 16 2 (Value saved in stack) (Value saved in stack)

3820 GROUP USER’S MANUAL3-38

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # APPENDIX Stores the contents of accumulator in memory. Stops the oscillator. Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are “0” or not. Transfers the contents of the stack pointer to index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. STA STP STX STY TAX TAY TST TSX TXA TXS TYA WIT M ← A M ← X M ← Y X ← A Y ← A M = 0? X ← S A ← X S ← X A ← Y AA BA Notes 1 : The number of cycles “n” is increased by 3 when T is 1. 2 : The number of cycles “n” is increased by 2 when T is 1. 3 : The number of cycles “n” is increased by 1 when T is 1. 4 : The number of cycles “n” is increased by 2 when branching has occurred. 5 : N, V, and Z flags are invalid in decimal operation mode.

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-393820 GROUP USER’S MANUAL APPENDIX N N N N N N Z Z Z Z Z Z 96 5 2

9 D 63 9 9 63 8 1 72 9 1 72

Symbol Contents Symbol Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any ad- dressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by AD H and AD L, in ADH is 8 high-order bits and ADL is 8 low-or- der bits. Contents of address indicated by zero page AD L 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N V X Y S PC PS PC H PC L AD H AD L FF nn M M(X) M(S) M(AD H , ADL) M(00, ADL) Ab Mb OP n V

3820 GROUP USER’S MANUAL3-40

GZZ-SH06-14B<25B0> Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M38203M4-XXXFP/GP/HP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 000016 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16 M38203M4-XXXFP Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38203M4–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) 000016 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38203M4–’ data ROM 16254 bytes Product name ASCII code : ‘M38203M4–’ data ROM 16254 bytes M38203M4-XXXHPM38203M4-XXXGP

3-413820 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M38203M4-XXXFP/GP/HP MITSUBISHI ELECTRIC GZZ-SH06-14B<25B0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. 27256 27512EPROM type The pseudo-command *= $8000 .BYTE ‘M38203M4–’ *= $0000 .BYTE ‘M38203M4–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38203M4-XXXFP,80P6S for M38203M4-XXXGP,80P6D for M38203M4-XXXHP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? Ceramic resonator External clock input Ports P71 and P70 function Quartz crystal Other ( ) XCIN and XCOUT function (external resonator) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-42

GZZ-SH07-60B<36A0> Receipt SINGLE-CHIP MICROCOMPUTER M38203M4DXXXFP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. 27256 27512 000016 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16 Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38203M4D” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘D’ = 4416 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) 000016 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38203M4D’ data ROM 16254 bytes Product name ASCII code : ‘M38203M4D’ data ROM 16254 bytes

3-433820 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M38203M4DXXXFP MITSUBISHI ELECTRIC GZZ-SH07-60B<36A0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. 27256 27512EPROM type The pseudo-command *= $8000 .BYTE ‘M38203M4D’ *= $0000 .BYTE ‘M38203M4D’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38203M4DXXXFP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? Ceramic resonator External clock input Ports P71 and P70 function Quartz crystal Other ( ) XCIN and XCOUT function (external resonator) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-44

M38207M8-XXXFP M38207M8-XXXHPM38207M8-XXXGP GZZ-SH06-58B<2XB0> Receipt SINGLE-CHIP MICROCOMPUTER M38207M8-XXXFP/GP/HP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38207M8–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘7’ = 3716 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 807F16 808016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38207M8–’ data ROM 32638 bytes

3-453820 GROUP USER’S MANUAL APPENDIX Ports P71 and P70 function X CIN and XCOUT function (external resonator) (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? 27512 *= $0000 .BYTE ‘M38207M8–’ SINGLE-CHIP MICROCOMPUTER M38207M8-XXXFP/GP/HP MITSUBISHI ELECTRIC GZZ-SH06-58B<2XB0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38207M8-XXXFP,80P6S for M38207M8-XXXGP,80P6D for M38207M8-XXXHP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = Ceramic resonator External clock input Quartz crystal Other ( ) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-46

GZZ-SH08-64B<45A0> Receipt SINGLE-CHIP MICROCOMPUTER M38207M8DXXXFP/GP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M38207M8DXXXFP M38207M8DXXXGP Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38207M8D” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘7’ = 3716 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘D’ = 4416 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM type (indicate the type used) 27512 EPROM address 000016 000F16 001016 807F16 808016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38207M8D’ data ROM 32638 bytes

3-473820 GROUP USER’S MANUAL APPENDIX Ports P71 and P70 function X CIN and XCOUT function (external resonator) (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? 27512 *= $0000 .BYTE ‘M38207M8D’ SINGLE-CHIP MICROCOMPUTER M38207M8DXXXFP/GP MITSUBISHI ELECTRIC GZZ-SH08-64B<45A0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38207M8DXXXFP,80P6S for M38207M8DXXXGP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = Ceramic resonator External clock input Quartz crystal Other ( ) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-48

M38203M4LXXXFP M38203M4LXXXHPM38203M4LXXXGP GZZ-SH08-63B<45B0> Receipt SINGLE-CHIP MICROCOMPUTER M38203M4LXXXFP/GP/HP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 000016 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16 Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38203M4L” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ L ’ = 4C16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) 000016 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38203M4L’ data ROM 16254 bytes Product name ASCII code : ‘M38203M4L’ data ROM 16254 bytes

3-493820 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M38203M4LXXXFP/GP/HP MITSUBISHI ELECTRIC GZZ-SH08-63B<45B0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. 27256 27512EPROM type The pseudo-command *= $8000 .BYTE ‘M38203M4L’ *= $0000 .BYTE ‘M38203M4L’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38203M4LXXXFP,80P6S for M38203M4LXXXGP,80P6D for M38203M4LXXXHP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? Ceramic resonator External clock input Ports P71 and P70 function Quartz crystal Other ( ) XCIN and XCOUT function (external resonator) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-50

M38203M2LXXXFP M38203M2LXXXHPM38203M2LXXXGP GZZ-SH08-46B<43B0> Receipt SINGLE-CHIP MICROCOMPUTER M38203M2LXXXFP/GP/HP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 000016 000F16 001016 607F16 608016 7FFD16 7FFE16 7FFF16 Checksum code for entire EPROM (hexadecimal notation) In the address space of the microcomputer, the internal ROM area is from address E08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M38203M2L” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘2’ = 3216 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ L ’ = 4C16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) 000016 000F16 001016 E07F16 E08016 FFFD16 FFFE16 FFFF16 Product name ASCII code : ‘M38203M2L’ data ROM 8062 bytes Product name ASCII code : ‘M38203M2L’ data ROM 8062 bytes

3-513820 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M38203M2LXXXFP/GP/HP MITSUBISHI ELECTRIC GZZ-SH08-46B<43B0> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembier source program. 27256 27512EPROM type The pseudo-command *= $8000 .BYTE ‘M38203M2L’ *= $0000 .BYTE ‘M38203M2L’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. We recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6N for M38203M2LXXXFP,80P6S for M38203M2LXXXGP,80P6D for M38203M2LXXXHP) and attach it to the mask ROM confirmation form. h 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? At what frequency? f(X IN) = (2) Which function will you use the pins P71/XCIN and P70/XCOUT as P71 and P70, or XCIN and XCOUT ? Ceramic resonator External clock input Ports P71 and P70 function Quartz crystal Other ( ) XCIN and XCOUT function (external resonator) MHz h 4. Comments

3820 GROUP USER’S MANUAL3-52

3.7 Mark specification from

3-533820 GROUP USER’S MANUAL APPENDIX

3820 GROUP USER’S MANUAL3-54

3.8 Package outlines

3-553820 GROUP USER’S MANUAL APPENDIX

3820 GROUP USER’S MANUAL3-56

Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) Timer 3 (T3) Timer X mode register (TXM) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X (low-order) (TXL) Timer Y (low-order) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high-order) (TXH) Timer Y (high-order) (TYH) PULL register A (PULL A) PULL register B (PULL B) Timer Y mode register (TYM) Timer 123 mode register (T123M) f output control register (CKOUT) Segment output enable register (SEG) LCD mode register (LM)

3-573820 GROUP USER’S MANUAL APPENDIX

3.10 Pin configuration

PIN CONFIGURATION (TOP VIEW) Pin configuration of M38203M4-XXXFP Package type : 80P6N-A 80-pin plastic-molded QFP P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/ P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN M38203M4-XXXFP 123 456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 414243444546474849505152535455565758596061626364 M38203M4-XXXFP

3820 GROUP USER’S MANUAL3-58

PIN CONFIGURATION (TOP VIEW) Pin configuration of M38203M4-XXXGP/ HP Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/ P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN 1234 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 056 4142434445464748495051525354555657585960 M38203M4-XXXGP M38203M4-XXXHP

USER’S MANUAL 3820Group Jul. First Edition 1995 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1995 MITSUBISHI ELECTRIC CORPORATION

User’s Manual H-EE367-A KI-9507 Printed in Japan (ROD) © 1995 MITSUBISHI ELECTRIC CORPORATION New publication, effective Jul. 1995. Specifications subject to change without notice.

MESC TECHNICAL NEWS No. (1/ ) GRADE Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” This news includes a few corrections and supplementary explanation for the following documents. Please refer to the corrected information as shown below. l User’s Manual attaching this news

• 3820 Group (Printed & PDF documents, 1995.7 issued, document number: H-EE367-A)
• 3822 Group (Printed & PDF documents, 1995.3 issued, document number: H-ED347-A)
• 3825 Group (Printed & PDF documents, 1995.7 issued, document number: H-EE379-A) M380-14-9907 A

Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.1

3820 Group User’s Manual P2-66

3822 Group User’s Manual P2-65

3825 Group User’s Manual P2-65

(1) Timer X n Timer mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the timer X interrupt enable bit and the timer X interrupt request bit to “0”.
• After setting ˆ below, set the timer X interrupt enable bit to “1” (interrupts enabled). M380-14-9907 [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer X stops counting (before setting À below), clear the timer X interrupt enable bit to “0”.
• After setting ´ below, clear the timer X interrupt request bit to “0” and next set the timer X interrupt enable bit to “1” (interrupt en- abled).
• Set ˆ last.

3820 Group User’s Manual P2-67

3822 Group User’s Manual P2-66

3825 Group User’s Manual P2-66

(1) Timer X n Pulse output mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer X or CNTR 0) and the interrupt request bits (timer X or CNTR0) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR 0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer X stops counting (before setting \` below), clear the interrupt enable bit (timer X or CNTR0) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer X or CNTR 0) to “0” and next set the interrupt enable bit (timer X or CNTR 0) to “1” (interrupt enabled).
• Set ˜ last. Previous change

3820 Group User’s Manual P2-68

3822 Group User’s Manual P2-67

3825 Group User’s Manual P2-67

(1) Timer X n Event counter mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer X or CNTR 0) and the interrupt request bits (timer X or CNTR0) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR 0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer X stops counting (before setting \` below), clear the interrupt enable bit (timer X or CNTR0) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer X or CNTR 0) to “0” and next set the interrupt enable bit (timer X or CNTR 0) to “1” (interrupt enabled).
• Set ˜ last. Previous change (2 / 4)

Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.2

3820 Group User’s Manual P2-71

3822 Group User’s Manual P2-70

3825 Group User’s Manual P2-70

(2) Timer Y n Timer mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the timer Y interrupt enable bit and the timer Y interrupt request bit to “0”.
• After setting ˆ below, set the timer Y interrupt enable bit to “1” (interrupts enabled). M380-14-9907

3820 Group User’s Manual P2-72

3822 Group User’s Manual P2-71

3825 Group User’s Manual P2-71

(2) Timer Y n Period measurement mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR1) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled). After change Previous change

3820 Group User’s Manual P2-73

3822 Group User’s Manual P2-72

3825 Group User’s Manual P2-72

(2) Timer Y n Event counter mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR1) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled). After change Previous change

3820 Group User’s Manual P2-69

3822 Group User’s Manual P2-68

3825 Group User’s Manual P2-68

(1) Timer X n Pulse width measurement mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer X or CNTR 0) and the interrupt request bits (timer X or CNTR0) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer X or CNTR 0) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer X stops counting (before setting \` below), clear the interrupt enable bit (timer X or CNTR0) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer X or CNTR 0) to “0” and next set the interrupt enable bit (timer X or CNTR 0) to “1” (interrupt enabled).
• Set ˜ last. [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer Y stops counting (before setting À below), clear the timer Y interrupt enable bit to “0”.
• After setting ´ below, clear the timer Y interrupt request bit to “0” and next set the timer Y interrupt enable bit to “1” (interrupt en- abled).
• Set ˆ last. [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer Y stops counting (before setting \` below), clear the interrupt enable bit (timer Y or CNTR1) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer Y or CNTR 1) to “0” and next set the interrupt enable bit (timer Y or CNTR 1) to “1” (interrupt enabled).
• Set ˜ last. [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer Y stops counting (before setting \` below), clear the interrupt enable bit (timer Y or CNTR1) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer Y or CNTR 1) to “0” and next set the interrupt enable bit (timer Y or CNTR 1) to “1” (interrupt enabled).
• Set ˜ last. (3 /4)

Corrections and Supplementary Explanation for “3820/3822/3825 Group User’s Manuals” No.3 M380-14-9907

3820 Group User’s Manual P2-74

3822 Group User’s Manual P2-73

3825 Group User’s Manual P2-73

(2) Timer Y n Pulse width HL continu- ously measurement mode [Notes on use] Notes 1: For using interrupt processing, set the following:

• Before setting À below, clear the interrupt enable bits (timer Y or CNTR 1) and the interrupt request bits (timer Y or CNTR1) to “0”.
• After setting ˜ below, set the interrupt enable bits (timer Y or CNTR 1) to “1” (interrupts enabled). After change [Notes on use] Notes 1: For using interrupt processing, set the following:
• Before timer Y stops counting (before setting \` below), clear the interrupt enable bit (timer Y or CNTR1) to “0”.
• After setting ˆ below, clear the interrupt request bit (timer Y or CNTR 1) to “0” and next set the interrupt enable bit (timer Y or CNTR 1) to “1” (interrupt enabled).
• Set ˜ last. (4 /4)