3740

LT3740 LINER

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FEATURES

APPLICATIONS

DESCRIPTION

Wide Operating Range, Valley Mode, No RSENSE™ Synchronous Step-Down Controller The L T®3740 is a synchronous step-down switching regulator controller that drives N-channel power MOSFET stages. The controller uses valley current mode architecture to achieve very low duty cycles with excellent transient response without requiring a sense resistor. The L T3740 includes an internal step-up converter to provide a bias 7.8V higher than the input voltage for the drive. This enables the part to work from an input voltage as low as 2.2V. The XREF pin is an external reference input that allows the user to override the internal 0.8V feedback reference with any lower value, allowing full control of the output voltage during operation, output voltage tracking or soft-start. The L T3740 has three current limit levels that can be chosen by connecting the RANGE pin to ground, open, and input respectively. High Effi ciency Step-Down Converter n Wide VIN Range: 2.2V to 22V n Internal Boost Provides 6V Gate Drive For VIN Down to 2.2V n No Sensing Resistor Required n Dual N-Channel MOSFET Synchronous Drive n Valley Current Mode Control n Optimized for High Step-Down Ratio n Power Good Output Voltage Monitor n 0.8V Reference n Three Pin-Selected Current Limit Levels n Constant Switching Frequency: 300kHz n Programmable Soft-Start n Output Voltage T racking n Available in 16-Pin 5mm × 3mm DFN n Notebook and Palmtop Computers, PDA n Portable Instruments n Distributed Power Systems L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Effi ciency vs Load Current SWB VIN SHDN XREF RANGE VC BGDP BIAS TGATE SW SN+ BGATE GND L T3740 SN– PGND FB

3740 TA01a

0.9μH 1μF 0.22μF VOUT 1.8V 10A VIN 3V to 12V HAT2168H HAT2165H 100μF s 3 10μF 39pF 22μH 20k 15k 1nF 22pF 80.6k 105k15k B320A1Ω LOAD CURRENT (A) EFFICIENCY (%)

3740 TA01b

VIN = 3V VIN = 5V VIN = 12V VOUT = 1.8V

Operating Temperature Range (Note 2)....–40°C to 85°C (Note 1) ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 5V unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operation Voltage ● 2.2 V Maximum Operation Voltage ● 22 V Input Supply Current SHDN = 0V SHDN = 5V, BIAS = 14V, FB = 1.5V 0.6 2.5 μA mA Feedback Reference Voltage XREF=1V

• 794 800 808 mV Feedback Voltage Line Regulation V IN = 2.5V to 22V 0.006 % FB Pin Input Current FB = 800mV 230 nA Error Amplifi er T ransconductance VC = 1.2V 380 μS Controller Switching Frequency ● 260 300 330 kHz Minimum BGATE On Time (Note 3) 500 700 ns Current Limit RANGE = 0V RANGE = Open RANGE = V IN 105 115 140 mV mV mV Reverse Current Limit 35 mV PIN CONFIGURATION V C FB XREF SHDN PGOOD RANGE V IN SWB SN– PGND BGATE BGDP SN+ SW TGATE BIAS TOP VIEW DHC PACKAGE 16-LEAD (5mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD IS GND (PIN 17), MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3740EDHC#PBF L T3740EDHC#TRPBF 3740 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3740EDHC L T3740EDHC#TR 3740 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 5V unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS SHDN Voltage to Enable Device ● 1.1 V SHDN Voltage to Disable Device ● 0.5 V TGATE On Voltage 5.5 V TGATE Off Voltage 0.2 V BGATE On Voltage 5.5 V BGATE Off Voltage 0.2 V TGATE Rise Time C LOAD = 3300pF 30 ns TGATE Fall Time C LOAD = 3300pF 30 ns BGATE Rise Time C LOAD = 3300pF 50 ns BGATE Fall Time C LOAD = 3300pF 50 ns PGOOD Threshold ● 720 740 765 mV PGOOD Low Voltage I PGOOD = 100μA ● 0.2 V PGOOD Current Capacity 500 μA Internal Boost Switching Frequency 0.8 1 1.2 MHz Internal Boost Switch Current Limit 360 440 520 mA (BIAS – V IN) in Operation 7.8 V (BIAS – VIN) to Start Controller 7.2 V Note 2: The L T3740E is guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The minimum off time of the L T3740 application consists of the minimum BGATE on time, the delay from TGATE OFF to BGATE ON (80ns) and the delay from BGATE OFF to TGATE ON (80ns). TYPICAL PERFORMANCE CHARACTERISTICS T ransient Response T ransient Response Shutdown Pin Start-Up (TA = 25°C, unless otherwise noted) LOAD STEP 0A TO 10A VIN = 10V , VOUT = 2.5V FIGURE 4 CIRCUIT VOUT 50mV/DIV IL 5A/DIV

3740 G01

20μs/DIV LOAD STEP 0A TO 10A V IN = 5V , VOUT = 1.8V PAGE 17 CIRCUIT VOUT 50mV/DIV IL 5A/DIV

3740 G02

10μs/DIV

3740 G03

VIN = 10V , VOUT = 2.5V ILOAD = 3A SHDN 2V/DIV VO 2V/DIV IL 2A/DIV 2ms/DIV

TYPICAL PERFORMANCE CHARACTERISTICS Shutdown vs Maximum VC VC vs Current Sensing Threshold Feedback Reference Voltage vs Temperature PGOOD Threshold vs Temperature Shutdown Threshold vs Temperature Switching Frequency vs Temperature SHUTDOWN (V) MAXIMUM VC (V) 1.0 0.8 1.6 1.4 1.8 1.2 2.0

3740 G07

0.6 0.4 0.2 1.5 210.5 2.5 3 VC (V) CURRENT SENSING THRESHOLD (mV) 150 250 200 300

3740 G08

RANGE = VIN RANGE = OPEN RANGE = GND TEMPERATURE (°C) –50 VFB (mV)800 806 808 804 802 810

3740 G09a

25 75 500–25 100 TEMPERATURE (°C) –50 VFB (mV)740 760 750 770

3740 G09b

25 500–25 75 100 TEMPERATURE (°C) –50 0.8 1.1 1.0 0.9 1.2

3740 G10

0.7 0.6 0.5 0.4 25 500–25 75 100 SHDN (V) TEMPERATURE (°C) –50 CONTROLLER FREQUENCY (KHz) 300 315 310 305 320

3740 G11

25 500–25 75 100 (TA = 25°C, unless otherwise noted) XREF Pin Start-Up Load Regulation Current Limit vs Bottom Gate On-Time SS 0.5V/DIV VO 2V/DIV IL 2A/DIV

3740 G04

VIN = 10V , VOUT = 2.5V ILOAD = 3A 2ms/DIV LOAD CURRENT (A) DVOUT (%) –0.3 –0.4 –0.1 –0.2

3740 G05

–0.5 –0.6 –0.7 –0.8 2 4 6 10 RANGE = VIN RANGE = OPEN RANGE = GND VIN = 10V VOUT = 2.5V RS = 12mΩ BOTTOM GATE ON DUTY CYCLE (%) CURRENT SENSING LIMIT (mV) 100 160 140 180 120 200

3740 G06

RANGE = VIN RANGE = OPEN RANGE = GND

Error Amplifi er T ransconductance vs Temperature BIAS-VIN to Enable Controller vs Temperature Undervoltage Lockout Threshold vs Temperature PIN FUNCTIONS SN– (Pin 1): Negative Current Sensing Pin. Connect this pin to the source of the bottom MOSFET for No R SENSE or to a current sense resistor. PGND (Pin 2): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET. BGATE (Pin 3): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET. BGDP (Pin 4): Bottom Gate Drive Power Supply. Connect this pin to a voltage source higher than 7V (VIN or BIAS). SN+ (Pin 5): Positive Current Sensing Pin. Connect this pin to the drain of the bottom MOSFET for No RSENSE or to a current sense resistor. SW (Pin 6): Switch Node. Connect this pin to the source of the top N-channel MOSFET and the drain of the bottom N-channel MOSFET. TGATE (Pin 7): Top Gate Drive. Drives the gate of the top N-channel MOSFET to BIAS. BIAS (Pin 8): Top Gate Drive Power Supply. Connect a capacitor between this pin and V IN. SWB (Pin 9): Switch Pin of the Internal Boost. Connect the boost inductor here. VIN (Pin 10): Input Supply Pin. Must be locally bypassed with a capacitor. RANGE (Pin 11): Current Limit Range Select Pin. Ground this pin for 50mV current sense voltage limit. Leave this pin open for 80mV current sense voltage limit. Connect this pin to V IN for current sense voltage limit of 105mV. PGOOD (Pin 12): Power Good Output. Open collector logic output that is pulled low when the FB voltage lower than 720mV. SHDN (Pin 13): Shutdown Pin. Connect to 2.5V or higher to enable device; 0.5V or less to disable device. Also, this pin functions as soft-start when a voltage ramp is applied. XREF (Pin 14): External Reference Pin. This pin sets the FB voltage externally between 0V and 0.8V. It can be used to slave the output voltage during normal operation or the output start-up behavior to an external signal source. Tie this pin to 1V or higher to use the internal 0.8V reference. FB (Pin 15): Feedback Pin. Pin voltage is regulated to 0.8V if internal reference is used or to the XREF pin if voltage is between 0V and 0.8V. Connect the feedback resistor divider to this pin. TEMPERATURE (°C) –50 ERROR AMP (μs) 340 390 370 380 350 360 400

3740 G12

25 500–25 75 100 TEMPERATURE (°C) –50 BIAS-VIN (V) 7.20 7.45 7.35 7.40 7.25 7.30 7.50

3740 G13

7.15 7.10 7.05 7.00 25 500–25 75 100 TEMPERATURE (°C) –50 UNDERVOL TAGE LOCKOUT VIN (V) 2.0 2.5 1.5 3.0

3740 G14

1.0 0.5 25 500–25 75 100 TYPICAL PERFORMANCE CHARACTERISTICS(TA = 25°C, unless otherwise noted)

1.2MHz OSCILLATOR RAMP GENERATOR VREF 0.80V 300KHz OSCILLATOR RAMP GENERATOR SWITCH LOGIC BIAS VC SHDN XREF FB PGOOD TGATE SW BGDP BGATE PGND SN SN– RANGE Gm SWB gm RQ 0.72V S VIN 7.8V 3740 BD 910 Σ Σ PIN FUNCTIONS VC (Pin 16): Error Amplifi er Compensation Pin. Connect the external compensation RC to this pin. The current comparator threshold increases with the voltage of this pin. Exposed Pad (Pin 17): Ground. Must be soldered to PCB ground.

The L T3740 is a constant-frequency, valley current mode controller for DC/DC step-down converters. At the start of each oscillator cycle, the switch logic is set, which turns on the bottom MOSFET . After a 500ns blanking time, the bottom MOSFET current is sensed and added to a stabilizing ramp, and the resulting sum is fed into the PWM comparator A1. When this voltage goes below the voltage at V C pin, the switch logic is reset, which turns off the bottom MOSFET, and turns on the top MOSFET . The top MOSFET remains on until the next oscillator cycle. The bottom MOSFET current can be determined by sensing the voltage between the drain and source of the MOSFET using the bottom MOSFET on-resistance, or by sensing the voltage drop across a resistor between the source of the bottom MOSFET and ground. The two current sensing pins are SN + and SN–. The gm error amplifi er adjusts the voltage on the VC pin by comparing the feedback signal VFB with the reference, which is determined by the lower of the internal 0.8V reference and the voltage at the XREF pin. If the error amplifi er’s output increases, more current is delivered to the output; if it decreases, less current is delivered. The L T3740 features an open collector PGOOD signal. When the voltage at FB pin is less than 720mV, the PGOOD output is pulled low by a NPN transistor . The 720mV threshold is independent of the voltage on XREF pin. The small internal step-up converter provides a BIAS voltage about 7V higher than the input voltage V IN for the drive of the top MOSFET. This enables the L T3740 to work from an input voltage as low as 2.2V. The controller starts operation when the BIAS pin is about 7V higher than V IN pin. The voltage supply for the bottom MOSFET drive is provided through the BGDP pin. For V IN lower than 7V, BGDP should be connected to BIAS to get enough drive bias. For V IN higher than 7V, BGDP can be connected directly to VIN to reduce power loss. Grounding the SHDN pin turns both the internal step-up converter and the controller off. The SHDN pin can also be used to implement an optional soft-start function. Start-Up and Shutdown During normal operation, when the feedback voltage is above 720mV, the L T3740 operates in forced continuous mode. When the feedback voltage is below 720mV, either during the start-up or because an external reference is applied, a zero current detect comparator is enabled to monitor the on-state bottom MOSFET current. When the current reaches zero, both the top and bottom MOSFETs are turned off, resulting in discontinuous operation. During the time that both top and bottom MOSFETs are off, no current signal is fed into the L T3740. Only the stabilizing ramp is fed into the PWM comparator to decide the next turn on of the top MOSFET. The L T3740 uses the SHDN pin to implement one of the two different startup schemes. As shown in the block diagram, the V C pin is clamped to SHDN pin through a PNP transistor. If the SHDN pin is slowly ramped up, the VC pin will track it up proportionally. As the VC pin voltage is compared to the current signal at comparator A1, this will, in turn, slowly ramp up the switching current. The tracking capability built into XREF can be used to implement another startup scheme. If less than 0.8V is applied to XREF, the L T3740 will use this voltage as the reference for regulation. Slowly ramping up the voltage at XREF forces the output to increase slowly, which limits the start-up current, as shown in Typical Performance Characteristics. A sharp SHDN signal is recommended to shut down the L T3740. If SHDN slowly ramps down, the V C signal will be dragged low for a considerable period of time before SHDN reaches its turn-off threshold. During this period of time, the output voltage could still be in regulation and the circuit operates in forced continuous mode. A low V C voltage will result in large bottom MOSFET on-time, which may cause a reverse inductor current that pumps the energy from the output to the input. If there is another supply at the output or the output has a big capacitor, the input voltage could overshoot, and may cause overvoltage damage to certain devices.

voltage without slope compensation is shown in Table 1. This is the value for high duty cycle operation. Table 1. Current Sensing Thresholds correspond to three compensation slopes. sensing resistance needs to be reduced. and turns off the bottom MOSFET. and maximum current IDS(MAX). on-resistance corresponding to certain gate voltage.

Figure 1. MOSFET RDS(ON) vs. Temperature Figure 1. For a maximum junction temperature of 100°C, 8V to prevent the gate from overvoltage damage. of time that BGDP is below 7V and the circuit is operating.

3740 F01

Figure 2. The Zener diode and the small MOSFET limit the 7V quick enough, this circuit is not necessary. Figure 3 can effectively reduce the noise. Figure 2. Circuit That Prevents Operation for VIN < 7V Figure 3. Noise Reduction for Bottom MOSFET

3740 F02

3740 F03

Choose MOSFET Sensing or Resistor Sensing The L T3740 can use either the bottom MOSFET on- resistance or an external sensing resistor for current sensing. Simplicity and high effi ciency are the benefi ts of using bottom MOSFET on-resistance. However, some MOSFETs have a wide on-resistance variation. As discussed previously, the gate-source voltage and the temperature also affect the MOSFET on-resistance. These factors affect the accuracy of the inductor current limit. The inductor saturation current will need enough margin to cover the current limit variation. In the cases where the input voltage supply has suffi cient current limit, a wide current limit variation of the controller may be tolerated. As the load increases to reach the input supply current limit, the input voltage corrupts, and limits the total power in the circuit. To reduce the current limit variation, a more accurate external sensing resistor can be used between the bottom MOSFET source and ground. Connect SN + and SN– pins to the two terminals of the resistor. Power Dissipation The resulting power dissipation in the MOSFETs are: P TOP = DTOP • IL2 • RDS(ON),TOP P BOT = DBOT • IL2 • RDS(ON),BOT If an external sensing resistor is used, the extra power dissipation in the sensing resistor is: P RS = DBOT • IL2 • Rs The power losses in the bottom MOSFET and external sensing resistor are greatest during an output short-circuit, where maximum inductor current and maximum bottom duty cycle occur. Besides I 2R power loss, there are transition losses and gate drive losses. The transition losses that increase with the input voltage and inductor current are mainly in the top MOSFET. The losses can be estimated with a constant k = 1.7A –1 as: T ransition Loss = k • V IN2 • IL • CRSS • FS The gate drive losses increase with the gate drive power supply voltage, gate voltage and gate capacitance as shown below: P GD,TOP = VBIAS • CGS,TOP • VGS,TOP • FS P GD,BOT = VBGDP • CGS,BOT • VGS,BOT • FS Duty Cycle Limits At the start of each oscillator cycle, the top MOSFET turns off and the bottom MOSFET turns on with a 500ns duty cycle on the top MOSFET. If the maximum duty cycle is reached, due to a dropping input voltage for example, the output voltage will droop out of regulation. Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. The highest effi ciency is obtained with a small ripple current. However, achieving this requires a large inductor. There is a trade off between component size and effi ciency. A reasonable starting point is to choose a ripple current that is about 30% of I OUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specifi ed maximum, the inductance should be chosen according to: L = 1– VOUT VIN(MAX) ⎠⎟  VOUT FS  ΔIL(MAX)

Once the value for L is known, the type of inductor must be selected. High effi ciency converters generally cannot afford the core loss found in low cost powdered iron cores; instead use ferrite, molypermalloy or Kool Mμ ® cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 4 conducts dur- ing the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) effi ciency loss. The diode can be rated for about one half of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. Another important benefi t of the Schottky diode is that it reduces the SW node ringing at switching edges, which reduces the noise in the circuit and also makes the MOSFETs more reliable. C IN and COUT Selection The input capacitance CIN is required to fi lter the square wave current at the drain of the top MOSFET . Use a low ESR capacitor sized to handle the maximum RMS current. IRMS ≈IOUT(MAX)  VOUT VIN  VIN VOUT This formula has a maximum at VIN = 2VOUT, where: IRMS = 1 2 IOUT(MAX) This simple worst-case condition is commonly used for design because even signifi cant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of C OUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ΔV OUT is approximately bounded by: ΔVOUT <Δ lL E S R + 1 8F S COUT Since ΔIL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfi ed, the capacitance is adequate for fi ltering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have signifi cantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coeffi cient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to signifi cant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5μF to 50μF aluminum electrolytic capacitor with an ESR in the range of 0.5Ω to 2Ω.

The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the L T3740, the maximum sense voltage is selected by the RANGE pin. With valley current control, the maximum sense voltage and the sense resistance determine the maxi- mum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSN(MAX) RS + ΔIL The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The maximum sense voltage in- creases as duty cycle decreases. If MOSFET on-resistance is used for current sensing, it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of I LIMIT which heats the MOSFET switches. In the event of output short-circuit to ground, the L T3740 operates at maximum inductor current and minimum duty cycle. The actual inductor discharging voltage is the voltage drop on the parasitic resistors including bottom MOSFET on-resistance, inductor ESR, external sensing resistor if it is used and the actual short-circuit load resistance. Because of the big variation of these parasitic resistances, the top MOSFET on-time can vary considerably for the same input voltage. In the case of high input voltage and low parasitic resistance, pulse-skipping may happen. Effi ciency Considerations The percent effi ciency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the effi ciency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in L T3740 circuits: 1. DC I 2R losses. These arise from the on-resistances of the MOSFETs, external sensing resistor , inductor and PC board traces and cause the effi ciency to drop at high output currents. The average output current fl ows through the inductor , but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same R DS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I 2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. 2. T ransition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is signifi cant at high input voltages and can be estimated from: T ransition Loss = (1.7A –1) • VIN2 • IOUT • CRSS • FS 3. Gate drive loss. The previous formula show the factors of this loss. For the top MOSFET, nothing can be done other than choosing a small C GS MOSFET without sacrifi cing on-resistance. For the bottom MOSFET, the gate drive loss can be reduced by choose the right BGDP voltage supply. 4. C IN loss. The input capacitor has the diffi cult job of fi ltering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I 2R loss and suffi cient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including C OUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve effi ciency, the input current is the best indicator of changes in effi ciency. If a change is made and the input current decreases, then the effi ciency has increased. If there is no change in input current, then there is no change in effi ciency.

by the regulator to return V OUT to its steady-state value. overshoot or ringing that would indicate a stability problem. MOSFET drive and most of the internal controller circuitry. The step-up converter has a current limit of 400mA. category with small size are listed in Table 2. Table 2. Recommended Inductors for Step-Up Converter needs to cover the maximum input current. the inductance should not be less than 10μH at 400mA. the output of the L T3740 step-up converter. Table 3. Recommended Ceramic Capacitor Manufacturers

Selecting a standard value of 2.0μH results in a ripple current of: ΔIL = 2.5V (300kHz)(2μH) 1 – 2.5V 15V ⎠⎟ = 3.47A Set Range = V IN. At minimum input voltage V IN = 7V, the maximum current sensing voltage is 145mV. Use an external sensing resistor of 12mΩ. The inductor current valley will be clamped to 12A. The ripple current at V IN = 7V is 2.68A, there is about 33% of margin for the 10A load current to cover the maximum current sensing voltage variation. For the case of using MOSFET on-resistance for current sensing, choosing a Si4840 (R DS(ON) = 0.008Ω (NOM) 0.0095Ω (MAX) for V GS = 7V, θJA = 40°C/W) yields a nominal sense voltage of: V SN(NOM) = (10A)(1.3)(0.0095Ω) =123mV To check if the current limit is acceptable, assume a junc- tion temperature of about 55°C above a 70°C ambient with ρ 125°C = 1.5: ILIMIT = 145mV 1.5  0.0095Ω + 2.68A 2 = 11.5A Double check the assumed TJ in the MOSFET at VIN = 7V with maximum load current: P BOT = DBOT • IL2 • RDS(ON), BOT PBOT = 1– 2.5V ⎠⎟ 1 0 A() Double check the assumed TJ in the MOSFET : The power dissipation in the bottom MOSFET increases with input voltage. For VIN = 20V, PBOT = 1– 2.5V 20V ⎠⎟ 1 0 A() Double check the assumed TJ in the MOSFET : Choose a Si4840 (CRSS = 200pF) for the top MOSFET and check its power dissipation at maximum load current with ρ 100°C = 1.3: PTOP = 2.5V 20V 1 0 A() 10A  200pF  300kHz= 0.15W + 0.41W= 0.56W This analysis shows that careful attention to heat sinking will be necessary in this circuit. Check the reverse current comparator margin. The maxi- mum ripple current happens at maximum input voltage: ΔIL(MAX) = 2.5V 300kHz  2μH 1 – 2.5V 20V ⎠⎟ = 3.65A At no load, the maximum reverse current voltage is: RS  ΔIL(MAX) 2 = 12mΩ  3.65A 2 = 22mV

minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 4. Figure 4. Design Example: 2.5V/10A Output

3740 F04

PC Board Layout Considerations As with all switching regulators, careful attention must be paid to the PCB board layout and component placement. ■ Place the power components close together with short and wide interconnecting trances. The power components consist of the top and bottom MOSFETs, the inductor, C IN and COUT. One way to approach this is to simply place them on the board fi rst. ■ Similar attention should be paid to the power components that make up the boost converter. They should also be placed close together with short and wide traces. ■ Always use a ground plane under the switching regulator to minimize interplane coupling. ■ Minimize the parasitic inductance in the loop of CIN, MOSFETs and D1 which carries large switching current. ■ Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI low. ■ Use planes for V IN and VOUT to maintain good voltage fi ltering and to keep power losses low. Unused areas can be fi lled with copper and connect to any DC node IN, VOUT, GND) ■ Place C B close to BIAS pin and input capacitor. ■ Keep the high dv/dt nodes (SW , TG, BG, SWB) away from sensitive small signal nodes.

High Effi ciency Step-Down Converter Effi ciency vs Load Current SWB VIN SHDN XREF RANGE VC BGDP BIAS TGATE SW SN+ BGATE GND L T3740 SN– PGND FB

3740 TA02a

3.4μH 1μF 0.47μF VOUT 3.3V 10A VIN 7V to 20V HAT2168H HAT2165H 100μF s 3 20μF 22pF 22μH 16k 15k 10k 1500pF 22pF 80.6k 255k B340A1Ω LOAD CURRENT (A) EFFICIENCY (%)

3740 TA02b

VIN = 7V VIN = 15V VIN = 20V VOUT = 3.3V

2.5V/10A TYPICAL APPLICATIONS EFFICIENCY SWB VIN SHDN XREF RANGE VC BGDP BIAS TGATE SW SN+ BGATE GND L T3740 SN– PGND FB

3740 TA03a

1.05μH 1μF 1μF VOUT 2.5V VIN 4V to 15V HAT2168H HAT2165H 100μF s 3 22μF s 2 47pF 22μH 7.5k 10k 10k 680pF 22pF 46.4k 100k 5.1k B340A1Ω LOAD CURRENT (A) EFFICIENCY (%)86

3740 TA03b

VIN = 4V VIN = 15V VOUT = 2.5V

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 16-Lead Plastic DFN (5mm × 3mm) (Reference L TC DWG # 05-08-1706) 3.00 p0.10 (2 SIDES) 5.00 p0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 p 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 p 0.10 (2 SIDES) 0.75 p0.05 R = 0.115 TYP R = 0.20 TYP 4.40 p0.10 (2 SIDES) 169 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DHC16) DFN 110 0.25 p0.05 PIN 1 NOTCH

0.50 BSC

4.40 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 p0.05 (2 SIDES)2.20 p0.05 0.65 p0.05 3.50 p0.05 PACKAGE OUTLINE 0.25 p 0.05

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2006 LT 0908 REV C • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L TC1778 No R SENSE, Step-Down Synchronous DC/DC Controller V IN: 4V to 36V, Fast T ransient Responds, Current Mode, IOUT ≤ 20A L TC1876 2-Phase, Dual Synchronous Step-Down Switching Controller Current Mode; 20A per Channel L T3430/L T3431 Monolithic 3A, 200kHz/500kHz Step-Down Switching Regulator V IN: 5.5V to 60V, 0.1Ω Saturation Switch, 16-Lead SSOP Package L TC3708 No R SENSE, Dual, 2-Phase, Synchronous DC/DC Controller V IN: 4V to 36V, Current Mode, Up/Down T racking, Synchronizable L TC3728L Dual, 2-Phase Synchronous Step-Down Controller V IN: 4V to 36V, 550kHz, PLL: 250kHz to 550kHz L TC3778 Wide Operating Range, No R SENSE Step-Down Controller Single Channel, Separate V ON Programming L TC3824 High Voltage, Wide Input Range, Step-Down Controller With Low I Q V IN: 4V to 60V, IQ = 40μA, 100% Duty Cycle, 2A P-Channel Gate Drive, 10-Pin MSOP High Effi ciency Step-Down Converter SWB VIN SHDN XREF RANGE VC BGDP BIAS TGATE SW SN+ BGATE GND L T3740 SN– PGND FB

3740 TA04

3.4μH 1μF 0.47μF VOUT 3.3V 10A VIN 7V to 20V HAT2168H HAT2165H 100μF s 3 20μF 22pF 22μH 16k 15k 10k 1500pF 22pF 80.6k 255k B340A