3513

LT3513 LINER

Document overview

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Technical content

APPLICATIONS

The L T®3513 5-output adjustable switching regulator provides power for large TFT-LCD panels. The 38-pin 5mm × 7mm QFN device can generate a 3.3V or 5V logic supply along with the triple output supply required for the TFT-LCD panel. A lower voltage secondary logic supply may also be generated with the addition of an external NPN driven by the internal linear regulator . A step-down regulator provides a low voltage output, V LOGIC, with up to 1.2A of current while capable of operating from a wide input range of 4.5V to 30V . A high power step-up con- verter , a lower power step-up converter and an inverting converter provide the three independent output voltages: AV DD, VON and VOFF required by the LCD panel. A high-side PNP provides delayed turn-on of the VON signal and can handle up to 30mA. Protection circuitry ensures that VON is disabled if any of the four outputs are more than 10% below the programmed voltage. n Automotive TFT-LCD Displays n Large TFT-LCD Desktop Monitors n Flat Panel Televisions n 4.5V to 30V Input Voltage Range n Four Integrated Switches: 2.2A Buck, 1.5A Boost, 0.25A Boost, 0.25A Inverter (Guaranteed Minimum Current Limit) n External NPN LDO Driver n Fixed Frequency, Low Noise Outputs n Inductor Current Sense for Buck n Soft-Start for All Outputs n Externally Programmable VON Delay n Three Integrated Schottky Diodes n PGOOD Pin for AVDD Output Disconnect n PanelProtect TM Circuitry Disables VON Upon Fault n Thermally Enhanced 38-Lead 5mm × 7mm QFN Package Start-Up Waveforms AVDD 10V/DIV RUN/SS 2V/DIV VLOGIC 5V/DIV IIN(AVG) 1A/DIV VOFF 10V/DIV VE3 20V/DIV VON 20V/DIV 5ms/DIV

3513 TA01b

L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. PanelProtect is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. VC1 7.5k 4.7k 2.7nF 4.7nF 10μF VLDO 3.3V 0.5A VLOGIC 0.5A VOFF –10V 20mA VIN 8V TO 16V 22μF 4.7μH 0.22μF 47nF 15nF 15nF 15nF VON 22V 20mA 2.2μF VC3 30k 165k 232k 10k 1.5nF VC2VC1 GND 13k 2.2nF VC4 VIN VLOGIC LDOPWR L T3513 UVLO SW2 2.2μF FB5 FB3 BD FB1 SENSE– SENSE+ SW1 BOOST BIAS SW3 6.8μH 42.2k 10k 30.1k 10k 69.8k 10μH 0.47μF 10k 60.4k 178k 53.6k 100k 10k 10μF 10μH AVDD 80mA 10μF 0.47μF NFB4 SW4 RUN-SS3/4 C T RUN-SS2 RUN-SS1 VONSINK VON VON_CLK VON_CLK PGOOD FB2 VLOGIC

ELECTRICAL CHARACTERISTICS

(Note 1) V SENSE C V Operating Temperature Range (Note 2).. –40°C to 125°C The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , BIAS = 3V , unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage l 4.5 V Quiescent Current Not Switching VRUNSS1 = 0V 7.5 mA μA RUN-SS1, RUN-SS2, RUN-SS3/4 Pin Current RUN-SS1= RUN-SS2 = RUN-SS3 = RUN-SS4 = 0.4V 2μ A RUN-SS1, RUN-SS2, RUN-SS3/4 Threshold 0.8 V BIAS Pin Voltage to Begin RUN-SS2, RUN-SS3/4 l 2.25 2.7 V BIAS Pin Current BIAS = 3.1V , All Switches Off 16.5 20 mA PIN CONFIGURATION 13 14 15 16 TOP VIEW UHF PACKAGE 38-LEAD (5mm s 7mm) PLASTIC QFN 17 18 19 38 37 36 35 34 33 32

1 FB5

V RUN-SS3/4 FB3 RUN-SS2 SW3 VON VONSINK VON_CLK PGOOD VC3 SENSE+ SENSE– BIAS BOOST LDOPWR BD SW4 NFB4 RUN-SS1 V VC2 UVLO V IN VIN SW1 SW1 GND FB1 C T GND SW2 SW2 GND BIAS FB2 TJMAX = 125°C, θJA = 34°C/W , θJC = 1°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L T3513EUHF#PBF L T3513EUHF#TRPBF 3513 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C L T3513IUHF#PBF L T3513IUHF#TRPBF 3513 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ ABSOLUTE MAXIMUM RATINGS

PARAMETER CONDITIONS MIN TYP MAX UNITS FB Threshold Offset to Begin CT Charge (Note 3) 90 125 160 mV CT Pin Current Source All FB Pins = 1.5V 16 20 25 μA CT Threshold to Power VON All FB Pins = 1.5V 1 1.1 1.2 V VON Switch Drop V ON Current = 30mA 200 400 mV Maximum VON Current V E3 = 30V l 30 50 mA VON_CLK Input Voltage High 1.5 V VON_CLK Input Voltage Low 0.3 V VONSINK Voltage On V ONSINK Current = 1μA ● 1.2 V Master Oscillator Frequency 1.90 1.80 2 2.12 2.22 MHz MHz Foldback Switching Frequency All FB = 0V 200 kHz UVLO Pin Threshold UVLO Pin Voltage Rising 1.25 V UVLO Pin Hysteresis Current V UVLO = 1V 3.4 3.9 4.4 μA PGOOD Threshold Offset 90 125 160 mV PGOOD Sink Current PGOOD Connected to 40V Through 100k 4 mA PGOOD Pin Leakage V PGOOD = 40V 1 μA Switch 1 (2.2A Buck) FB1 Voltage 1.215 1.205 1.235 1.255 1.265 V V FB1 Voltage Line Regulation 4.5V < V IN < 32V 0.01 0.03 %/V FB1 Pin Bias Current (Note 4) ● 30 200 nA Error Amplifi er 1 Voltage Gain 250 V/V Error Amplifi er 1 T ransconductance ΔI = 10μA 220 μmhos Maximum Duty Cycle ● 75 85 % Switch 1 Current Limit Duty Cycle = 35% (Note 5) 2.2 3 3.5 A Switch 1 VCESAT ISW = 1.5A 430 mV Switch 1 Leakage Current FB1 = 1.5V 0.1 10 μA Minimum BOOST Voltage Above SW1 Pin I SW = 1.5A (Note 6) 1.8 2.5 V BOOST Pin Current I SW = 1.5A 30 50 mA BOOST Schottky Diode Drop I = 170mA 700 mV Switch 2 (1.5A BOOST) FB2 Voltage 1.20 1.19 1.22 1.24 1.25 V V FB2 Voltage Line Regulation 4.5V < V IN < 32V 0.01 0.03 %/V FB2 Pin Bias Current (Note 4) ● 30 200 nA Error Amplifi er 2 Voltage Gain 250 V/V Error Amplifi er 2 T ransconductance ΔI = 10μA 220 μmhos Switch 2 Current Limit 1.5 1.85 2.3 A Switch 2 VCESAT ISW2 = 1.2A 360 mV Switch 2 Leakage Current FB2 = 1.5V 0.1 1 μA BIAS Pin Current Due to SW2 I SW2 = 1.2A 45 mA Maximum Duty Cycle (SW2) ● 75 90 % The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , BIAS = 3V , unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS Switch 3 (250mA BOOST) FB3 Voltage 1.20 1.19 1.22 1.24 1.25 V V FB3 Voltage Line Regulation 4.5V < V IN < 32V 0.01 0.03 %/V FB3 Pin Bias Current (Note 4) ● 30 200 nA Error Amplifi er 3 Voltage Gain 250 V/V Error Amplifi er 3 T ransconductance ΔI = 10μA 220 μmhos Switch 3 Current Limit 0.25 0.3 0.38 A Switch 3 VCESAT ISW3 = 0.2A 200 mV Switch 3 Leakage Current FB3 = 1.5V 0.1 1 μA BIAS Pin Current Due to SW3 I SW3 = 0.2A 18 mA Maximum Duty Cycle (SW3) ● 84 88 % Schottky Diode Drop I = 170mA 900 mV Switch 4 (250mA Inverter) NFB4 Voltage –1.205 –1.215 –1.180 –1.155 –1.145 V V NFB4 Voltage Line Regulation 4.5V < V IN < 32V 0.01 0.03 %/V NFB4 Pin Bias Current (Note 4) ● 51 6 μ A Error Amplifi er 4 Voltage Gain 200 V/V Error Amplifi er 4 T ransconductance ΔI = 10μA 220 μmhos Switch 4 Current Limit 0.28 0.3 0.40 A Switch 4 VCESAT ISW4 = 0.2A 200 mV Switch 4 Leakage Current NFB4 = –1.5V 0.1 1 μA BIAS Pin Current Due to SW4 I SW4 = 0.2A 18 mA Maximum Duty Cycle (SW4) 84 88 % Schottky Diode Drop (D4) I = 170mA 700 mV NPN LDO FB5 Voltage 0.61 0.6 0.625 0.63 0.65 V V Base Drive Current FB5 = 0.5V 6 8 10 mA LDOPWR Minimum Voltage BD = 3.5V 4.5 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T3513E is guaranteed to meet specifi ed performance from 0°C to 125°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L T3513I is guarenteed over the full –40°C to 125°C operating junction temperature range. Note 3: The C T pin is held low until FB1, FB2, FB3 and NFB4 all ramp above the FB threshold offset. Note 4: Current fl ows out of FB1, FB2, FB3 and NFB4. Note 5: Current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature range when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , BIAS = 3V , unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS Maximum Output Current for VLOGIC = 3.3V SW1 Current Limit vs Duty Cycle Start and Run VLOGIC = 3.3V BOOST Pin Current SW2 Current Limit SW3 Current Limit SW4 Current Limit SW1 V CESAT SW2 VCESAT VIN (V) 2.0 2.2 2.6

3513 G01

1.8 1.6 51 0 2 0 1.4 1.2 2.4 IOUT(MAX) (A) L = 2.4μH L = 4.3μH DUTY CYCLE (%) SW1 CURRENT LIMIT (A) 0.5 1.0 1.5 2.0 2.5 3.0 35 45 55 65

3513 G02

LOAD CURRENT (A) 0.001 VIN (V) 0.01 0.1 1

3513 G03

VIN(MIN) START VIN(MIN) RUN SWITCH CURRENT (mA) 1500 2500

3513 G04

BOOST CURRENT (mA) AMBIENT TEMPERATURE (°C) –40 1.5 SW CURRENT LIMIT (A) 1.6 1.8 1.9 2.0 2.5 2.2 10 60 85

3513 G05

1.7 2.3 2.4 2.1 –15 35 110 AMBIENT TEMPERATURE (°C) –50 SW CURRENT LIMIT (mA) 300 350 400 110

3513 G06

–10 30 70–30 10 50 90 150 500 450 AMBIENT TEMPERATURE (°C) –50 SW CURRENT LIMIT (mA) 300 350 400 110

3513 G07

–10 30 70–30 10 50 90 150 500 450 SW1 CURRENT (mA) VCESAT (mV) 200 400 600 500 1000 1500 2000

3513 G08

ISW2 (mA) VCE2SAT (mV) 200 400 600 100 300 500 400 800 1200 1600

3513 G09

TA = 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS SW3 VCESAT SW4 VCESAT VON Current Limit Oscillator Frequency Frequency Foldback Reference Voltage BIAS Pin Current Effi ciency, AVDD = 13V Effi ciency, VLOGIC = 5V ISW3 (mA) VCE3SAT (mV) 200 250 300 150 250

3513 G10

ISW (mA) 200 250 350 150 250

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300VCESAT (mV) VE3 (V) ION LIMIT (mA)

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AMBIENT TEMPERATURE (°C) –50 FREQUENCY (MHz) 2.1 2.2 2.3

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2.0 1.9 1.7 0 50 100 1.8 2.5 2.4 VFB (mV) SWITCHING FREQUENCY (kHz) 1500 2000 2500 450 750 1200

3513 G14

TEMPERATURE (°C) –40 –15

1.20 REFERENCE VOLTAGE (V)

1.22 1.25 10 60 85

3513 G15

1.21 1.24 1.23 35 110 TEMPERATURE (°C) –50 BIAS CURRENT (mA) 0 50 100 150

3513 G16

L2 = 10μH L3 = 10μH L4 = 10μHISW2 = 0A ISW3 = 0A ISW4 = 0A LOAD CURRENT (mA) EFFICIENCY (%) 100 100 200 300 400

3513 G17

IOUT (mA) 100 EFFICIENCY (%) 100 700 1100

3513 G18

TA = 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS LDO Current Limit vs Temperature VUVLO vs Temperature FB5 (Pin 1): Feedback Pin. Tie the resistor tap to this pin and set the output of the LDO according to VLDO = 0.625 • (1 + R14/R15). Reference designators refer to Figure 1. VC1 (Pin 2): Control Voltage and Compensation Pin for Internal Error Amplifi er . Connect a series RC from this pin to ground to compensate switching regulator 1. RUN-SS3/4 (Pin 3): Run/Soft-Start Pin. This is the soft- start pin for switching regulators 3 and 4. Place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. When the BIAS pin reaches 2.8V , a 2μA current source charges the capacitor . When the voltage at this pin reaches 0.8V , switches 3 and 4 turn on and begin switching. For slower start-up use a larger capacitor . For complete shutdown tie RUN-SS3/4 to ground. FB3 (Pin 4): Feedback Pin. Tie the resistor tap to this pin and set V ON according to VON = 1.23V • (1 + R8/R9) – 150mV . Reference designators refer to Figure 1. RUN-SS2 (Pin 5): Run/Soft-Start Pin. This is the soft-start pin for switching regulator 2. Place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. When the BIAS pin reaches 2.25V , a 2μA cur- rent source charges the capacitor . When the voltage at this pin reaches 0.8V , switch 2 turns on and begins switching. For slower start-up use a larger capacitor . For complete shutdown tie RUN-SS2 to ground. SW3 (Pin 6): Switch Node. The SW3 pin is the collector of the internal NPN bipolar transistor for switching regulator 3. Minimize trace area at this pin to keep EMI down. E3 (Pin 7): This is switching regulator 3’s output and the emitter of the output disconnect PNP. Tie the output capacitor and resistor divider here. V ON (Pin 8): This is the delayed output for switching regulator 3. VON reaches its programmed voltage after the internal CT timer times out. Protection circuitry ensures VON is disabled if any of the four outputs are more than 10% below normal voltage. This output is also disabled when V ON_CLK is high. VONSINK (Pin 9): This is an open-collector output con- trolled by the V ON_CLK pin. When V ON_CLK is low, this pin draws no current and when VON_CLK is high, this pin draws current. VON_CLK (Pin 10): This pin controls the output disconnect device and the open collector of VONSINK. When this pin is low, the VON pin is enabled and the VONSINK pin is a high impedance. When this pin is high, the VON pin is disabled and the VONSINK pin sinks current to ground. Reference Voltage for FB5, LDO AMBIENT TEMPERATURE (°C) –50 BASE CURRENT LIMIT OF INTERNAL PNP (mA)

3513 G19

0–25 75 10025 125 AMBIENT TEMPERATURE (oC) –50 1.30 1.31 1.33 100

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1.29 1.28 05 0 1.27 1.26 1.32UVLO (V) UVLO FOR START UVLO MINIMUM FOR RUN TEMPERATURE (°C) –40 640 650 670 35 85

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–15 10 60 110 610 600 660REFERENCE VOLTAGE (mV) TA = 25°C, unless otherwise noted.

PGOOD (Pin 11): Power Good Comparator Output. This is the open collector output of the power good comparator and can be used in conjunction with an external P-chan- nel MOSFET to provide output disconnect for AV DD as shown in Figure 2. When switcher 2’s output reaches approximately 90% of its programmed voltage, PGOOD will be pulled to ground. This will pull down on the gate of the MOSFET , connecting AV DD. A 100k pull-up resistor between the source and the gate of the P-channel MOSFET keeps it off when switcher 2’s output is low. V C3 (Pin 12): Control Voltage and Compensation Pin for Internal Error Amplifi er . Connect a series RC from this pin to ground to compensate switching regulator 3. CT (Pin 13): Timing Capacitor Pin. This is the input to the VON timer and programs the time delay from all four feedback pins reaching 1.125V to VON turning on. The CT capacitor value can be set using the equation C = (20μA

• t DELAY)/1.1V . GND (Pins 14, 17, 33): Ground. SW2 (Pins 15, 16): Switch Node. The SW2 pin is the col- lector of the internal NPN bipolar transistor for switching regulator 2. Minimize trace area at this pin to keep EMI down. BIAS (Pins 18, 29): The BIAS pin is used to improve ef- fi ciency when operating at higher input voltages. Connect- ing this pin to the output of switching regulator 1 forces most of the internal circuitry to draw its operating current from V LOGIC rather than VIN. The drivers of switches 2, 3, 4 and 5 are supplied by BIAS. Switches 2, 3, 4 and 5 will not switch until the BIAS pin reaches approximately 2.7V . Both BIAS pins must be tied to V LOGIC. FB2 (Pin 19): Feedback Pin. Tie the resistor divider tap to this pin and set AV DD according to AV DD = 1.23V • (1 + R5/R6). Reference designators refer to Figure 2. VC2 (Pin 20): Control Voltage and Compensation Pin for Internal Error Amplifi er . Connect a series RC from this pin to ground to compensate switching regulator 2. VC4 (Pin 21): Control Voltage and Compensation Pin for Internal Error Amplifi er . Connect a series RC from this pin to ground to compensate switching regulator 4. RUN-SS1 (Pin 22): Run/Soft-Start Pin. This is the soft-start pin for switching regulator 1. Place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. When power is applied to the V IN pin, a 2μA current source charges the capacitor . When the voltage at this pin reaches 0.8V , switch 1 turns on and begins switching. For slower start-up use a larger capacitor . For complete shutdown tie RUN-SS1 to ground. NFB4 (Pin 23): Negative Feedback Pin. Tie the resistor di- vider tap to this pin and set V OFF according to VOFF = –1.18 • (1 + R3/R4). Reference designators refer to Figure 2. D4 (Pin 24): Internal Schottky Diode Pin. This pin is the anode of an internal Schottky diode with the other end connected to ground. This Schottky diode is used in generating the V OFF output. SW4 (Pin 25): Switch Node. The SW4 pin is the collector of the internal NPN bipolar transistor for switching regulator 4. Minimize trace area at this pin to keep EMI down. BD (Note 26): NPN LDO Base Drive. This pin controls the base of the external NPN LDO transistor . LDOPWR (Pin 27): Input Voltage for LDO Driver . This pin supplies the current for the NPN LDO base. This pin can be connected to V IN. To save power at high VIN voltages, the pin can alternatively be connected to the AVDD supply. BOOST (Pin 28): The BOOST pin is used to provide a drive voltage higher than VIN to the switch 1 drive circuit. An internal Schottky diode is connected between BIAS and BOOST . A capacitor needs to be connected between BOOST and SW1. SENSE – (Pin 30) Negative Current Sense Input. This pin (along with the SENSE+ pin) is used to sense the inductor current for the buck switching regulator . PIN FUNCTIONS

SENSE+ (Pin 31) Positive Current Sense Input. This pin (along with the SENSE– pin) is used to sense the inductor current for the buck switching regulator . FB1 (Pin 32): Feedback Pin. Tie the resistor divider tap to this pin and set V LOGIC according to VLOGIC = 1.23V • (1 + R1/R2). Reference designators refer to Figure 2. SW1 (Pins 34, 35): Switch Node. The SW1 pins are the emitter of the internal NPN bipolar power transistor for switching regulator 1. These points must be tied together for proper operation. Connect these pins to the inductor , catch diode and boost capacitor . V IN (Pins 36, 37): Input Voltage. This pin supplies current to the internal circuitry of the L T3513. This pin must be locally bypassed with a capacitor . UVLO (Pin 38): Undervoltage Lockout. A resistor divider connected to V IN is tied to this pin to program the minimum input voltage at which the L T3513 will operate. This pin is compared to the internal 1.25V reference. When UVLO is less than 1.25V , the switching regulators are not allowed to operate (the RUN/SS pins are still used to turn on each switching regulator). When this pin falls below 1.25V , 3.9μA will be pulled from the pin to provide programmable hysteresis for UVLO. Exposed Pad (Pin 39): Ground. The Exposed Pad of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The Exposed Pad must be soldered to the circuit board for proper operation. PIN FUNCTIONS

1.23V gm 1.18V 1.234V 1.1V 1.234V R DRIVER BIAS VC3 SW3 VONSINK VON_CLK VON_CLK

3513 F01

R DRIVER BIAS VC4 23NFB4100k100k SW4 FOLDBACK OSCILLATOR 1.1V FB2 SQ R DRIVER VC2 30SENSE– SENSE+ SW2 15, 16 BIAS 18, 29 FOLDBACK OSCILLATOR gm gm SQ R DRIVER BIAS CURRENT SENSE AMP VC1 SW1 34, 35 BOOST VINSLOPE COMP/ ONE-SHOT gm gm CT RUN-SS1 RUN-SS3/4 BIAS

38 UVLO

11 PGOOD

UVLO1.25V 3μA

19 FB2

32 FB1

14,17,33 VIN 36,37 2.7V+ 1.1V VON_CLK SW3 LOCKOUT INTERNAL REGULATOR AND REFERENCE MASTER OSCILLATOR 2MHz RUN-SS2 FB3 VON SW2 LOCKOUT 0.625V Figure 1 BLOCK DIAGRAM

8mA of current to the base of an external NPN transistor . clock signals, one for each of the switching regulators. source will charge the external capacitor tied to the CT pin. cycle-by-cycle current limit. Figure 2. L T3513 Power-Up Sequence. (T races from Both Photos

3513 F02a

3513 F02b

All four switchers employ a constant-frequency current mode control scheme. Switcher 1, the step-down regula- tor , differs slightly from the others with inductor current sense. Instead of monitoring the current at the switch, current nodes are used to measure the current through the inductor . Inductor current sense does not suffer from minimum on-time problems, therefore always keep- ing the switch current limited with any input-to-output voltage ratio. Switcher 1 is always synchronized to the master oscillator . The other three switchers each have their own slave oscillator . The slave oscillator reduces the frequency when the feedback voltage dips below 0.75V and decreases linearly below the threshold as shown in the Performance Characteristics’ Frequency Foldback plot. Other than these two differences, the control loop is similar in all four switchers. A pulse from the master oscillator for switcher 1 or a pulse from the slave oscillator for the other three switchers sets the RS latch and turns on the internal NPN bipolar power switch. Current in the switch and the external inductor begins to increase. When this current exceeds a level determined by the voltage at V C, the current comparator resets the latch, turning off the switch. The current in the inductor fl ows through the Schottky diode and begins to decrease. The cycle begins again at the next pulse from the oscillator . In this way, the voltage on the V C pin controls the current through the inductor to the output. The internal error amplifi er regulates the output by continually adjusting the VC pin voltage. The threshold for switching on the V C pin is 0.8V , and an active clamp of 1.8V limits the V C voltage. Switchers 2, 3 and 4 also contain an independent current limit not dependent on VC or duty cycle. Switcher 1’s current limit is controlled by the V C voltage and varies with duty cycle. All four switch- ers also use slope compensation to ensure stability with the current mode scheme at duty cycles above 50%. The RUN-SS1, RUN-SS2 and RUN-SS3/4 pins control the rate of rise of the feedback pins. The switch driver for SW1 operates either from V IN or from the BOOST pin. An external capacitor and an integrated Schottky diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to saturate the internal bipolar NPN power switch for effi cient operation. INPUT VOL TAGE RANGE STEP-DOWN CONSIDERATION The minimum operating voltage of switcher 1 is determined either by the L T3513’s undervoltage lockout of ~4V or by its maximum duty cycle. A user defi ned undervoltage lockout may be set with the UVLO pin at a voltage higher than the internal undervoltage lockout. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC VV VV V OUT F IN SW F = + where VF is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.3V at maximum load). This leads to a minimum input voltage of: V VV DC V VIN MIN OUT F MAX F SW () –= + with DCMAX = 0.75. The user defi ned undervoltage is set by a resistor divider connected to the UVLO pin. The comparator pulls 3μA from the pin when the UVLO pin is higher than 1.25V . The hysteresis and minimum input voltage equations are as follows: VR k µ A VV RR R HYS IN MIN =+() = + 22 3 9 12 5 12 .() UVLO 3513 A1 VIN OPERATION

lists several vendors and types that are suitable. Table 1. Inductor Vendors inductors and choose one to meet cost or space goals.

tradeoffs in output ripple and transient performance. the presence of output capacitor series resistance (ESR). and small circuit size, are therefore an option. where ΔIL is the peak-to-peak ripple current in the inductor . age and at temperature extremes. and X5R types. Electrolytic capacitors are also an option. Table 2. Low ESR Surface Mount Capacitors reverse voltage is equal to the regulator input voltage.

Table 3. Schottky Diodes to start as a function of input voltage for a 3.3V output. a load to the switcher that will allow it to start. R4 should be 10k or less to avoid bias current errors.

1. The NFB4 pin works just as the other FB pins. Choose

R5 should be 2.5kΩ or less to avoid bias current errors. regulator is 75% for SW2, and 84% for SW3 and SW4. cycle, as calculated above, is greater than the maximum. so that the actual duty cycle is reduced.

Table 1 lists several inductor vendors and types that are suitable to use with the L T3513. Consult each manufacturer for detailed information and for their entire selection of related parts. Use ferrite core inductors to obtain the best effi ciency, as core losses at frequencies above 1MHz are much lower for ferrite cores than for powdered-iron units. A 10μH to 22μH inductor will be the best choice for most L T3513 step-up and charge pump designs. Choose an inductor that can carry the entire switch current without saturating. For inverting and SEPIC regulators, a coupled inductor , or two separate inductors is an option. When using coupled inductors, choose one that can handle at least the switch current without saturating. If using uncoupled inductors, each inductor need only handle ap- proximately one-half of the total switch current. A 4.7μH to 15μH coupled inductor or two 10μH to 22μH uncoupled inductors will usually be the best choice for most L T3513 inverting and SEPIC designs. Output Capacitor Selection Use low ESR (equivalent series resistance) capacitors at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small pack- ages. X7R dielectrics are preferred, followed by X5R, as these materials retain their capacitance over wide voltage and temperature ranges. A 10μF to 22μF output capaci- tor is suffi cient for most L T3513 applications. Even less capacitance is required for outputs with |V OUT| > 20V or |IOUT| < 100mA. Solid tantalum or OS-CON capacitors will also work, but they will occupy more board area and will have a higher ESR than a ceramic capacitor . Always use a capacitor with a suffi cient voltage rating. Diode Selection A Schottky diode is recommended for use with the L T3513 switcher 2 and switcher 4. The Schottky diode for switcher 3 is integrated inside the L T3513. Choose diodes for switcher 2 and switcher 4 rated to handle an average current greater than the load current and rated to handle the maximum diode voltage. The average diode current in the step-up and SEPIC is equal to the load current. Each of the two diodes in the charge pump confi gurations carries an average diode current equal to the load current. The ground connected diode in the charge pump is integrated into the L T3513. The maximum diode voltage in the step- up and charge pump confi gurations is equal to |V OUT|. The maximum diode voltage in the SEPIC and inverting confi gurations is V IN + |VOUT|. Input Capacitor Selection Bypass the input of the L T3513 circuit with a 4.7μF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type will work if there is additional bypassing provided by bulk electrolytic capacitors or if the input source impedance is low. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input sup- ply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the L T3513 input and to force this switching current into a tight local loop, minimizing EMI. The input capaci- tor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. The input capacitor RMS current can be calculated from the step-down output voltage and current, and the input voltage: CI VV V V I IN RMS OUT OUT IN OUT IN OUT = () < 2 and is largest when V IN = 2VOUT (50% duty cycle). The ripple current contribution from the other channels will be minimal. Considering that the maximum load current from switcher 1 is ~3A, RMS ripple current will always be less than 1.5A. The high frequency of the L T3513 reduces the energy storage requirements of the input capacitor , so that the capacitance required is less than 10μF . The com- bination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors makes OPERATION

them the preferred choice. The low ESR results in very low voltage ripple. Ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. Use X5R and X7R types. An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor , for example a 1μF ceramic capacitor in parallel with a low ESR tantalum capacitor . For the electrolytic capacitor , a value larger than 10μF will be required to meet the ESR and ripple current requirements. Because the input capacitor is likely to see high surge currents when the input source is applied, only consider a tantalum capacitor if it has the appropriate surge current rating. The manufacturer may also recommend operation below the rated voltage of the capacitor . Be sure to place the 1μF ceramic as close as possible to the V IN and GND pins on the IC for optimal noise immunity. A fi nal caution is in order regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the L T3513. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor (an electrolytic) in parallel with the ceramic capacitor . For details, see Ap- plication Note 88. Soft-Start and Shutdown The RUN-SS1(Run/Soft-Start) pin is used to place the switching regulators and the internal bias circuits in shutdown mode. It also provides a soft-start function, along with RUN-SS2 and RUN-SS3/4. If the RUN-SS1 pin is pulled to ground, the L T3513 enters its shutdown mode with all regulators off and quiescent current reduced to ~30μA. An internal 2μA current source pulls up on the RUN-SS1, RUN-SS2, and RUN-SS3/4 pins. If the RUN-SS1 pin reaches ~0.6V , the internal bias circuits start and the quiescent currents increase to their nominal levels. If a capacitor is tied from the RUN-SS1, RUN-SS2 or RUN-SS3/4 pins to ground, then the internal pull-up current will generate a voltage ramp on these pins. This voltage clamps the V C pin, limiting the peak switch current and therefore input current during start-up. The RUN-SS1 pin clamps V C1, the RUN-SS2 pin clamps V C1 and the RUN-SS3/4 pin clamps the VC3 and VC4 pins. A good value for the soft-start capacitors is COUT/10,000, where COUT is the value of the largest output capacitor . VON Pin Considerations The VON pin is the delayed output for switching regulator 3. When the CT pin reaches 1.1V , the output disconnect PNP turns on, connecting V ON to E3. The V ON pin is current limited and will protect the L T3513 and input source from a shorted output. The V ON pin output is also controlled from the V ON_CLK pin. When VON_CLK is low, the VON output will turn on if the CT pin is greater than 1.1V . When VON_CLK is high, greater than 1.5V , the VON output is disabled and the VONSINK open collector device turns on. If the VONSINK pin is connected to VON through a resistor , the VON voltage will decay with a high VON_CLK. VON_CLK may be synced to the horizontal scanning frequency to improve LCD image quality. Low Voltage Dropout Linear Regulator The L T3513 features an output to drive an external NPN transistor LDO to provide a lower voltage logic supply volt- age. The output is capable of providing 10mA of current to the base of the NPN. The output of the LDO is controlled by the FB5 pin. Choose the resistor values according to: RR V V LDO8 7 0 625 1= ⎛ ⎠⎟. – R8 should be 10k or less to avoid bias current errors. The internal compensation of the LDO relies on a low ESR ceramic capacitor between the values of 2.2μF and 20μF . X7R dielectrics are preferred, followed by X5R, as these materials retain their capacitance over wide voltage and temperature ranges. OPERATION

BOOST nodes as small as possible.

3519 F03

Figure 3. Subtracting the Current When the Switch is On (3a) the High Frequency Switching Current (3c) Keep this Loop Small. Figure 4. Topside PCB Layout

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 38-Lead Plastic QFN (5mm × 7mm) (Reference L TC DWG # 05-08-1701 Rev C) 5.00 p 0.10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD

5.50 REF

5.15 ± 0.10 7.00 p 0.10 0.75 p 0.05 R = 0.125 TYP R = 0.10 TYP 0.25 p 0.05 (UH) QFN REF C 1107

0.50 BSC

0.200 REF

0.00 – 0.05 RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 REF

3.15 ± 0.10 0.40 p0.10 0.70 p 0.05

5.5 REF

3.00 REF 3.15 ± 0.05 4.10 p 0.05 5.50 p 0.05 5.15 ± 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER PACKAGE DESCRIPTION

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008 LT 1108 REV A • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L T3003 3-Channel LED Ballaster with PWM Dimming V IN: 3V to 48V , IQ = 3,000:1 T rue Color PWM TM , ISD < 5μA, L T3465/L T3465A Constant Current, 1.2MHz/2.7MHz, High Effi ciency White LED Boost Regulators with Integrated Schottky Diode VIN: 2.7V to 16V , VOUT(MAX) = 34V , IQ = 1.9mA, ISD < 1μA, ThinSOT TM Package L T3466/L T3466-1 Dual Constant Current, 2MHz High Effi ciency White LED Boost Regulators with Integrated Schottky Diode VIN: 2.7V to 24V , VOUT(MAX) = 40V , IQ = 5mA, ISD < 16μA, 3mm × 3mm DFN10 Package L T3474 36V , 1A (I LED), 2MHz Step-Down LED Driver V IN: 4V to 36V , VOUT(MAX) = 13.5V , IQ = 400:1 T rue Color PWM, ISD < 16μA, TSSOP16E Package L T3475 Dual 1.5A (I LED), 36V , 2MHz Step-Down LED Driver V IN: 4V to 36V , VOUT(MAX) = 13.5V , IQ = 3,000:1 T rue Color PWM, ISD < 1μA, TSSOP20E Package L T3476 Quad Output 1.5A, 2MHz High Current LED Driver with 1,000:1 Dimming VIN: 2.8V to 16V , VOUT(MAX) = 36V , IQ = 1,000:1 T rue Color PWM, ISD < 10μA, 5mm × 7mm QFN10 Package L T3478/L T3478-1 42V , 4.5A (I SW), 2.25MHz, LED Drivers with 3,000:1 T rue Color PWM Dimming VIN: 2.8V to 36V , VOUT(MAX) = 42V , IQ = 6.1mA, ISD < 3μA, L T3486 Dual 1.3A, 2MHz High Current LED Driver V IN: 2.5V to 24V , VOUT(MAX) = 36V , IQ = 1,000:1 T rue Color PWM, ISD < 1μA, 5mm × 3mm DFN, TSSOP16E Packages L T3491 Constant Current, 2.3MHz, High Effi ciency White LED Boost Regulator with Integrated Schottky Diode VIN: 2.5V to 12V , VOUT(MAX) = 27V , IQ = 2.6mA, ISD < 8μA, 2mm × 2mm DFN6, SC70 Packages L T3494/L T3494A 40V , 180mA/350mA Micropower Low Noise Boost Converters with Output Disconnect VIN: 2.3V to 16V , VOUT(MAX) = 40V , IQ = 65μA, ISD < 1μA, 3mm × 2mm DFN8 Package L T3497 Dual 2.3MHz, Full Function LED Driver with Integrated Schottkys and 250:1 T rue Color PWM Dimming VIN: 2.5V to 10V , VOUT(MAX) = 32V , IQ = 6mA, ISD < 12μA, 3mm × 2mm DFN10 Package L T3498 2.3MHz, 20mA LED Driver and OLED Driver with Integrated Schottkys VIN: 2.5V to 12V , VOUT(MAX) = 32V , IQ = 1.65mA, ISD < 9μA, 3mm × 2mm DFN12 Package L T3591 Constant Current, 1MHz, High Effi ciency White LED Boost Regulator with Integrated Schottky Diode and 80:1 T rue Color PWM Dimming V IN: 2.5V to 12V , VOUT(MAX) = 40V , IQ = 4mA, ISD < 9μA, 3mm × 2mm DFN8 Package L T3595 16-Channel 48V , 2MHz Buck Mode LED Driver with 3000:1 T rue Color PWM Dimming VIN: 4.5V to 50V , IQ = 3,000:1 T rue Color PWM, ISD < 3μA, 5mm × 9mm QFN56 Package T rue Color PWM and ThinSOT are trademarks of Linear Technology Corporation.