2A20112

R2A20112SP RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

Features

• Maximum Ratings  Supply voltage Vcc: 24 V  Operating junction temperature Tjopr: –40 to +150°C
• Electrical characteristics  VREF output voltage VREF: 5.0 V ± 3%  UVLO operation start voltage VH: 10.5 V ± 0.7 V  UVLO operation shutdown voltage VL: 9.3 V ± 0.5 V  UVLO hysteresis voltage Hysuvl: 1.2 V ± 0.5 V
• Functions  Boost converter control with critical conduction mode  Interleaving control  Two mode overvoltage protection Mode1: Dynamic OVP corresponding to a voltage rise by load change Mode2: Static OVP corresponding to overvoltage in stable  Feedback loop open detection  Master and Slave independence overcurrent protection  280 µs restart timer  Package lineup: Pb-free SOP-16/DILP-16

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 2 of 7 Pin Arrangement ZCD-S ZCD-M VCC PGND GD-S SGND (Top view) FBCOMP NC RT NC RAMP VREF GD-M OCP-M OCP-S Pin Functions Pin No. Pin Name Input/Output Function

1 ZCD-M Input Master converter ze ro current detection input terminal

2 ZCD-S Input Slave converter zero current detection input terminal

3 N.C. — Open

4 VREF Output Reference voltage output terminal

5 SGND — Ground for small signal circuit

6 RT Input/Output Oscillator frequency setting terminal

7 RAMP Input/Output Ramp waveform setting terminal

8 COMP Output Error am plifier output terminal

9 FB Input Error amplifier input terminal

10 OCP-S Input Slave converter overcurrent detection terminal

11 OCP-M Input Master converte r overcurrent detection terminal

12 N.C. — Open

13 GD-S Output Slave converter Power MOSFET drive terminal

14 PGND — Ground for power stage

15 GD-M Output Master converter Power MOSFET drive terminal

16 VCC Input Supply voltage terminal

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 3 of 7 Block Diagram FB S R Q Q S R Q NC FB A A RT OSC 0.8V ~ 6.4V Clamp OCP-M Vzcd_lo = 1.5 V 300 mVhys 0.8V ~ 6.4V Clamp Vzcd_lo = 1.5 V 300 mVhys ZCD-M ZCD-S Slave Control + OSC OCP-S TIMER VREF: 5 V UVLO ON: 10.5 V OFF: 9.3 V Ramp Low detect0.2 V0.92 V VCC Iramp GD Disable COMP Discharge OVP BLOCK OCP-M OCP-S 0.3 V OCP-M OCP-S NC GD-S PGND GD-M VCC 2.5 V 9.1 V Error Amp OCP COMP1 OCP COMP2 VREF SGND RAMP COMP FB OVP BLOCK FB open detect GD Disable COMP Discharge VFB × 1.09 V/100 mVhys 0.5 V/0.2 Vhys VFB × 1.05 V Static OVP Dynamic OVP

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 4 of 7 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Note Supply voltage Vcc –0.3 to 24 V GD-M Peak current Ipk-gdm ±200 mA 3 GD-M DC current Idc-gdm ±10 mA GD-S Peak current Ipk-gds ±200 mA 3 GD-S DC current Idc-gds ±10 mA ZCD terminal current Izcd ±10 mA RT terminal current Irt –200 µA Vref terminal current Iref –5 mA COMP terminal current Icomp ±1 mA Vt-group1 –0.3 to Vcc V 4 Terminal voltage Vt-group2 –0.3 to Vref V 5 Vref terminal voltage Vt-ref –0.3 to Vref+0.3 V Power dissipation Pt 1 W 6 Operating junction temperature Tj-opr –40 to +150 °C Storage temperature Tstg –55 to +150 °C Notes: 1. Rated voltages are with reference to the SGND terminal. 2. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). 3. Shows the transient current when driving a capacitive load. 4. This is the rated vo ltage for the following pins: RAMP, FB 5. This is the rated vo ltage for the following pins: RT, OCP-M , OCP-S 6. In case of R2A20112DD (DILP): θja = 120°C/W In case of R2A20112SP (SOP): θja = 120°C/W This value is a thing mounting on 40 × 40 × 1.6 [mm], a glass epoxy board of wiring density 10%.

Electrical Characteristics

(Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Symbol Min Typ Max Unit Test Conditions UVLO Turn-on threshold Vuvlh 9.8 10.5 11.2 V UVLO Turn-off threshold Vuvll 8.8 9.3 9.8 V UVLO hysteresis Hysuvl 0.7 1.2 1.7 V Standby current Istby — 120 200 µA Vcc = 8.9 V, ZCD = Open Supply Operating current Icc — 4.9 7.0 mA Output voltage Vref 4.85 5.00 5.15 V Isource = –1 mA Line regulation Vref-line — 5 20 mV Isource = –1 mA, Vcc = 10 V to 24 V Load regulation Vref-load — 5 20 mV Isource = –1 mA to –5 mA VREF Temperature stability dVref — ±80 — ppm/°C Ta = –40 to 125°C * Note: 1. Design spec.

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 5 of 7 Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Symbol Min Typ Max Unit Test Conditions Feedback voltage Vfb 2.40 2.50 2.60 V FB-COMP short, RAMP = 0 V Input bias current Ifb –0.5 0 0.5 µA Measured pin: FB Open loop gain Av — 60 — dB *1 Upper clamp voltage Vclamp-comp 8.0 9.1 10.6 V FB = 2.0 V, COMP: Open Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V, COMP: Open Source current Isrc-comp — –120 — µA FB = 1.5 V, COMP = 2.5 V Sink current 1 Isnkcomp1 — 120 — µA *1 Sink current 2 Isnkcomp2 — 300 — µA FB = 3.5 V, COMP = 2.5 V Error amplifier Transconductance gm 150 200 290 µs FB = 2.45 V ↔ 2.55 V, COMP = 2.5 V RAMP charge current Ic-ramp 130 150 170 µA RAMP = 0 V to 7 V RAMP discharge current Id-ramp 7 16 29 mA FB = 1 V, COMP = 2 V, RAMP = 0 V to 1.5 V to 1 V RAMP Low voltage Vl-ramp — 17 200 mV FB = 1 V, COMP = 3 V, RAMP = 0 V to 2.5 V to open Isink = 100 µA Upper clamp voltage Vzcdh 5.8 6.4 7.0 V Isource = –3 mA Lower clamp voltage Vzcdl 0.3 0.8 1.3 V Isink = 3 mA ZCD low threshold voltage Vzcd_lo 1.05 1.50 1.75 V *1 ZCD hysteresis Hyszcd 180 300 390 mV *1 Zero current detector Input bias current Izcd –1 — 1 µA 1.2 V < Vzcd < 5 V Phase delay Phase 160 180 200 deg. *1, *2 Slave control On time ratio Ton-ratio –5 — 5 % *1, *2 Restart Restart time delay Tstart 210 280 350 µs Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Note: 1. Design spec. GD-M GD-S Tperiod (25 µs) Ton-m (12.5 µs) Tdelay Ton-s Phase = × 360 [deg.]Tdelay Tperiod Ton-ratio = × 100 [%]1 – Ton-s Ton-m

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 6 of 7 Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 22 kΩ, OCP = GND, CRAMP = 680 pF, RZCD-GND = 51 kΩ, FB = COMP) Item Symbol Min Typ Max Unit Test Conditions Master gate drive rise time tr-gdm — 30 100 ns CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Slave gate drive rise time tr-gds — 30 100 ns CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Master gate drive fall time tf-gdm — 30 100 ns CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Slave gate drive fall time tf-gds — 30 100 ns CL = 100 pF, Cramp = 3300 pF FB = 2.0 V, COMP = 5 V Vol1-gdm — 0.05 0.2 Isink = 2 mA Master gate drive low voltage Vol2-gdm — 0.03 0.7 V Isink = 1 mA, VCC = 5 V Master gate drive high voltage Voh-gdm 11.5 11.9 — V Isource = –2 mA Vol1-gds — 0.05 0.2 Isink = 2 mA Slave gate drive low voltage Vol2-gds — 0.03 0.7 V Isink = 1 mA, VCC = 5 V Gate drive Slave gate drive high voltage Voh-gds 11.5 11.9 — V Isource = –2 mA * Over current protection OCP threshold voltage Vocp 0.27 0.3 0.33 V Dynamic OVP threshold voltage Vdovp VFB× 1.035 VFB× 1.050 VFB× 1.065 V Static OVP threshold voltage Vsovp VFB× 1.075 VFB× 1.090 VFB× 1.105 V COMP = Open Static OVP hysteresis Hys- sovp 50 100 150 mV COMP = Open FB open detect threshold voltage Vfbopen 0.45 0.50 0.55 V COMP = Open Over voltage protection FB open detect hysteresis Hysfbopen 0.16 0.20 0.24 V COMP = Open Note: 1. Design spec.

REJ03D0904-0200 Rev.2.00 Nov 13, 2007 Page 7 of 7 Package Dimensions 0.80 0.15 1.27 7.50 8.00 0.400.34 10.5 MaxNomMin Dimension in Millimeters Symbol Reference 2.20 0.900.700.50 5.50 0.200.100.00 0.46 0.250.200.15 7.80 8°0° 0.12 1.15 10.06 L Z HE y x θ c bp E D e L A E 16 9 xM p y F Index mark b D E H Z A Terminal cross section ( Ni/Pd/Au plating ) p c b Detail F L L A θ NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. e P-SOP16-5.5x10.06-1.27 0.24g MASS[Typ.] FP-16DAVPRSP0016DH-B RENESAS CodeJEITA Package Code Previous Code 7.62 MaxNomMin Dimension in Millimeters Symbol Reference 19.2 6.3 5.06 Z D E A bp c θ e L 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0° 15° 20.32 7.4 0.40 0.48 1.12 2.54 p 1 8 16 9 e b A L A Z e c E D b 0.89 θ ( Ni/Pd/Au plating ) MASS[Typ.] DP-16FVPRDP0016AE-B RENESAS CodeJEITA Package Code Previous Code

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