SST29EE010_00 SST

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1 Megabit (128K x8) Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010 Data Sheet © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. 304-3 6/00 These specifications are subject to change without notice. FEATURES:

  • Single Voltage Read and Write Operations – 5.0V-only for the SST29EE010 – 3.0-3.6V for the SST29LE010 – 2.7-3.6V for the SST29VE010
  • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention
  • Low Power Consumption – Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V – Standby Current: 10 µA (typical)
  • Fast Page-Write Operation – 128 Bytes per Page, 1024 Pages – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 5 sec (typical) – Effective Byte-Write Cycle Time: 39 µs (typical)
  • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 3.0-3.6V operation: 150 and 200 ns – 2.7-3.6V operation: 200 and 250 ns
  • Latched Address and Data
  • Automatic Write Timing – Internal V PP Generation
  • End of Write Detection – Toggle Bit – Data# Polling
  • Hardware and Software Data Protection
  • TTL I/O Compatibility
  • JEDEC Standard – Flash EEPROM Pinouts and command sets
  • Packages Available – 32 Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 20mm, 8mm x 14mm) PRODUCT DESCRIPTION The SST29EE010/29LE010/29VE010 are 128K x8 CMOS Page-Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash tech- nology. The split-gate cell design and thick oxide tunnel- ing injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010/29LE010/29VE010 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE010/29LE010/29VE010 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Page-Write, the SST29EE010/29LE010/29VE010 provide a typical Byte- Write time of 39 µsec. The entire memory, i.e., 128 KBytes, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a Write cycle. To protect against inadvertent write, the SST29EE010/29LE010/29VE010 have on-chip hard- ware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applica- tions, the SST29EE010/29LE010/29VE010 are offered with a guaranteed Page-Write endurance of 10 4 cycles. Data retention is rated at greater than 100 years. The SST29EE010/29LE010/29VE010 are suited for ap- plications that require convenient and economical updat- ing of program, configuration, or data memory. For all system applications, the SST29EE010/29LE010/ 29VE010 significantly improve performance and reliabil- ity, while lowering power consumption. The SST29EE010/29LE010/29VE010 improve flexibility while lowering the cost for program, data, and configura- tion storage applications. To meet high density, surface mount requirements, the SST29EE010/29LE010/29VE010 are offered in 32-pin TSOP (8mm x 20mm and 8mm x 14mm) and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST Page-Mode EEPROM offers in-circuit electrical write capability. The SST29EE010/29LE010/29VE010 does not require separate Erase and Program opera- tions. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE010/29LE010/29VE010 have industry stan- dard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE010/ 29LE010/29VE010 are compatible with industry stan- dard EEPROM pinouts and functionality. Read The Read operations of the SST29EE010/29LE010/ 29VE010 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the

© 2000 Silicon Storage Technology, Inc. 304-3 6/00

1 Megabit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010 chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3). Write The Page-Write to the SST29EE010/29LE010/29VE010 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE010/29LE010/29VE010 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same com- mand bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes on “The Proper Use of JEDEC Standard Software Data Protection” and “Pro- tecting Against Unintentional Writes When Using Single Power Supply Flash Memories” in this data book. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE010/29LE010/29VE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an in- ternally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the T BLCO timer after the rising edge of WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled Page- Write cycle timing diagrams and Figures 14 and 16 for flowcharts. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three-byte load se- quence that allows writing to the selected page and will leave the SST29EE010/29LE010/29VE010 protected at the end of the Page-Write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the T BLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE010/ 29LE010/29VE010 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the Page-Write feature of SST29EE010/ 29LE010/29VE010 allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A 7 through A16. Any byte not loaded with user data will be written to FF. See Figures 4 and 5 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte- load cycle time (T BLC ) of 100 µs, the SST29EE010/ 29LE010/29VE010 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs (T BLCO ) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 µs. The page to be loaded is determined by the page address of the last byte loaded. Software Chip-Erase The SST29EE010/29LE010/29VE010 provide a Chip- Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flow- chart.

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 Write Operation Status Detection The SST29EE010/29LE010/29VE010 provide two soft- ware means to detect the completion of a Write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ 7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. The actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ 7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ When the SST29EE010/29LE010/29VE010 are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. Toggle Bit (DQ During the internal write cycle, any consecutive attempts to read DQ 6 will produce alternating 0’s and 1’s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. Data Protection The SST29EE010/29LE010/29VE010 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VCC Power Up/Down Detection: The Write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inad- vertent writes during power-up or power-down. Software Data Protection (SDP) The SST29EE010/29LE010/29VE010 provide the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation re- quires the inclusion of a series of three byte-load opera- tions to precede the data loading operation. The three byte-load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent write opera- tions, e.g., during the system power-up or power-down. The SST29EE010/29LE010/29VE010 are shipped with the Software Data Protection disabled. The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific soft- ware command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 µs. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts. The SST29EE010/29LE010/29VE010 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled.

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FUNCTIONAL BLOCK DIAGRAM OF SST29EE010/29LE010/29VE010 Single power supply reprogrammable nonvolatile memo- ries may be unintentionally altered. SST strongly recom- mends that Software Data Protection (SDP) always be enabled. The SST29EE010/29LE010/29VE010 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing. Please refer to the following Application Notes located at the back of this databook for more information on using SDP:

  • Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories
  • The Proper Use of JEDEC Standard Software Data Protection Product Identification The product identification mode identifies the device as the SST29EE010/29LE010/29VE010 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST29EE010/29LE010/29VE010. Users may wish to use the software product identification operation to identify the part (i.e. using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations. Product Identification Mode Exit In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 4 for software command codes, Figure 11 for timing wave- form and Figure 17 for a flowchart. 304 PGM T1.2 TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Data Manufacturer’s ID 0000 H BF H SST29EE010 Device ID 0001 H 07 H SST29LE010 Device ID 0001 H 08 H SST29VE010 Device ID 0001 H 08 H Y -Decoder and Page Latches I/O Buffers and Data Latches 304 ILL B1.0 Address Buffer & Latches X-Decoder DQ 7 - DQ0 A16 - A0 WE# OE# CE# 1,048,576 Bit EEPROM Cell Array Control Logic

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCC S FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A16-A7 Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle. A6-A0 Column Address Column Addresses are toggled to load page data. Inputs DQ7-DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations Vcc Power Supply To provide 5-volt supply (± 10%) for the SST29EE010, 3-volt supply SST29VE010 Vss Ground NC No Connection Unconnected pins. 304 PGM T2.0 A11 A13 A14 NC WE# VCC NC A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 304 ILL F01.1 Standard Pinout Top View Die Up DQ0 A14 A13 A11 OE# A10 CE# DQ7 4 3 2 1 32 31 30 A12 A15 A16 NC VCC WE# NC 32-Lead PLCC Top View 32-Pin PDIP Top View 304 ILL F02.0 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 NC A16 A15 A12 DQ0 DQ1 DQ2 VSS VCC WE# NC A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read V IL V IL VIH D OUT AIN Page-Write V IL VIH V IL D IN AIN Standby V IH X X High Z X Write Inhibit X V IL X High Z/ D OUT X Write Inhibit X X V IH High Z/ DOUT X Software Chip-Erase VIL VIH V IL D IN AIN, See Table 4 Product Identification Hardware Mode V IL V IL VIH Manufacturer ID (BF) A 16 - A1 = VIL, A9 = VH , A0 = VIL Device ID (see notes) A 16 - A1 = VIL, A9 = VH , A0= VIH Software Mode V IL VIH V IL See Table 4 SDP Enable Mode V IL VIH V IL See Table 4 SDP Disable Mode V IL VIH V IL See Table 4 304 PGM T3.0 TABLE 4: SOFTWARE COMMAND CODES Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data Software Data 5555H AAH 2AAAH 55H 5555H A0H Addr(2) Data Protect Enable & Page-Write Software Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H Protect Disable Software Chip- 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Erase Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate Software 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H ID Entry(3) Notes: (1) Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”. (2) Page-Write consists of loading up to 128 Bytes (A6 - A0). (3) Alternate six-byte software Product-ID Command Code (4) The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer ID = BFH, is read with A0 = 0, SST29EE010 Device ID = 07H, is read with A0 = 1. SST29LE010/29VE010 Device ID = 08H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. 3. This device supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends the three-byte command code sequence be used. 304 PGM T4.1

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 SST29EE010 O PERATING RANGE Range Ambient Temp V CC Commercial 0°C to +70°C 5V±10% Industrial -40°C to +85°C 5V±10% AC CONDITIONS OF TEST See Figures 12 and 13 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) CC + 0.5V Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. SST29LE010 O PERATING RANGE Range Ambient Temp V CC Commercial 0°C to +70°C 3.0V to 3.6V Industrial -40°C to +85°C 3.0V to 3.6V SST29VE010 O PERATING RANGE Range Ambient Temp V CC Commercial 0°C to +70°C 2.7V to 3.6V Industrial -40°C to +85°C 2.7V to 3.6V

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 TABLE 5: SST29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10% Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=V IL,WE#=V IH , all I/Os open, Read 30 mA Address input = V IL/VIH, at f=1/TRC Min., VCC =VCC Max Write 50 mA CE#=WE#=V IL, OE#=V IH, VCC =V CC Max. ISB1 Standby VCC Current 3 mA CE#=OE#=WE#=V IH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 50 µA CE#=OE#=WE#=V CC -0.3V. (CMOS input) V CC = VCC Max. ILI Input Leakage Current 1 µA V IN =GND to VCC , VCC = VCC Max. ILO Output Leakage Current 10 µA V OUT =GND to VCC , VCC = VCC Max. VIL Input Low Voltage 0.8 V V CC = VCC Min. VIH Input High Voltage 2.0 V V CC = VCC Max. VOL Output Low Voltage 0.4 V I OL = 2.1 mA, VCC = VCC Min. VOH Output High Voltage 2.4 V I OH = -400µA, VCC = VCC Min. VH Supervoltage for A9 11.6 12.4 V CE# = OE# =V IL, WE# = VIH IH Supervoltage Current 100 µA CE# = OE# = V IL, WE# = VIH, for A9 A9 = VH Max. 304 PGM T5.1 TABLE 6: SST29LE010/29VE010 DC OPERATING CHARACTERISTICS VCC = 3.0-3.6 FOR SST29LE010, VCC = 2.7-3.6 FOR SST29VE010 Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=V IL,WE#=V IH , all I/Os open, Read 12 mA Address input = V IL/VIH, at f=1/TRC Min., VCC =VCC Max Write 15 mA CE#=WE#=V IL, OE#=V IH, VCC =VCC Max. ISB1 Standby VCC Current 1 mA CE#=OE#=WE#=V IH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 15 µA CE#=OE#=WE#=V CC -0.3V. (CMOS input) V CC = VCC Max. ILI Input Leakage Current 1 µA V IN =GND to VCC , VCC = VCC Max. ILO Output Leakage Current 10 µA V OUT =GND to VCC , VCC = VCC Max. VIL Input Low Voltage 0.8 V V CC = VCC Min. VIH Input High Voltage 2.0 V V CC = VCC Max. VOL Output Low Voltage 0.4 V I OL = 100 µA, VCC = VCC Min. VOH Output High Voltage 2.4 V I OH = -100 µA, VCC = VCC Min. VH Supervoltage for A9 11.6 12.4 V CE# = OE# =V IL, WE# = VIH IH Supervoltage Current 100 µA CE# = OE# = V IL, WE# = VIH, for A9 A9 = VH Max. 304 PGM T6.1

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open) Parameter Description Test Condition Maximum C I/O(1) I/O Pin Capacitance V I/O = 0V 12 pF C IN(1) Input Capacitance V IN = 0V 6 pF Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 304 PGM T8.0 TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N END Endurance 10,000 Cycles JEDEC Standard A117 TDR (1) Data Retention 100 Years JEDEC Standard A103 VZAP_HBM (1) ESD Susceptibility 2000 Volts JEDEC Standard A114 Human Body Model VZAP_MM (1) ESD Susceptibility 200 Volts JEDEC Standard A115 Machine Model ILTH (1) Latch Up 100 mA JEDEC Standard 78 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 304 PGM T9.3 TABLE 7: POWER -UP TIMINGS Symbol Parameter Maximum Units TPU-READ (1) Power-up to Read Operation 100 µs TPU-WRITE (1) Power-up to Write Operation 5 ms 304 PGM T7.0

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 TABLE 11: SST29LE010 READ CYCLE TIMING PARAMETERS SST29LE010-150 SST29LE010-200 Symbol Parameter Min Max Min Max Units TRC Read Cycle Time 150 200 ns TCE Chip Enable Access Time 150 200 ns TAA Address Access Time 150 200 ns TOE Output Enable Access Time 60 100 ns TCLZ (1) CE# Low to Active Output 0 0 ns TOLZ (1) OE# Low to Active Output 0 0 ns TCHZ (1) CE# High to High-Z Output 30 50 ns TOHZ (1) OE# High to High-Z Output 30 50 ns TOH (1) Output Hold from Address Change 0 0 ns 304 PGM T11.0 TABLE 12: SST29VE010 READ CYCLE TIMING PARAMETERS SST29VE010-200 SST29VE010-250 Symbol Parameter Min Max Min Max Units TRC Read Cycle Time 200 250 ns TCE Chip Enable Access Time 200 250 ns TAA Address Access Time 200 250 ns TOE Output Enable Access Time 100 120 ns TCLZ (1) CE# Low to Active Output 0 0 ns TOLZ (1) OE# Low to Active Output 0 0 ns TCHZ (1) CE# High to High-Z Output 50 50 ns TOHZ (1) OE# High to High-Z Output 50 50 ns TOH (1) Output Hold from Address Change 0 0 ns 304 PGM T12.0 AC CHARACTERISTICS TABLE 10: SST29EE010 READ CYCLE TIMING PARAMETERS SST29EE010-90 SST29EE010-120 Symbol Parameter Min Max Min Max Units TRC Read Cycle Time 90 120 ns TCE Chip Enable Access Time 90 120 ns TAA Address Access Time 90 120 ns TOE Output Enable Access Time 40 50 ns TCLZ (1) CE# Low to Active Output 0 0 ns TOLZ (1) OE# Low to Active Output 0 0 ns TCHZ (1) CE# High to High-Z Output 30 30 ns TOHZ (1) OE# High to High-Z Output 30 30 ns TOH (1) Output Hold from Address 0 0 ns Change 304 PGM T10.1

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 TABLE 13: PAGE -W RITE CYCLE TIMING PARAMETERS SST29EE010 SST29LE/VE010 Symbol Parameter Min Max Min Max Units TWC Write Cycle (Erase and Program) 10 10 ms TAS Address Setup Time 0 0 ns TAH Address Hold Time 50 70 ns TCS WE# and CE# Setup Time 0 0 ns TCH WE# and CE# Hold Time 0 0 ns TOES OE# High Setup Time 0 0 ns TOEH OE# High Hold Time 0 0 ns TCP CE# Pulse Width 70 120 ns TWP WE# Pulse Width 70 120 ns TDS Data Setup Time 35 50 ns TDH Data Hold Time 0 0 ns TBLC (1) Byte Load Cycle Time 0.05 100 0.05 100 µs TBLCO (1) Byte Load Cycle Time 200 200 µs TIDA Software ID Access and Exit Time 10 10 µs TSCE Software Chip-Erase 20 20 ms Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 304 PGM T13.3

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 3: READ CYCLE TIMING DIAGRAM FIGURE 4: WE# CONTROLLED PAGE -W RITE CYCLE TIMING DIAGRAM 304 ILL F03.0 CE# ADDRESS A 16-0 OE# WE# DQ 7-0 VIH TCLZ TOH DATA VALIDDATA VALID TOLZ TOE HIGH-Z HIGH-Z TCE TCHZ TOHZ TRC TAA 304 ILL F04.1 CE# OE# WE# ADDRESS A 16-0 DQ 7-0 SW0 AA 55 A0 DATA VALID SW1 SW2 BYTE 0 BYTE 1 BYTE 127 TDS TDH TBLC TBLCO TWC TWP TOEHTOES TCHTCS TAH TAS 5555 Three-Byte Sequence for Enabling SDP 2AAA 5555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 5: CE# CONTROLLED PAGE -W RITE CYCLE TIMING DIAGRAM FIGURE 6: DATA # POLLING TIMING DIAGRAM 304 ILL F06.0 CE# OE# WE# TWC + TBLCO TOE TOEH TCE TOES D# D ADDRESS A 16-0 DQ 7 D 304 ILL F05.1 CE# OE# WE# ADDRESS A 16-0 DQ 7-0 SW0 AA 55 A0 DATA VALID SW1 SW2 BYTE 0 BYTE 1 BYTE 127 TDS TDH TBLC TBLCO TWC TCP TOEHTOES TCHTCS TAH TAS 5555 Three-Byte Sequence for Enabling SDP 2AAA 5555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 7: TOGGLE BIT TIMING DIAGRAM FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM 304 ILL F07.0 CE# OE# WE# TWC + TBLCO TWO READ CYCLES WITH SAME OUTPUTS TOEH TOE TOES TCE ADDRESS A 16-0 DQ 6 304 ILL F08.1 CE# OE# WE# ADDRESS A 14-0 DQ 7-0 SW0 SW1 SW2 SW3 SW4 SW5 TBLCO TBLC TWC TWP 55555555 55AA 55 20 AA80 Six-Byte Sequence for Disabling Software Data Protection 2AAA2AAA 55555555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 9: SOFTWARE CHIP-ERASE TIMING DIAGRAM FIGURE 10: SOFTWARE ID ENTRY AND READ 304 ILL F09.1 CE# OE# WE# ADDRESS A 14-0 DQ 7-0 SW0 SW1 SW2 SW3 SW4 SW5 TBLCO TBLC TSCE TWP 55555555 55AA 55 10 AA80 Six-Byte Code for Software Chip-Erase 2AAA2AAA 55555555 304 ILL F10.1 CE# OE# WE# ADDRESS A 14-0 DQ 7-0 SW0 SW1 SW2 DEVICE ID = 07 for SST29EE010 = 08 for SST29LE010/29VE010 TIDA TAA TBLC TWP 5555 55AA BF DEVICE ID90 Three-Byte Sequence for Software ID Entry 00002AAA 00015555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 11: SOFTWARE ID EXIT AND RESET 304 ILL F11.0 CE# OE# WE# ADDRESS A 14-0 DQ 7-0 SW0 SW1 SW2 TIDA TBLC TWP 5555 55AA F0 Three-Byte Sequence for Software ID Exit and Reset 2AAA5555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 12: AC INPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 13: A TEST LOAD EXAMPLE 304 ILL F13.0 TEST LOAD EXAMPLE TO TESTER TO DUT C L R L LOW R L HIGH VCC 304 ILL F12.1 REFERENCE POINTS OUTPUTINPUT VHT VLT VHT VLT VIHT VILT AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% « 90%) are <10 ns. Note: VHT –VHIGH Test VLT–VLOW Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 14: WRITE ALGORITHM 304 ILL F14.0 No Load Byte Data Ye s Byte Address = 128? Write Completed Increment Byte Address By 1 Wait TBLCO Wait for end of Write (TWC , Data# Polling bit or Toggle bit operation) Set Byte Address = 0 Set Page Address Software Data Protect Write Command Start See Figure 16

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 15: WAIT OPTIONS 304 ILL F15.1 No No Read a byte from page Ye s Ye s Does DQ 6 match? Write Completed Read same byte Page-Write Initiated Toggle Bit Wait TWC Write Completed Page-Write Initiated Internal Timer Read DQ 7 (Data for last byte loaded) Is DQ7 = true data? Write Completed Page-Write Initiated Data# Polling

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS 304 ILL F16.0 Write data: AA Address: 5555 Software Data Protect Enable Command Sequence Write data: 55 Address: 2AAA Write data: A0 Address: 5555 Wait TWC Wait TBLCO SDP Enabled Load 0 to

128 Bytes of

Write data: AA Address: 5555 Software Data Protect Disable Command Sequence Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: AA Address: 5555 Wait TWC Wait TBLCO SDP Disabled Write data: 55 Address: 2AAA Write data: 20 Address: 5555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS 304 ILL F17.0 Write data: AA Address: 5555 Software Product ID Entry Command Sequence Write data: 55 Address: 2AAA Pause 10 µs Write data: 90 Address: 5555 Read Software ID Write data: AA Address: 5555 Software Product ID Exit & Reset Command Sequence Write data: 55 Address: 2AAA Pause 10 µs Write data: F0 Address: 5555 Return to normal operation

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 FIGURE 18: SOFTWARE CHIP-ERASE COMMAND CODES 304 ILL F18.1 Write data: AA Address: 5555 Software Chip-Erase Command Sequence Write data: 55 Address: 2AAA Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 10 Address: 5555 Wait TSCE Chip-Erase to FFH Write data: 80 Address: 5555

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST29xE010 - XXX - XX - XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up) 8mm x 20mm W = TSOP (die up) 8mm x 14mm U = Unencapsulated die Operating Temperature C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns Voltage E = 5.0V-only L = 3.0-3.6V V = 2.7-3.6V

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 SST29EE010 Valid combinations SST29EE010-90-4C-EH SST29EE010-90-4C-NH SST29EE010-90-4C-PH SST29EE010-120-4C-EH SST29EE010-120-4C-NH SST29EE010-120-4C-PH SST29EE010-90-4C-WH SST29EE010-120-4C-WH SST29EE010-90-4I-EH SST29EE010-90-4I-NH SST29EE010-90-4I-WH SST29EE010-120-4C-U2 SST29LE010 Valid combinations SST29LE010-150-4C-EH SST29LE010-150-4C-NH SST29LE010-150-4C-WH SST29LE010-150-4I-EH SST29LE010-150-4I-NH SST29LE010-150-4I-WH SST29LE010-200-4C-U2 SST29VE010 Valid combinations SST29VE010-200-4C-EH SST29VE010-200-4C-NH SST29VE010-200-4C-WH SST29VE010-200-4I-EH SST29VE010-200-4I-NH SST29VE010-200-4I-WH SST29VE010-250-4C-U2 Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part.

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE : NH 32-LEAD PLASTIC DUAL -IN-LINE PACKAGE (PDIP) SST PACKAGE CODE : PH PACKAGING DIAGRAMS 32.pdipPH-ILL.1 pin 1 index CL Base Plane Seating Plane Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .170 .200 4 PLCS. .600 BSC.100 BSC .120 .150.016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 15˚ .600 .625 .530 .550 .030 .040 .013 .021 .490 .530 .075 .095 .015 Min. .125 .140 TOP VIEW SIDE VIEW BOTTOM VIEW 123 2 .026 .032 .400 BSC 32.PLCC.NH-ILL.1 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. .050 BSC. .050 BSC. .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 Optional Pin #1 Identifier .547 .553 .585 .595 .485 .495 .020 R. MAX. .106 .112 R.x 30˚

© 2000 Silicon Storage Technology, Inc. 304-3 6/00 SST29EE010 / SST29LE010 / SST29VE010 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE : EH 32.TSOP-WH-ILL.3 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 PIN # 1 IDENTIFIER 14.20 13.80 0.70 0.50 32.TSOP-EH-ILL.3 Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 8.10 7.90 .27 .17 1.05 0.95 .50 BSC 0.15 0.0518.50 18.30 20.20 19.80 0.70 0.50 PIN # 1 IDENTIFIER Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873