28F128J3A INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 58
Technical content
Datasheet sections
- 1.0 Product Overview
- 2.0 Principles of Operation
- 2.1 Data Protection
- 3.0 Bus Operations
- 3.1 Read
- 3.2 Output Disable
- 3.3 Standby
- 3.4 Reset/Power-Down
- 3.5 Read Query
- 3.6 Read Identifier Codes
- 3.7 Write
- 4.0 Command Definitions
- 4.1 Read Array Command
- 4.2 Read Query Mode Command
- 4.2.1 Query Structure Output
- 4.2.2 Query Structure Overview
- 4.2.3 Block Status Register
- 4.2.4 CFI Query Identification String
- 4.2.5 System Interface Information
- 4.2.6 Device Geometry Definition
- 4.2.7 Primary-Vendor Specific Extended Query Table
- 4.3 Read Identifier Codes Command
- 4.4 Read Status Register Command
- 4.5 Clear Status Register Command
- 4.6 Block Erase Command
- 4.7 Block Erase Suspend Command
- 4.8 Write to Buffer Command
- 4.9 Byte/Word Program Commands
- 4.10 Program Suspend Command
- 4.11 Set Read Configuration Command
- 4.11.1 Read Configuration
- 4.12 Configuration Command
- 4.13 Set Block Lock-Bit Commands
- 4.14 Clear Block Lock-Bits Command
- 4.15 Protection Register Program Command
- 4.15.1 Reading the Protection Register
- 4.15.2 Programming the Protection Register
- 4.15.3 Locking the Protection Register
- 5.0 Design Considerations
- 5.1 Three-Line Output Control
- 5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling
- 5.3 Power Supply Decoupling
- 5.4 Input Signal Transitions - Reducing Overshoots and Undershoots When Using
3 Volt Intel® StrataFlash™ Memory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16) Preliminary Datasheet Product Features Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel® StrataFlash™ memory products provide 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-per-cell storage technology to the flash market segment. Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of over one billion units of manufacturing experience since 1987. As a result, Intel StrataFlash components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash memory (28F640J5 and 28F320J5) devices. Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel ® 0.25 micron ETOX™ VI process technology, Intel StrataFlash memory provides the highest levels of quality and reliability. I High-Density Symmetrically-Blocked Architecture — 128 128-Kbyte Erase Blocks (128 M) — 64 128-Kbyte Erase Blocks (64 M) — 32 128-Kbyte Erase Blocks (32 M) I High Performance Interface Asynchronous Page Mode Reads — 110/25 ns Read Access Time (32 M) — 120/25 ns Read Access Time (64 M) — 150/25 ns Read Access Time (128 M) I 2.7 V–3.6 V VCC Operation I 128-bit Protection Register — 64-bit Unique Device Identifier — 64-bit User Programmable OTP Cells I Enhanced Data Protection Features Absolute Protection with VPEN = GND — Flexible Block Locking — Block Erase/Program Lockout during Power Transitions I Packaging — 56-Lead TSOP Package — 64-Ball Intel® Easy BGA Package I Cross-Compatible Command Support Intel Basic Command Set — Common Flash Interface — Scalable Command Set I 32-Byte Write Buffer — 6 µs per Byte Effective Programming Time I 12.8M Total Min. Erase Cycles (128 Mbit) 6.4M Total Min. Erase Cycles (64 Mbit) 3.2M Total Min. Erase Cycles (32 Mbit) — 100K Minimum Erase Cycles per Block I Automation Suspend Options — Block Erase Suspend to Read — Block Erase Suspend to Program — Program Suspend to Read I 0.25 µ Intel® StrataFlash™ Memory Technology Order Number: 290667-008 April 2001 Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F128J3A, 28F640J3A, 28F320J3A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999–2001 *Other names and brands may be claimed as the property of others.
28F128J3A, 28F640J3A, 28F320J3A iv Preliminary Buffers or Transceivers39
6.5 AC Characteristics— Read-Only Operations
28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date of Revision Version Description 07/07/99 -001 Original Version 08/03/99 -002 A 0–A2 indicated on block diagram 09/07/99 -003 Changed Minimum Block Erase time,I OL , IOH , Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations 12/16/99 -004 Changed Block Erase time and t AVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart 03/16/00 -005 Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed V CCQ1 setting and changed VCCQ2/3 to VCCQ1/2 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed V OL of 0.45 V Removed V OH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements 06/26/00 -006 Updated cover sheet statement of 700 million units to one billion. Corrected Table 10 to show correct maximum program times. Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 2/15/01 -007 Updated cover page to reflect 100K minimum erase cycles. Updated cover page to reflect 110 ns 32M read speed. Removed Set Read Configuration command from Table 4. Updated Table 8 to reflect reserved bits are 1-7; not 2-7. Updated Table 16 bit 2 definition from R to PSS. Changed V PENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec- tion 6.5, AC Characteristics–Read-Only Operations (1,2) Updated write parameter W13 (tWHRL ) from 90 ns to 500 ns, Section 6.6, AC Characteristics–Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1 ) from 30 to 75 µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per- formance (1,2,3) 04/13/01 -008 Revised Section 7.0, Ordering Information
28F128J3A, 28F640J3A, 28F320J3A Preliminary 1
1.0 Product Overview
The 0.25 µ 3 V olt Intel StrataFlash memory family contains high-density memories organized as
16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in- system. A 128-bit protection register has multiple uses, including unique flash device identification. The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward- compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The status register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
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on completion of programming and/or block erases. miniature card or SIMM module. device block diagram is shown in Figure 1 on page 2. (Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities. Figure 2 and Figure 3 show the pinouts. Figure 1. 3 Volt Intel® StrataFlash™ Memory Block Diagram
Table 1. Lead Descriptions internally latched during a program cycle. bit 7) to determine WSM status. when the chip is de-selected, the outputs are disabled, or the WSM is busy. CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 2 on page 7), power reduces to standby levels. CE 0, CE1, or CE2 that disables the device (see Table 2 on page 7). RP# inhibits write operations which provides data protection during power transitions. WE# INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. CCQ with a pull-up resistor. With VPEN ≤ VPENLK , memory contents cannot be altered. VCC SUPPLY DEVICE POWER SUPPLY: With VCC ≤ VLKO , all write attempts to the flash memory are inhibited. output voltages compatible with system data bus voltages, connect VCCQ to the system supply voltage. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
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- Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC)
- Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC)
- Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC)
- Don’t Use (DU) pins refer to pins that should not be connected
Figure 2. 3 Volt Intel® StrataFlash™ Memory Easy BGA Package
- A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this pin is a no-connect (NC).
- A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this pin is a no-connect (NC).
- A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this pin is a no-connect (NC).
Figure 3. 3 Volt Intel® StrataFlash™ Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy
3 Volt Intel
28F128J3A, 28F640J3A, 28F320J3A
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2.0 Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset/power-down mode (see Section 3.0, “Bus Operations” on page 7), the device defaults to read array mode. Manipulation of external memory control pins allows array read, standby, and output disable operations. Read array, status register, query, and identifier codes can be accessed through the CUI (Command User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block erasure, programming, and lock-bit configuration. All functions associated with altering memory contents— block erase, program, lock-bit configuration— are accessed via the CUI and verified through the status register. Commands are written using standard micro-processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, program, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during program cycles. Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or program data from/to any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location.
2.1 Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to VPENH . The device accommodates either design practice and encourages optimization of the processor-memory interface. When V PEN ≤ VPENLK , memory contents cannot be altered. The CUI’s two-step block erase, byte/ word program, and lock-bit configuration command sequences provide protection from unwanted operations even when VPENH is applied to VPEN . All program functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations.
3.0 Bus Operations
memory conform to standard microprocessor bus cycles. NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND. Figure 4. Memory Map Table 2. Chip Enable Truth Table
28F128J3A, 28F640J3A, 28F320J3A
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3.1 Read
Information can be read from any block, query, identifier codes, or status register independent of the VPEN voltage. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data flow in and out of the component: CE 0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 2, “Chip Enable Truth Table” on page 7), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 2), select the memory device. OE# is the data output (DQ0–DQ 15) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at VIH. When reading information in read array mode, the device defaults to asynchronous page mode. This mode provides high data transfer rate for memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A 2:0 addresses data in the page buffer. The page size is four words or eight bytes. Asynchronous word/byte mode is supported with no additional commands required.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ 15 are placed in a high-impedance state.
3.3 Standby
CE 0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which substantially reduces device power consumption. DQ0–DQ 15 outputs are placed in a high- impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
3.4 Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH . Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake- up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time t PHWL is required after RP# goes to logic-high (VIH) before another command can be written.
28F128J3A, 28F640J3A, 28F320J3A Preliminary 9 As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel ® Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5 Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information, and Intel-specific extended query information.
3.6 Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code and the block lock configuration codes for each block (see Figure 5 on page 10). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock configuration codes identify locked and unlocked blocks.
3.7 Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when V PEN = VPENH , block erasure, program, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). Standard microprocessor write timings are used.
4.0 Command Definitions
When the VPEN voltage ≤ VPENLK , only read operations from the status register, query, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.
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x16 mode (upper byte contains 00h). Figure 5. Device Identifier Code Memory Map
32 Mbit
64 Mbit
128 Mbit
- See Table 2 for valid CE configurations.
- OE# and WE# should never be enabled simultaneously.
0–DQ 7 if BYTE# is low and DQ0–DQ 15 if BYTE# is high.
- Refer to DC Characteristics. When VPEN ≤ VPENLK , memory contents can be read, but not altered.
- X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for
- In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit
programming inactive), program suspend mode, or reset/power-down mode.
- High Z will be VOH with an external pull-up resistor.
- See Section 3.6 for read identifier code data.
- See Section 4.2 for read query data.
VPENH and VCC is within specification. 11.Refer toTable 4 for valid DIN during a write operation. Table 3. Bus Operations
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- Commands other than those shown above are reserved by Intel for future device implementations and
- The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command
Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set.
- Bus operations are defined in Table 3.
- X = Any valid address within the device.
BA = Address within the block. IA = Identifier Code Address: see Figure 5 and Table 15. QA = Query database Address. PA = Address of memory location to be programmed. other address inputs are ignored.
- ID = Data read from Identifier Codes.
QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
- The upper byte of the data bus (DQ
8–DQ 15) during command writes is a “Don ’t Care” in x16 operation.
- Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See Section 4.3 for read identifier code data.
- If the WSM is running, only DQ7 is valid; DQ15–DQ 8 and DQ6–DQ 0 float, which places them in a high-
- After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
Table 4. Intel® StrataFlash™ Memory Command Set Definitions(1)
11 Write BA E8H Write BA N
28F128J3A, 28F640J3A, 28F320J3A Preliminary 13 10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 7, “Write to Buffer Flowchart” on page 30 for additional information. 11.The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 12.Attempts to issue a block erase or program to a locked block. 13.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 14.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is initiated. 15.The clear block lock-bits operation simultaneously clears all block lock-bits.
4.1 Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. The read configuration register defaults to asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the V PEN voltage.
4.2 Read Query Mode Command
This section defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
4.2.1 Query Structure Output
The Query “database” allows system software to gain information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0–7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, “Q ” and “R ” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q ” in the low byte (DQ 0–7) and 00h in the high byte (DQ8–15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
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shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
- The system must drive the lowest order addresses to access all the device’s array data when the device is
system, is "Not Applicable" for x8-configured devices.
4.2.2 Query Structure Overview
The following sections describe the Query structure sub-sections in detail. Table 5. Summary of Query Structure Output as a Function of Device and Mode Table 6. Example of Query Structure Output of a x16- and x8-Capable Device
- Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
- BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is
- Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.
4.2.3 Block Status Register
given block is locked or can be accessed for flash program/erase operations.
- BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location
4.2.4 CFI Query Identification String
vendor-specified command set(s). Table 7. Query Structure(1) Table 8. Block Status Register Table 9. CFI Identification
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4.2.5 System Interface Information
The following device information can optimize system interface software. Table 10. System Interface Information
4.2.6 Device Geometry Definition
This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition
- x = 0 means no erase blocking; the device erases in “bulk”
- x specifies the number of device or partition regions with one or
- Symmetrically blocked partitions have one blocking region
- Partition size = (total blocks) x (individual block size)
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4.2.7 Primary-Vendor Specific Extended Query Table
table specifies this and other similar information.
- Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value
Table 12. Primary Vendor-Specific Extended Query
- The variable P is a pointer which is defined at CFI offset 15h.
- The variable P is a pointer which is defined at CFI offset 15h.
4.3 Read Identifier Codes Command
manufacturer, device and block lock configuration codes (see Table 15 for identifier code values). Table 13. Protection Register Information (P+E)h 1 Number of Protection register fields in JEDEC ID space. pre-programmed and user-programmable. Table 14. Burst Read Information
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- A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is
A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h).
- X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory
4.4 Read Status Register Command
functions independently of the VPEN voltage. (check status register bit 7), all contents of the status register are valid when read. Table 15. Identifier Codes
- Block Is Unlocked DQ 0 = 0
- Block Is Locked DQ 0 = 1
- Reserved for Future Use DQ 1–7
Table 16. Status Register Definitions Table 17. eXtended Status Register Definitions command sequence was entered. Block Lock-Bits command sequences. Codes command to determine block lock-bit status. masked when polling the status register. that a Write Buffer is available. be masked when polling the status register.
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4.5 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 16). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V PEN voltage. The Clear Status Register command is only valid when the WSM is off or the device is suspended.
4.6 Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 10, “Block Erase Flowchart” on page 33). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE 0, CE1, or CE2 to update the status register. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V CC is valid and VPEN = VPENH . If block erase is attempted while VPEN ≤ VPENLK , SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set to “1.”
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set to “1”). In default mode, STS will also transition to V OH . Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to “0” and STS output (in default mode) will transition to V OL . However, SR.6 will remain “1” to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by
28F128J3A, 28F640J3A, 28F320J3A Preliminary 23 issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V OL . After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 11, “Block Erase Suspend/Resume Flowchart” on page 34). V PEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8 Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure 7, “Write to Buffer Flowchart” on page 30). At this point, the eXtended Status Register (XSR, see Table 17) information is loaded and XSR.7 reverts to “buffer available” status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is ready for loading. Now a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A 4–A 0 of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another Write to Buffer Setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. If a program error is detected, the status register should be erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an “Invalid Command/Sequence” error and status register bits SR.5 and SR.4 will be set to a “1.” Reliable buffered writes can only occur when V PEN = VPENH . If a buffered write is attempted while VPEN ≤ VPENLK , status register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding block lock-bit be reset. If a buffered write is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to “1.”
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4.9 Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, “Byte/Word Program Flowchart” on page 31). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when V CC and VPEN are valid. If a byte/word program is attempted while VPEN ≤ VPENLK , status register bits SR.4 and SR.3 will be set to “1.” Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/ word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to “1.”
4.10 Program Suspend Command
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set to “1”, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to V OH . Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to V OL . After the Program Resume command is written, the device automatically outputs status register data when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same V PEN and V CC levels used for programming) while in program suspend mode. Refer to Figure 9, “Program Suspend/Resume Flowchart” on page 32.
4.11 Set Read Configuration Command
This command is not support on this product. This device will default to the asynchronous page mode. If this command is given to the device it will not effect the operation of the device.
4.11.1 Read Configuration
Status register and identifier only support standard word/byte single read operations. Table 18. Read Configuration Register Definition
4.12 Configuration Command
on page 26 displays the possible STS configurations. modes, the STS pin pulses low with a typical pulse width of 250 ns. Read mode configuration effects reads from the flash array.
26 Preliminary
Table 19. Configuration Coding Definitions
4.13 Set Block Lock-Bit Commands
Bit command. This command is invalid while the WSM is running or the device is suspended. output or status register bit SR.7. until a new command is issued. V PENLK , lock-bit contents are protected against alteration. operation indicated by the given configuration is completed. 7–DQ 2 are reserved for future use. when a common interrupt service routine is desired.
28F128J3A, 28F640J3A, 28F320J3A Preliminary 27
4.14 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock- bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs status register data when read (see Figure 13 on page 36). The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can only occur when V CC and VPEN are valid. If a clear block lock-bits operation is attempted while V PEN ≤ VPENLK , SR.3 and SR.5 will be set to “1.” If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.
4.15 Protection Register Program Command
The 3 V olt Intel StrataFlash memory includes a 128-bit protection register that can be used to increase the security of a system design. For example, the number contained in the protection register can be used to “mate” the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
4.15.1 Reading the Protection Register
The protection register is read in the identification read mode. The device is switched to this mode by writing the Read Identifier command (90H). Once in this mode, read cycles from addresses shown in Table 20 or Table 21 retrieve the specified information. To return to read array mode, write the Read Array command (FFH).
4.15.2 Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the
28 Preliminary
address space will result in a status register error (program error bit SR.4 will be set to 1). (program error bit SR.4 and lock error bit SR.1 will be set to 1).
4.15.3 Locking the Protection Register
result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible. addressing). For x8 mode A0 is used (See Table 21 for x8 addressing). Figure 6. Protection Register Memory Map
4 Words
1 Word Lock
Table 20. Word-Wide Protection Register Addressing
0 F a c t o r y 10000001
1 F a c t o r y 10000010
2 F a c t o r y 10000011
3 F a c t o r y 10000100
4 U s e r 10000101
5 U s e r 10000110
6 U s e r 10000111
7 U s e r 10001000
Table 21. Byte-Wide Protection Register Addressing
1 F a c t o r y 10000001
2 F a c t o r y 10000010
3 F a c t o r y 10000010
4 F a c t o r y 10000011
5 F a c t o r y 10000011
6 F a c t o r y 10000100
7 F a c t o r y 10000100
8 U s e r 10000101
9 U s e r 10000101
30 Preliminary
Figure 7. Write to Buffer Flowchart
- Byte or word count values on DQ0 - DQ7 are loaded into the
= 00H to 1FH and for word mode are N = 0000H to 000FH.
- The device now outputs the status register when read (XSR is
- Write Buffer contents will be programmed at the device start
address or destination flash address.
- Align the start address on a Write Buffer boundary for
- The device aborts the Write to Buffer command if the current
address is outside of the original block address.
- The status register indicates an "improper command
with a Clear Status Register command.
- Toggling OE# (low to high to low) updates the status register.
Figure 8. Byte/Word Program Flowchart
- Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. after a sequence of programming operations. be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. implemeting lock-bit configuration.
32 Preliminary
Figure 9. Program Suspend/Resume Flowchart
Figure 10. Block Erase Flowchart
- The Erase Confirm byte must follow Erase Setup.
reset the device to read array mode.
34 Preliminary
Figure 11. Block Erase Suspend/Resume Flowchart
Figure 12. Set Block Lock-Bit Flowchart Repeat for subsequent lock-bit operations. a sequence of lock-bit set operations.
36 Preliminary
Figure 13. Clear Lock-Bit Flowchart
Figure 14. Protection Register Programming Flowchart Repeat for subsequent programming operations. Write FFH after the last program operation to reset device to read array mode. attempts are allowed by the Write State Machine.
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38 Preliminary
5.0 Design Considerations
5.1 Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE 2, OE#, and RP#) to accommodate multiple memory connections. This control provides for: a.Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable the device (see Table 2) while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2 STS and Block Erase, Program, and Lock-Bit Configuration
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. It is recommended that a 2.5k resister be used between STS# and V CCQ . In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS pin, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE 0, CE1, CE2, and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three V CC pins (these devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic capacitor between each of the device’s three VCC pins (this includes VCCQ ) and ground. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each Intel StrataFlash memory device. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed between VCC and GND at the array’s power supply connection. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
28F128J3A, 28F640J3A, 28F320J3A Preliminary 39
5.4 Input Signal Transitions - Reducing Overshoots and
Undershoots When Using Buffers or Transceivers As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications. (See “Absolute Maximum Ratings” on page 40.) Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light- drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For additional information, please refer to the AP-647 5 Volt Intel StrataFlash™ Memory Design Guide.
5.5 V CC , VPEN , RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# ≠ VIH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of t PLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = V IL clears the status register. The CUI latches commands issued by system software and is not altered by VPEN , CE0, CE1, or CE 2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO . VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK , the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. V PEN must be kept at or below VCC during VPEN transitions.
5.6 Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lock- bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for V CC voltages above VLKO when VPEN is active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving WE# to VIH or disabling the device will inhibit writes. The CUI’s two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled while RP# = V IL regardless of its control inputs.
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40 Preliminary
5.7 Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.
6.0 Electrical Specifications
6.1 Absolute Maximum Ratings
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC and VPEN pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins, VCC , and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Parameter Maximum Rating Temperature under Bias Expanded –25 °C to +85 °C Storage Temperature –65 °C to +125 °C Voltage On Any Pin –2.0 V to +5.0 V(1) Output Short Circuit Current 100 mA (2) NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design
6.2 Operating Conditions
6.3 Capacitance
- Sampled, not 100% tested.
Table 22. Temperature and VCC Operating Conditions
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42 Preliminary
6.4 DC Characteristics
Symbol Parameter Notes Typ Max Unit Test Conditions ILI Input and VPEN Load Current 1 ±1 µA VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND ILO Output Leakage Current 1 ±10 µA VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND ILO Output Leakage Current 1 ±10 µA VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND ICCS VCC Standby Current 1,2,3,4 50 120 µA CMOS Inputs, VCC = VCC Max, Device is enabled (see Table 2, “Chip Enable Truth Table” on page 7), RP# = VCCQ ± 0.2 V 0.71 2 mA TTL Inputs, VCC = VCC Max, Device is enabled (see Table 2), RP# = VIH ICCD VCC Power-Down Current 4 50 120 µA RP# = GND ± 0.2 V, IOUT (STS) = 0 mA ICCR VCC Page Mode Read Current 1,3,4 15 20 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 2) f = 5 MHz, IOUT = 0 mA 24 29 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 2) f = 33 MHz, I OUT = 0 mA ICCR VCC Byte Mode Read Current 1,3,4 40 50 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard word/byte single reads Device is enabled (see Table 2) f = 5 MHz, IOUT = 0 mA ICCW VCC Program or Set Lock-Bit Current 1,4,5 35 60 mA CMOS Inputs, V PEN = VCC 40 70 mA TTL Inputs, V PEN = VCC ICCE VCC Block Erase or Clear Block Lock-Bits Current 1,4,5 35 70 mA CMOS Inputs, V PEN = VCC 40 80 mA TTL Inputs, V PEN = VCC ICCWS ICCES VCC Program Suspend or Block Erase Suspend Current 1,4,6 10 mA Device is disabled (see Table 2)
- All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages
CC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
- Current values are specified over the temperature range (0 °C to 70 °C) and may increase slightly at –25 °C.
- Sampled, not 100% tested.
suspend mode, the device’s current draw is ICCR or ICCW .
- Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK , and not
guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max).
- Typically, VPEN is connected to VCC (2.7 V–3.6 V).
- Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed
in the range between VLKO (min) and VCC (min), and above VCC (max). output timing ends, at VCCQ /2 V (50% of VCCQ ). Input rise and fall times (10% to 90%) < 5 ns.
0.4 V VCCQ = VCCQ2/3 Min
0.2 V VCCQ = VCCQ2/3 Min
Figure 15. Transient Input/Output Reference Waveform for VCCQ = 3.0 V–3.6 V or
44 Preliminary
Figure 16. Transient Equivalent Testing Load Circuit
28F128J3A, 28F640J3A, 28F320J3A Preliminary 45
6.5 AC Characteristics — Read-Only Operations(1,2)
NOTES: CE X low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE 1, or CE2 that disables the device (see Table 2). 1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV -tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2) without impact on tELQV . 3. See Figures 14–16, Transient Input/Output Reference Waveform for VCCQ = 3.0 V –3.6 V or VCCQ = 2.7 V – 3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics. 4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (t APA ) will equal R2 (tAVQV ). Versions (All units in ns unless otherwise noted) # Sym Parameter Notes Min Max Min Max R1 t AVAV Read/Write Cycle Time
32 Mbit 110 110
64 Mbit 120 120
128 Mbit 150 150
R2 t AVQV Address to Output Delay R3 t ELQV CE X to Output Delay
32 Mbit 2 110 110
64 Mbit 2 120 120
128 Mbit 2 150 150
R4 t GLQV OE# to Non-Array Output Delay 2, 4 50 50 R5 t PHQV RP# High to Output Delay
32 Mbit 150 150
64 Mbit 180 180
128 Mbit 210 210
R6 t ELQX CE X to Output in Low Z 5 0 0 R7 t GLQX OE# to Output in Low Z 5 0 0 R8 t EHQZ CE X High to Output in High Z 5 55 55 R9 t GHQZ OE# High to Output in High Z 5 15 15 R10 t OH Output Hold from Address, CEX, or OE# Change, Whichever Occurs First 50 0 R11 t ELFL/tELFH CE X Low to BYTE# High or Low 5 10 10 R12 t FLQV/tFHQV BYTE# to Output Delay 1000 1000 R13 t FLQZ BYTE# to Output in High Z 5 1000 1000 R14 t EHEL CEx High to CEx Low 5 0 0 R15 t APA Page Address Access Time 5, 6 25 30 R16 t GLQV OE# to Array Output Delay 4 25 30
46 Preliminary
the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). For standard word/byte read operations, R15 (tAPA ) will equal R2 (tAVQV ). reads, query reads, or device identifier reads. Figure 17. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations
28F128J3A, 28F640J3A, 28F320J3A Preliminary 47
6.6 AC Characteristics — Write Operations(1,2)
NOTES: CE X low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE 1, or CE2 that disables the device (see Table 2). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics–Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (t WP ) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 5. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH ) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL . 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. V PEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). Versions Valid for All Speeds Unit # Symbol Parameter Notes Min Max W1 t PHWL (tPHEL ) RP# High Recovery to WE# (CE X) Going Low 3 1 µs W2 t ELWL (tWLEL )C E X (WE#) Low to WE# (CEX) Going Low 4 0 ns W3 t WP Write Pulse Width 4 70 ns W4 t DVWH (tDVEH ) Data Setup to WE# (CE X) Going High 5 50 ns W5 t AVWH (tAVEH ) Address Setup to WE# (CE X) Going High 5 55 ns W6 t WHEH (tEHWH )C E X (WE#) Hold from WE# (CEX) High 10 ns W7 t WHDX (tEHDX ) Data Hold from WE# (CE X) High 0 ns W8 t WHAX (tEHAX ) Address Hold from WE# (CE X) High 0 ns W9 t WPH Write Pulse Width High 6 30 ns W11 t VPWH (tVPEH )V PEN Setup to WE# (CEX) Going High 3 0 ns W12 t WHGL (tEHGL ) Write Recovery before Read 7 35 ns W13 t WHRL (tEHRL )W E # ( C E X) High to STS Going Low 8 500 ns W15 t QVVL VPEN Hold from Valid SRD, STS Going High 3,8,9 0 ns
28F128J3A, 28F640J3A, 28F320J3A
48 Preliminary
6.7 Block Erase, Program, and Lock-Bit Configuration
Performance(1,2,3) NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (t WHQV1 , tEHQV1 ) is 6.8 µs/byte (typical) 7. Effective per-word program time (tWHQV2 , tEHQV2 ) is 13.6 µs/word (typical) 8. Max values are measured at worst case temperature and VCC corner after 100k cycles # Sym Parameter Notes Typ Max Unit W16 Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) 4,5,6,7 218 654 µs W16 tWHQV3 tEHQV3 Byte Program Time (Using Word/Byte Program Command) 4 210 630 µs Block Program Time (Using Write to Buffer Command) 4 0.8 2.4 sec W16 tWHQV4 tEHQV4 Block Erase Time 4 1.0 5.0 sec W16 tWHQV5 tEHQV5 Set Lock-Bit Time 4 64 75 µs W16 tWHQV6 tEHQV6 Clear Block Lock-Bits Time 4 0.5 0.70 sec W16 tWHRH1 tEHRH1 Program Suspend Latency Time to Read 25 75 µs W16 tWHRH tEHRH Erase Suspend Latency Time to Read 26 35 µs
CE 1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#). a. VCC power-up and standby. b. Write block erase, write buffer, or program setup. c. Write block erase or write buffer confirm, or valid address and data. e. Read status register or query data. f. Write Read Array command. Figure 18. AC Waveform for Write Operations
50 Preliminary
NOTE: STS is shown in its default mode (RY/BY#).
- These specifications are valid for all product versions (packages and speeds).
- If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns. Figure 19. AC Waveform for Reset Operation
28F128J3A, 28F640J3A, 28F320J3A Preliminary 51
7.0 Ordering Information
NOTE: 1. These speeds are for either the standard asynchronous read access times or for the first access of a page- mode read sequence. VALID COMBINATIONS R C 2 8 F 1 2 8 J 3 A - 1 5 Package E = 56-Lead TSOP RC = 64-Ball Easy BGA Product line designator for all Intel ® Flash products Access Speed (ns)1
128 Mbit = 150
64 Mbit = 120
32 Mbit = 110
J = Intel ® StrataFlashTM memory, 2 bits-per-cell Device Density 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Voltage (VCC /VPEN ) 3 = 3 V/3 V Intel® 0.25 micron ETOX ™ VI Process Technology 56-Lead TSOP 64-Ball Easy BGA E28F128J3A-150 RC28F128J3A-150 E28F640J3A-120 RC28F640J3A-120 E28F320J3A-110 RC28F320J3A-110
28F128J3A, 28F640J3A, 28F320J3A
52 Preliminary
8.0 Additional Information
NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/ design/flash/isf. Order Number Document/Tool 298130 3 Volt Intel® StrataFlash™ Memory 28F128J3A, 28F640J3A, 320J3A Specification Update
290668 Intel® Persistent Storage Manager datasheet
292237 AP-689 Using Intel® Persistent Storage Manager
Note 3 AP-707 3 Volt Intel® StrataFlash™ Memory CPU Interface Design Guide 290606 5 Volt Intel® StrataFlash™ MemoryI28F320J5 and 28F640J5 datasheet 290608 3 Volt FlashFile™ Memory; 28F160S3 and 28F320S3 datasheet 290609 5 Volt FlashFile™ Memory; 28F160S5 and 28F320S5 datasheet 290429 5 Volt FlashFile™ Memory; 28F008SA datasheet 290598 3 Volt FlashFile™ Memory; 28F004S3, 28F008S3, 28F016S3 datasheet 290597 5 Volt FlashFile™ Memory; 28F004S5, 28F008S5, 28F016S5 datasheet
297859 AP-677 Intel® StrataFlash™ Memory Technology
292222 AP-664 Designing Intel® StrataFlash™ Memory into Intel® Architecture
292221 AP-663 Using the Intel® StrataFlash™ Memory Write Buffer
292218 AP-660 Migration Guide to 3 Volt Intel® StrataFlash™ Memory
292205 AP-647 5 Volt Intel® StrataFlash™ Memory Design Guide
292204 AP-646 Common Flash Interface (CFI) and Command Sets
292202 AP-644 Migration Guide to 5 Volt Intel® StrataFlash™ Memory
298161 Intel® Flash Memory Chip Scale Package User’s Guide
Note 4 Preliminary Mechanical Specification for Easy BGA Package