28F010 INTEL
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 290207-010 28F010 1024K (128K x 8) CMOS FLASH MEMORY Y Flash Electrical Chip-Erase Ð 1 Second Typical Chip-Erase Y Quick Pulse Programming Algorithm Ð1 0 ms Typical Byte-Program Ð 2 Second Chip-Program Y 100,000 Erase/Program Cycles Y 12.0V g5% V PP Y High-Performance Read Ð 65 ns Maximum Access Time Y CMOS Low Power Consumption Ð 10 mA Typical Active Current Ð5 0 mA Typical Standby Current Ð 0 Watts Data Retention Power Y Integrated Program/Erase Stop Timer Y Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface Y Noise Immunity Features Ð g10% V CC Tolerance Ð Maximum Latch-Up Immunity through EPI Processing Y ETOXTM Nonvolatile Flash Technology Ð EPROM-Compatible Process Base Ð High-Volume Manufacturing Experience Y JEDEC-Standard Pinouts Ð 32-Pin Plastic Dip Ð 32-Lead PLCC Ð 32-Lead TSOP (See Packaging Spec., Order Ý231369) Y Extended Temperature Options Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on- board during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases memory flexibility, while contributing to time and cost savings. The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel’s 28F010 is offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs. Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V V PP supply, the 28F010 performs 100,000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase algorithms. Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low power consumption, and immunity to noise. Its 65 nanosecond access time provides no-WAIT-state perform- ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 mA trans- lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address and data pins, from b1V to V CC a 1V. With Intel’s ETOX process base, the 28F010 builds on years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness.
Figure 1. 28F010 Block Diagram Table 1. Pin Description latched during a write cycle. are disabled. Data is internally latched during a write cycle. during a read cycle. OE Ý is active low. WEÝ INPUT WRITE ENABLE: Controls writes to the control register and the array. Note: With V PP s 6.5V, memory contents cannot be altered. register, erasing the entire array, or programming bytes in the array.
Figure 2. 28F010 Pin Configurations
APPLICATIONS
The 28F010 flash memory provides nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. These fea- tures make the 28F010 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and data-tables are required, the 28F010’s reprogrammability and non- volatility make it the obvious and ideal replacement for EPROM. Primary applications and operating systems stored in flash eliminate the slow disk-to-DRAM download process. This results in dramatic enhancement of performance and substantial reduction of power consumption Ð a consideration particularly impor- tant in portable equipment. Flash memory increases flexibility with electrical chip erasure and in-system update capability of operating systems and applica- tion code. With updatable code, system manufactur- ers can easily accommodate last-minute changes as revisions are made. In diskless workstations and terminals, network traf- fic reduces to a minimum and systems are instant- on. Reliability exceeds that of electromechanical media. Often in these environments, power interrup- tions force extended re-boot periods for all net- worked terminals. This mishap is no longer an issue if boot code, operating systems, communication pro- tocols and primary applications are flash-resident in each terminal. For embedded systems that rely on dynamic RAM/ disk for main system memory or nonvolatile backup storage, the 28F010 flash memory offers a solid state alternative in a minimal form factor. The 28F010 provides higher performance, lower power consumption, instant-on capability, and allows an ‘‘execute in place’’ memory hierarchy for code and data table reading. Additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail. The need for code updates pervades all phases of a system’s life Ð from prototyping to system manufac- ture to after-sale service. The electrical chip-erasure and reprogramming ability of the 28F010 allows in- circuit alterability; this eliminates unnecessary han- dling and less-reliable socketed connections, while adding greater test, manufacture, and update flexi- bility. Material and labor costs associated with code changes increases at higher levels of system inte- gration Ð the most costly being code updates after sale. Code ‘‘bugs’’, or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code requires the re- moval of EPROM components or entire boards. With the 28F010, code updates are implemented locally via an edge-connector, or remotely over a commun- cation link. For systems currently using a high-density static RAM/battery configuration for data accumulation, flash memory’s inherent nonvolatility eliminates the need for battery backup. The concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a considerable cost advantage over static RAM. Flash memory’s electrical chip erasure, byte pro- grammability and complete nonvolatility fit well with data accumulation and recording needs. Electrical chip-erasure gives the designer a ‘‘blank slate’’ in which to log or record data. Data can be periodically off-loaded for analysis and the flash memory erased producing a new ‘‘blank slate’’. A high degree of on-chip feature integration simpli- fies memory-to-processor interfacing. Figure 4 de- picts two 28F010s tied to the 80C186 system bus. The 28F010’s architecture minimizes interface cir- cuitry needed for complete in-circuit updates of memory contents. The outstanding feature of the TSOP (Thin Small Outline Package) is the 1.2 mm thickness. With stan- dard and reverse pin configurations, TSOP reduces the number of board layers and overall volume nec- essary to layout multiple 28F010s. TSOP is particu- larly suited for portable equipment and applications requiring large amounts of flash memory. Figure 3 illustrates the TSOP Serpentine layout. With cost-effective in-system reprogramming, ex- tended cycling capability, and true nonvolatility, the 28F010 offers advantages to the alternatives: EPROMs, EEPROMs, battery backed static RAM, or disk. EPROM-compatible read specifications, straight-forward interfacing, and in-circuit alterability offers designers unlimited flexibility to meet the high standards of today’s designs.
Figure 3. TSOP Serpentine Layout
Figure 4. 28F010 in a 80C186 System put data for erase and program verification. ceiving the appropriate verify or reset command.
Table 2. 28F010 Bus Operations
- Refer to DC Characteristics. When V PP e VPPL memory contents can be read but not written or erased.
- Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
ID is the Intelligent Identifier high voltage. Refer to DC Characteristics.
- Read operations with V PP e VPPH may access array data or the Intelligent Identifier codes.
- With V PP at high voltage, the standby current equals I CC a IPP (standby).
- Refer to Table 3 for valid Data-In during a write operation.
mode, the memory contents cannot be altered. of the processor-memory interface. vice selection. Refer to AC read timing waveforms. operation can only access the array data. until the operation is terminated.
the device code, respectively. address 0001H outputs the device code (B4H). data information needed to execute the command. dard microprocessor write timings are used. abling read-only operations. Table 3. Command Definitions
- Bus operations are defined in Table 2.
e Identifier address: 00H for manufacturer code, 01H for device code. EA e Erase Address: Address of memory location to be read during erase verify. PA e Program Address: Address of memory location to be programmed. Addresses are latched on the falling edge of the WE Ý pulse.
- ID e Identifier Data: Data read from location IA during device identification (Mfr e 89H, Device e B4H).
EVD e Erase Verify Data: Data read from location EA during erase verify. PD e Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE Ý. PVD e Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
- Following the Read int eligent ID command, two read operations access manufacturer and device codes.
- Figure 6 illustrates the Quick Erase Algorithm.
- Figure 5 illustrates the Quick Pulse Programming Algorithm.
- The second bus cycle must be followed by the desired command register write.
While V PP is high, for erasure and programming, memory contents can be accessed via the read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register con- tents are altered. The default contents of the register upon V PP pow- er-up is 00H. This default value ensures that no spu- rious alteration of memory contents occurs during the V PP power transition. Where the V PP supply is hard-wired to the 28F010, the device powers-up and remains enabled for reads until the command-regis- ter contents are changed. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Intelligent Identifier Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be ac- cessible while the device resides in the target sys- tem. PROM programmers typically access signature codes by raising A9 to a high voltage. However, mul- tiplexing high voltage onto address lines is not a de- sired system-design practice. The 28F010 contains an Intelligent Identifier opera- tion to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the command register. Following the com- mand write, a read cycle from address 0000H re- trieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of B4H. To terminate the operation, it is necessary to write another valid command into the register. Set-up Erase/Erase Commands Set-up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip-erasure, the erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the WE Ý pulse and terminates with the rising edge of the next WE Ý pulse (i.e., Erase-Verify Command). This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, chip-erasure can only occur when high voltage is applied to the V PP pin. In the absence of this high voltage, memory contents are protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Erase-Verify Command The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the WE Ý pulse. The register write terminates the erase operation with the rising edge of its WE Ý pulse. The 28F010 applies an internally-generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. In the case where the data read is not FFH, another erase operation is performed. (Refer to Set-up Erase/Erase). Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is com- plete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g. Program Set-up) to the command register. Figure 6, the Quick Erase algorithm, illus- trates how commands and bus operations are com- bined to perform electrical erasure of the 28F010. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Set-up Program/Program Commands Set-up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register performs the set-up operation. Once the program set-up operation is performed, the next WE Ý pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE Ý pulse. Data is internally latched on the rising edge of the WE Ý pulse. The rising edge of WE Ý also begins the pro- gramming operation. The programming operation terminates with the next rising edge of WE Ý, used to write the program-verify command. Refer to AC Programming Characteristics and Waveforms for specific timing parameters.
The 28F010 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at ran- dom. Following each programming operation, the byte just programmed must be verified. The program-verify operation is initiated by writing C0H into the command register. The register write terminates the programming operation with the ris- ing edge of its WE Ý pulse. The program-verify oper- ation stages the device for verification of the byte last programmed. No new address information is latched. The 28F010 applies an internally-generated margin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison between the programmed byte and true data means that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 5, the 28F010 Quick Pulse Programming algorithm, il- lustrates how commands are combined with bus op- erations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. Reset Command A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. Howev- er, redundancy requires that cell size be doubledÐ an expensive solution. Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric field is one-tenth that of common EEPROMs, minimizing the probabili- ty of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 MV/cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failure. The 28F010 is capable or 100,000 program/erase cycles. The device is programmed and erased using Intel’s Quick Pulse Programming and Quick Erase algorithms. Intel’s algorithmic approach uses a se- ries of operations (pulses), along with byte verifica- tion, to completely and reliably erase and program the device. For further information, see Reliability Report RR-60. QUICK PULSE PROGRAMMING ALGORITHM The Quick Pulse Programming algorithm uses pro- gramming operations of 10 ms duration. Each opera- tion is followed by a byte verification to determine when the addressed byte has been successfully pro- grammed. The algorithm allows for up to 25 pro- gramming operations per byte, although most bytes verify on the first or second operation. The entire sequence of programming and byte verification is performed with V PP at high voltage. Figure 5 illus- trates the Quick Pulse Programming algorithm. QUICK ERASE ALGORITHM Intel’s Quick Erase algorithm yields fast and reliable electrical erasure of memory contents. The algo- rithm employs a closed-loop flow, similar to the Quick Pulse Programming algorithm, to simulta- neously remove charge from all bits in the array. Erasure begins with a read of memory contents. The 28F010 is erased when shipped from the factory. Reading FFH data from the device would immedi- ately be followed by device programming. For devices being erased and reprogrammed, uni- form and reliable erasure is ensured by first pro- gramming all bits in the device to their charged state (Data e 00H). This is accomplished, using the Quick Pulse Programming algorithm, in approximately two seconds. Erase execution then continues with an initial erase operation. Erase verification (data e FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is en- countered. With each erase operation, an increasing number of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next erase operation, verification starts at that stored ad- dress location. Erasure typically occurs in one sec- ond. Figure 6 illustrates the Quick Erase algorithm.
- See DC Characteristics for the value of V
- Program Verify is only performed after byte program-
al) after the register is written with the Read command.
- Refer to principles of operation.
- CAUTION: The algorithm MUST BE FOLLOWED
Figure 5. 28F010 Quick Pulse Programming Algorithm
- See DC Characteristics for the value of V PPH and
- Erase Verify is performed only after chip-erasure. A
the register is written with the read command.
- Refer to principles of operation.
- CAUTION: The algorithm MUST BE FOLLOWED
Figure 6. 28F010 Quick Erase Algorithm
determine the magnitudes of these peaks. selection will suppress transient voltage peaks. charge to the smaller capacitors as needed. crease V PP voltage spikes and overshoots. CC voltages above V LKO when V PP is active. mand write, driving either to V IH will inhibit writes. power dissipated when updating the 28F010. Table 4. 28F010 Typical Update Power Dissipation
- Formula to calculate typical Program/Program Verify Power e [VPP c Ý Bytes c typical Ý Prog Pulses (t WHWH1 c IPP2
- Formula to calculate typical Erase/Erase Verify Power e [VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c
Ý Bytes)] a [VCC (ICC3 typical c tERASE typical a ICC5 typical c tWHGL c Ý Bytes)].
- One Complete Cycle e Array Preprogram a Array Erase a Program.
- ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
ABSOLUTE MAXIMUM RATINGS * Operating Temperature During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 §Ct o a70§C(1) During Erase/Program ÀÀÀÀÀÀÀÀÀ0 §Ct o a70§C(1) Operating Temperature During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C(2) During Erase/Program ÀÀÀÀÀÀ b40§Ct o a85§C(2) Temperature Under Bias ÀÀÀÀÀÀÀ b10§Ct o a80§C(1) Temperature Under Bias ÀÀÀÀÀÀÀ b50§Ct o a95§C(2) Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a125§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b2.0V to a7.0V(3) Voltage on Pin A 9 with Respect to Ground ÀÀÀÀÀÀÀ b2.0V to a13.5V(3, 4) VPP Supply Voltage with Respect to Ground During Erase/Program ÀÀÀÀ b2.0V to a14.0V(3, 4) VCC Supply Voltage with Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b2.0V to a7.0V(3) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (5) NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Parameter Limits Unit Min Max TA Operating Temperature (1) 07 0 §C TA Operating Temperature (2) b40 a85 §C VCC VCC Supply Voltage (10%) (6) 4.50 5.50 V VCC VCC Supply Voltage (5%) (7) 4.75 5.25 V NOTES: 1. Operating Temperature is for commercial product as defined by this specification. 2. Operating Temperature is for extended temperature products as defined by this specification. 3. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V for periods less than 20 ns. Maximum DC voltage on output pins is V CC a 0.5V, which may overshoot to V CC a 2.0V for periods less than 20 ns. 4. Maximum DC voltage on A 9 or V PP may overshoot to a14.0V for periods less than 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. 6. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics. DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ILI Input Leakage Current 1 g1.0 mAV CC e VCC Max VIN e VCC or V SS ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or V SS ICCS VCC Standby Current 1 0.3 1.0 mA V CC e VCC Max CEÝ e VIH ICC1 VCC Active Read Current 1 10 30 mA V CC e VCC Max, CE Ý e VIL f e 6 MHz, I OUT e 0m A
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products (Continued) Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ICC2 VCC Programming Current 1, 2 1.0 10 mA Programming in Progress ICC3 VCC Erase Current 1, 2 5.0 15 mA Erasure in Progress ICC4 VCC Program Verify Current 1, 2 5.0 15 mA V PP e VPPH Program Verify in Progress ICC5 VCC Erase Verify Current 1, 2 5.0 15 mA V PP e VPPH Erase Verify in Progress IPPS VPP Leakage Current 1 g10 mAV PP s VCC IPP1 VPPRead Current 1 90 200 mAV PP l VCC or Standby Current g10.0 V PP s VCC IPP2 VPP Programming Current 1, 2 8.0 30 mA V PP e VPPH Programming in Progress IPP3 VPP Erase Current 1, 2 6.0 30 mA V PP e VPPH Erasure in Progress IPP4 VPP Program Verify Current 1, 2 2.0 5.0 mA V PP e VPPH Program Verify in Progress IPP5 VPP Erase Verify Current 1, 2 2.0 5.0 mA V PP e VPPH Erase Verify in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage 2.4 V V CC e VCC Min IOH eb 2.5 mA VID A9 Intelligent Identifer Voltage 11.50 13.00 V IID A9 Intelligent Identifier Current 1, 2 90 200 mAA 9 e VID VPPL VPP during Read-Only 0.00 6.5 V NOTE: Erase/Program are Operations Inhibited when V PP e VPPL VPPH VPP during Read/Write 11.40 12.60 V Operations VLKO VCC Erase/Write Lock Voltage 2.5 V DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ILI Input Leakage Current 1 g1.0 mAV CC e VCC Max VIN e VCC or V SS ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or V SS ICCS VCC Standby Current 1 50 100 mAV CC e VCC Max CEÝ e VCC g0.2V ICC1 VCC Active Read Current 1 10 30 mA V CC e VCC Max, CE Ý e VIL f e 6 MHz, I OUT e 0m A
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products (Continued) Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ICC2 VCC Programming Current 1, 2 1.0 10 mA Programming in Progress ICC3 VCC Erase Current 1, 2 5.0 15 mA Erasure in Progress ICC4 VCC Program Verify Current 1, 2 5.0 15 mA V PP e VPPH, Program Verify in Progress ICC5 VCC Erase Verify Current 1, 2 5.0 15 mA V PP e VPPH, Erase Verify in Progress IPPS VPP Leakage Current 1 g10 mAV PP s VCC IPP1 VPP Read Current, ID 1 90 200 mAV PP l VCC Current or Standby Current g10 V PP s VCC IPP2 VPP Programming 1, 2 8.0 30 mA V PP e VPPH Current Programming in Progress IPP3 VPP Erase Current 1, 2 6.0 30 mA V PP e VPPH Erasure in Progress IPP4 VPP Program Verify 1, 2 2.0 5.0 mA V PP e VPPH, Program Current Verify in Progress IPP5 VPP Erase Verify 1, 2 2.0 5.0 mA V PP e VPPH, Erase Current Verify in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage 0.85 V CC V VCC e VCC Min, I OH eb 2.5 mA VOH2 VCC b 0.4 V CC e VCC Min, I OH eb 100 mA VID A9 Intelligent Identifier 11.50 13.00 V Voltage IID A9 Intelligent Identifier 1, 2 90 200 mAA 9 e VID Current VPPL VPP during Read-Only 0.00 6.5 V NOTE: Erase/Programs are Operations Inhibited when V PP e VPPL VPPH VPP during Read/Write 11.40 12.60 V Operations VLKO VCC Erase/Write Lock 2.5 V Voltage
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐExtended Temperature Products Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ILI Input Leakage Current 1 g1.0 mAV CC e VCC Max VIN e VCC or V SS ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or V SS ICCS VCC Standby Current 1 0.3 1.0 mA V CC e VCC Max CEÝ e VIH ICC1 VCC Active Read Current 1 10 30 mA V CC e VCC Max, CE Ý e VIL f e 6 MHz, I OUT e 0m A ICC2 VCC Programming Current 1, 2 1.0 30 mA Programming in Progress ICC3 VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress ICC4 VCC Program Verify Current 1, 2 5.0 30 mA V PP e VPPH Program Verify in Progress ICC5 VCC Erase Verify Current 1, 2 5.0 30 mA V PP e VPPH Erase Verify in Progress IPPS VPP Leakage Current 1 g10 mAV PP s VCC IPP1 VPP Read Current 1 90 200 mAV PP l VCC or Standby Current g10.0 V PP s VCC IPP2 VPP Programming Current 1, 2 8.0 30 mA V PP e VPPH Programming in Progress IPP3 VPP Erase Current 1, 2 6.0 30 mA V PP e VPPH Erasure in Progress IPP4 VPP Program Verify Current 1, 2 2.0 5.0 mA V PP e VPPH Program Verify in Progress IPP5 VPP Erase Verify Current 1, 2 2.0 5.0 mA V PP e VPPH Erase Verify in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage 2.4 V V CC e VCC Min IOH eb 2.5 mA VID A9 Intelligent Identifer Voltage 11.50 13.00 V IID A9 Intelligent Identifier Current 1, 2 90 500 mAA 9 e VID VPPL VPP during Read-Only 0.00 6.5 V NOTE: Erase/Program are Operations Inhibited when V PP e VPPL VPPH VPP during Read/Write 11.40 12.60 V Operations VLKO VCC Erase/Write Lock Voltage 2.5 V
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature Products Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max ILI Input Leakage 1 g1.0 mAV CC e VCC Max Current V IN e VCC or V SS ILO Output Leakage 1 g10 mAV CC e VCC Max Current V OUT e VCC or V SS ICCS VCC Standby 1 50 100 mAV CC e VCC Max Current CE Ý e VCC g0.2V ICC1 VCC Active Read 1 10 30 mA V CC e VCC Max, CE Ý e VIL Current f e 10 MHz, I OUT e 0m A ICC2 VCC Programming 1, 2 1.0 10 mA Programming in Progress Current ICC3 VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress ICC4 VCC Program Verify 1, 2 5.0 30 mA V PP e VPPH Current Program Verify in Progress ICC5 VCC Erase Verify 1, 2 5.0 30 mA V PP e VPPH Current Erase Verify in Progress IPPS VPP Leakage Current 1 g10 mAV PP s VCC IPP1 VPP Read Current, 1 90 200 mAV PP l VCC ID Current or g10 V PP s VCCStandby Current IPP2 VPP Programming 1, 2 8.0 30 mA V PP e VPPH Current Programming in Progress IPP3 VPP Erase Current 1, 2 6.0 30 mA V PP e VPPH Erasure in Progress IPP4 VPP Program Verify 1, 2 2.0 5.0 mA V PP e VPPH Current Program Verify in Progress IPP5 VPP Erase Verify 1, 2 2.0 5.0 mA V PP e VPPH Current Erase Verify in Progress VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage 0.85 V CC V VCC e VCC Min IOH eb 2.5 mA VOH2 VCC b 0.4 V CC e VCC Min IOH eb 100 mA VID A9 Intelligent Identifer 11.50 13.00 V Voltage IID A9 Intelligent Identifier 1, 2 90 500 mAA 9 e VID Current
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature Products (Continued) Symbol Parameter Notes Limits Unit Test Conditions Min Typical (4) Max VPPL VPP during Read-Only 0.00 6.5 V NOTE: Erase/Programs are Operations Inhibited when V PP e VPPL VPPH VPP during Read/Write 11.40 12.60 V Operations VLKO VCC Erase/Write Lock 2.5 V Voltage CAPACITANCE TA e 25§C, f e 1.0 MHz Symbol Parameter Notes Limits Unit Conditions Min Max CIN Address/Control Capacitance 3 8 pF V IN e 0V COUT Output Capacitance 3 12 pF V OUT e 0V NOTES: are valid for all product versions (packages and speeds). 2. Not 100% tested: characterization data available. 3. Sampled, not 100% tested. 4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
WAVEFORM(1) 290207–7 AC test inputs are driven at V OH (2.4 V TTL) for a Logic ‘‘1’’ and V OL (0.45 V TTL) for a Logic ‘‘0’’. Input timing begins at V IH (2.0 V TTL) and V IL (0.8 V TTL). Output tim- ing ends at V IH and V IL. Input rise and fall times (10% to 90%) k10 ns. HIGH SPEED AC TESTING INPUT/OUTPUT WAVEFORM(2) 290207–8 AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0’’. Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) k10 ns. AC TESTING LOAD CIRCUIT (1) CL e 100 pF CL includes Jig Capacitance 290207–22 RL e 3.3 K X HIGH SPEED AC TESTING LOAD CIRCUIT (2) CL e 30 pF CL includes Jig Capacitance 290207–23 RL e 3.3 K X AC TEST CONDITIONS (1) Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.45V and 2.4V Input Timing Reference Level ÀÀÀÀÀÀÀ0.8V and 2.0V Output Timing Reference Level ÀÀÀÀÀÀ0.8V and 2.0V Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ100 pF HIGH-SPEED AC TEST CONDITIONS (2) Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.0V and 3.0V Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V Output Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30 pF NOTES: 1. Testing characteristics for 28F010-65 in standard configuration, and 28F010-90, 28F010-120, and 28F010-150. 2. Testing characteristics for 28F010-65 in high speed configuration.
AC CHARACTERISTICSÐRead Only OperationsÐCommercial and Extended Temperature Products Versions VCC g 5% 28F010-65 (4) UnitVCC g 10% 28F010-65 (5) 28F010-90(5) 28F010-120(5) 28F010-150(5) Symbol Characteristic Notes Min Max Min Max Min Max Min Max Min Max tAVAV/tRC Read Cycle Time 65 70 90 120 150 ns tELQV/tCE CEÝ Access Time 65 70 90 120 150 ns tAVQV/tACC Address Access Time 65 70 90 120 150 ns tGLQV/tOE OEÝ Access Time 25 28 35 50 55 ns tELQX/tLZ CEÝ to Low Z 2, 3 0 0 0 0 0 ns tEHQZ Chip Disable to Output 2 35 40 45 55 55 ns in High Z tGLQX/tOLZ OEÝ to Output 2, 3 0 0 0 0 0 ns in Low Z tGHQZ/tDF Output Disable to Output 2 30 30 30 30 35 ns in High Z tOH Output Hold from Address, 1, 2 0 0 0 0 0 ns CE Ý,o rO E Ý Change tWHGL Write Recovery Time 6 6 6 6 6 ms before Read NOTES: 1. Whichever occurs first. 2. Sampled, not 100% tested. 3. Guaranteed by design. 4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
Figure 7. AC Waveforms for Read Operations
AC CHARACTERISTICSÐWrite/Erase/Program Only Operations (1)Ð Commercial and Extended Temperature Products Versions VCC g 5% 28F010-65 (4) UnitVCC g 10% 28F010-65 (5) 28F010-90(5) 28F010-120(5) 28F010-150(5) Symbol Characteristic Notes Min Max Min Max Min Max Min Max Min Max tAVAV/tWC Write Cycle Time 65 70 90 120 150 ns tAVWL/tAS Address Set-Up Time 0 0 0 0 0 ns tWLAX/tAH Address Hold Time 40 40 40 40 40 ns 65 5 tDVWH/tDS Data Set-Up Time 40 40 40 40 40 ns 65 5 tWHDX/tDH Data Hold Time 10 10 10 10 10 ns tWHGL Write Recovery Time 6 6 6 6 6 ms before Read tGHWL Read Recovery Time 2 0 0 0 0 0 ns before Write tELWL/tCS Chip Enable Set-Up Time 15 15 15 15 15 ns before Write tWHEH/tCH Chip Enable Hold Time 0 0 0 0 0 ns tWLWH/tWP Write Pulse Width 40 40 40 60 60 ns 65 5 tWHWL/tWPH Write Pulse Width High 20 20 20 20 20 ns tWHWH1 Duration of Programming 3 10 10 10 10 10 ms Operation Operation tVPEL VPP Set-Up Time to 2 1 1 1 1 1 ms Chip Enable Low NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Guaranteed by design. 3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics. 6. Minimum specification for Extended Temperature product.
Figure 12. AC Waveforms for Programming Operations
Figure 13. AC Waveforms for Erase Operations
AC CHARACTERISTICSÐAlternative CE Ý-Controlled WritesÐCommercial and Extended Temperature Versions VCC g 5% 28F010-65 (2, 4) UnitVCC g 10% 28F010-65 (5) 28F010-90(5) 28F010-120(5) 28F010-150(5) Symbol Characteristic Notes Min Max Min Max Min Max Min Max Min Max tAVAV Write Cycle Time 65 70 90 120 150 ns tAVEL Address Set-Up Time 0 0 0 0 0 ns tELAX Address Hold Time 45 45 45 55 55 ns 66 0 tDVEH Data Set-Up Time 35 35 35 45 45 ns 65 0 tEHDX Data Hold Time 10 10 10 10 10 ns tEHGL Write Recovery Time 6 6 6 6 6 ms before Read tGHWL Read Recovery Time 2 0 0 0 0 0 ns before Write tWLEL Write Enable Set-Up Time 0 0 0 0 0 ns before Chip Enable tEHWH Write Enable Hold Time 0 0 0 0 0 ns tELEH Write Pulse Width 45 45 45 70 70 ns 66 0 tEHEL Write Pulse Width High 20 20 20 20 20 ns tEHEH1 Duration of Programming 3 10 10 10 10 10 ms Operation Operation tVPEL VPP Set-Up Time to Chip 2 1 1 1 1 1 ms Enable Low NOTE: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Guaranteed by design. 3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics. 6. Minimum specification for Extended Temperature product.
ERASE AND PROGRAMMING PERFORMANCE Parameter Notes Min Typical Max Unit Chip Erase Time 1, 3, 4 1 10 Sec Chip Program Time 1, 2, 4 2 12.5 Sec NOTES: 1. ‘‘Typicals’’ are not guaranteed, but based on samples from production lots. Data taken at 25 §C, 12.0V V PP. 2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program a 6 msec write recovery), while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. Excludes 00H programming prior to erasure. 4. Excludes system level overhead.
Alternative CE Ý-Controlled Write Timings also apply to erase operations. Figure 14. Alternate AC Waveforms for Programming Operations
ORDERING INFORMATION
290207–20 VALID COMBINATIONS: P28F010-65 N28F010-65 TN28F010-90 P28F010-90 N28F010-90 P28F010-120 N28F010-120 P28F010-150 N28F010-150 E28F010-65 F28F010-65 TE28F010-90 E28F010-90 F28F010-90 TF28F010-90 E28F010-120 F28F010-120 E28F010-150 F28F010-150 ADDITIONAL INFORMATION Order Number ER-20, ‘‘ETOX Flash Memory Technology’’ 294005 ER-24, ‘‘Intel Flash Memory’’ 294008 ER-28, ‘‘ETOX III Flash Memory Technology’’ 294012 RR-60, ‘‘ETOX Flash Memory Reliability Data Summary’’ 293002 AP-316, ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’ 292046 AP-325 ‘‘Guide to Flash Memory Reprogramming’’ 292059
REVISION HISTORY
007 Removed 200 ns Speed Bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000 Clarified AC and DC Test Conditions Added ‘‘dimple’’ to F TSOP Package Corrected Serpentine Layout
008 Corrected AC Waveforms
Added Extended Temperature Options
009 Added 28F010-65 and 28F010-90 speeds
Revised Symbols, i.e., CE ,O E , etc. to CE Ý,O E Ý, etc.
010 Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table Textual Changes or Edits Corrected Erase/Program Times