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SST27SF256 SST

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©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 The SST logo and SuperFlash are registered trademarks of Silicon Storage T echnology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet

256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)

Many-Time Programmable Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 FEATURES:

Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8 4.5-5.5V Read Operation Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) Fast Read Access Time – 70 ns – 90 ns Fast Byte-Program Operation – Byte-Program Time: 20 µs (typical) – Chip Program Time: 0.7 seconds (typical) for SST27SF256 1.4 seconds (typical) for SST27SF512 2.8 seconds (typical) for SST27SF010 5.6 seconds (typical) for SST27SF020 Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) TTL I/O Compatibility JEDEC Standard Byte-wide EPROM Pinouts Packages Available – 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 28-pin PDIP for SST27SF256/512 – 32-pin PDIP for SST27SF010/020 PRODUCT DESCRIPTION The SST27SF256/512/010/020 are a 32K x8 / 64K x8 / 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external pro- grammer with a 12 volt power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Byte-Program, the SST27SF256/512/010/020 provide a Byte-Program time of 20 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST27SF256/512/010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27SF256/512 are offered in 32-pin PLCC, 32-pin TSOP , and 28-pin PDIP packages. The SST27SF010/020 are offered in 32-pin PDIP , 32-pin PLCC and 32-pin TSOP packages. See Figures 1, 2, and 3 for pinouts. Device Operation The SST27SF256/512/010/020 are a low cost flash solu- tion that can be used to replace existing UV-EPROM, OTP , and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry stan- dard EPROM products. In addition to EPROM functionality, these devices also support electrical erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the SST27SF256/512/010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (T CE ). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least T CE - TOE . When the CE# pin is high, the chip is deselected and a typical standby current of 10 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Byte-Program Operation The SST27SF256/512/010/020 are programmed by using an external programmer. The programming mode for SST27SF256/010/020 is activated by asserting 12V (±5%) SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories

256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 on VPP pin, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. The programming mode for SST27SF512 is acti- vated by asserting 12V (±5%) on OE#/V PP pin, VDD = 5V (±5%), and VIL on CE# pin. These devices are pro- grammed byte-by-byte with the desired data at the desired address using a single pulse (CE# pin low for SST27SF256/512 and PGM# pin low for SST27SF010/ 020) of 20 µs. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. Chip-Erase Operation The only way to change a data from a “0” to “1” is by electri- cal erase that changes every bit in the device to “1”. Unlike traditional EPROMs, which use UV light to do the Chip- Erase, the SST27SF256/512/010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (CE# pin low for SST27SF256/512 and PGM# pin for SST27SF010/020). In order to activate the Erase mode for SST27SF256/010/020, the 12V (±5%) is applied to V PP and A9 pins, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. In order to activate Erase mode for SST27SF512, the 12V (±5%) is applied to OE#/V PP and A9 pins, VDD = 5V (±5%), and VIL on CE# pin. All other address and data pins are “don’t care”. The falling edge of CE# (PGM# for SST27SF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figures 13, 14, and 15 for the flowcharts. Product Identification Mode The Product Identification mode identifies the devices as the SST27SF256, SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF256/010/020, the programming equip- ment must force V H (12V±5%) on address A9 with VPP pin at VDD (5V±10%) or VSS. To activate this mode for SST27SF512, the programming equipment must force VH (12V±5%) on address A9 with OE#/VPP pin at VIL. Two identifier bytes may then be sequenced from the device outputs by toggling address line A 0. For details, see Tables 3, 4, and 5 for hardware operation. TABLE 1: P RODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST27SF256 0001H A3H SST27SF512 0001H A4H SST27SF010 0001H A5H SST27SF020 0001H A6H T1.1 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 Y -Decoder I/O Buffers 502 ILL B1.1 Address Buffer X-Decoder DQ 7 - DQ0 A14 - A0 OE# CE# VPP SuperFlash Memory Control Logic FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256 Y -Decoder I/O Buffers 502 ILL B2.1 Address Buffer X-Decoder DQ 7 - DQ0 A15 - A0 OE#/V PP CE# SuperFlash Memory Control Logic FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF512 Y -Decoder I/O Buffers 502 ILL B3.2 Address Buffer X-Decoder DQ 7 - DQ0 AMS - A0 OE# CE# SuperFlash Memory Control Logic PGM# VPP AMS = A17 for SST27SF020, A16 for SST27SF010 FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010/020

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 1: P IN ASSIGNMENTS FOR 32-PIN PLCC 502 ILL F02c.2 SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256 SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256 NC DQ0 NC DQ0 DQ0 DQ0 A11 NC OE# A10 CE# DQ7 DQ6 A11 NC OE#/V PP A10 CE# DQ7 DQ6 A14 A13 A11 OE# A10 CE# DQ7 A14 A13 A11 OE# A10 CE# DQ7 4 3 2 1 32 31 30 A7 A12 VPP NC VDD A14 A13 A12 A15 NC VDD A14 A13 A12 A15 A16 VPP VDD PGM# NC A12 A15 A16 VPP VDD PGM# A17 32-pin PLCC Top View 14 15 16 17 18 19 20 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 2: P IN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM ) FIGURE 3: P IN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP 502 ILL F01.1 A11 A13 A14 NC NC VDD VPP NC NC A12 A11 A13 A14 NC NC VDD NC NC A15 A12 A11 A13 A14 NC PGM# VDD VPP A16 A15 A12 A11 A13 A14 A17 PGM# VDD VPP A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE#/V PP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 Standard Pinout Top View Die Up SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256 32-pin PDIP Top View VPP A16 A15 A12 DQ0 DQ1 DQ2 VSS VPP A16 A15 A12 DQ0 DQ1 DQ2 VSS VDD PGM# NC A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# A17 A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 502 ILL F02b.1 SST27SF010 SST27SF010SST27SF020 SST27SF020 28-pin PDIP Top View VPP A12 DQ0 DQ1 DQ2 VSS A15 A12 DQ0 DQ1 DQ2 VSS VDD A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD A14 A13 A11 OE#/V PP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 502 ILL F02a.1 SST27SF512SST27SF256SST27SF512 SST27SF256

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 TABLE 2: P IN DESCRIPTION Symbol Pin Name Functions AMS 1-A0 Address Inputs To provide memory addresses DQ 7-DQ 0 Data Input/output To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low OE# Output Enable For SST27SF256/010/020, to gate the data output buffers during Read operation OE#/V PP Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage pin during Chip-Erase and programming operation VPP Power Supply for Program or Erase For SST27SF256/010/020, high voltage pin during Chip-Erase and programming opera- tion 12V (±5%) VDD Power Supply To provide 5.0V supply (±10%) VSS Ground NC No Connection Unconnected pins. T2.3 502 1. AMS = Most significant address AMS = A14 for SST27SF256, A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% TABLE 3: O PERATION MODES SELECTION FOR SST27SF256 Mode CE# OE# V PP A 9 DQ Address Read V IL VIL VDD or VSS AIN D OUT AIN Output Disable V IL VIH VDD or VSS XH i g h Z X Byte-Program V IL VIH VPPH AIN D IN AIN Standby V IH XV DD or VSS XH i g h Z X Chip-Erase V IL VIH VPPH VH High Z X Program/Erase Inhibit V IH XV PPH XH i g h Z X Product Identification V IL VIL VDD or VSS VH Manufacturer’s ID (BFH) Device ID (A3H) A14 - A1 = VIL, A0 = VIL A14 - A1 = VIL, A0 = VIH T3.1 502 TABLE 4: O PERATION MODES SELECTION FOR SST27SF512 Mode CE# OE#/V PP A 9 DQ Address Read V IL VIL AIN D OUT AIN Output Disable V IL VIH X High Z X Program V IL VPPH AIN D IN AIN Standby V IH X X High Z X Chip-Erase V IL VPPH VH High Z X Program/Erase Inhibit V IH VPPH X High Z X Product Identification V IL VIL VH Manufacturer’s ID (BFH) Device ID (A4H) A15 - A1 = VIL, A0 = VIL A15 - A1 = VIL, A0 = VIH T4.1 502 TABLE 5: O PERATION MODES SELECTION FOR SST27SF010/020 Mode CE# OE# PGM# A 9 VPP DQ Address Read V IL VIL XA IN VDD or VSS D OUT AIN Output Disable V IL VIH XX V DD or VSS High Z A IN Program V IL VIH VIL AIN VPPH D IN AIN Standby V IH XX X V DD or VSS High Z X Chip-Erase V IL VIH VIL VH VPPH High Z X Program/Erase Inhibit VIH XX X V PPH High Z X Product Identification VIL VIL XV H VDD or VSS Manufacturer’s ID (BFH) Device ID1 1. Device ID = A5H for SST27SF010 and A6H for SST27SF020 AMS 2 - A1 = VIL, A0 = VIL AMS 2 - A1 = VIL, A0 = VIH 2. AMS = Most significant address AMS = A16 for SST27SF010 and A17 for SST27SF020 Note: X = VIL or VIH VPPH = 12V±5%, VH = 12V±5% T5.1 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) DD +0.5V 1. Outputs shorted for no more than one second. No more than one output shorted at a time. O PERATING RANGE Range Ambient Temp V DD VPP Commercial 0 °C to +70°C5 . 0 V ± 1 0 % 1 2 V ± 5 % AC C ONDITIONS OF TEST See Figures 11 and 12 TABLE 6: R EAD MODE DC OPERATING CHARACTERISTICS FOR SST27SF256/512/010/020 VDD = 5.0V±10%, VPP =V DD OR VSS (Ta = 0°C to +70°C (Commercial)) Symbol Parameter Limits Test ConditionsMin Max Units IDD VDD Read Current Address input=V IL/VIH at f=1/TRC Min VDD =V DD Max 30 mA CE#=OE#=V IL, all I/Os open IPPR VPP Read Current Address input=V IL/VIH at f=1/TRC Min VDD =V DD Max, VPP =VDD 100 µA CE#=OE#=V IL, all I/Os open ISB1 Standby VDD Current (TTL input) 3m A C E # = V IH, VDD =V DD Max ISB2 Standby VDD Current (CMOS input) 100 µA CE#=V DD -0.3 VDD =V DD Max ILI Input Leakage Current 1 µA V IN=GND to VDD , VDD =V DD Max ILO Output Leakage Current 10 µA V OUT =GND to VDD , VDD =V DD Max VIL Input Low Voltage 0.8 V V DD =V DD Min VIH Input High Voltage 2.0 V DD +0.5 V V DD =V DD Max VOL Output Low Voltage 0.2 V I OL =2.1 mA, VDD =V DD Min VOH Output High Voltage 2.4 V I OH =-400 µA, VDD =VDD Min IH Supervoltage Current for A9 100 µA CE#=OE#=V IL, A9=V H Max T6.3 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 TABLE 7: P ROGRAM /ERASE DC OPERATING CHARACTERISTICS FOR SST27SF256 VDD =5.0V±10%, VPP =V PPH (Ta=25°C±5 °C) Symbol Parameter Limits Test ConditionsMin Max Units IDD VDD Erase or Program Current 30 mA CE#=V IL, OE#=V IH, VPP =12V±5%, VDD =V DD Max IPP VPP Erase or Program Current 1 mA CE#=V IL, OE#=V IH, VPP =12V±5%, VDD =V DD Max ILI Input Leakage Current 1 µA V IN=GND to VDD , VDD =VDD Max ILO Output Leakage Current 1 µA V OUT =GND to VDD , VDD =V DD Max VH Supervoltage for A9 11.4 12.6 V CE#=OE#=V IL, IH Supervoltage Current for A9 100 µA CE#=OE#=V IL, A9=V H Max VPPH High Voltage for VPP Pin 11.4 12.6 V T7.1 502 TABLE 8: P ROGRAM /ERASE DC OPERATING CHARACTERISTICS FOR SST27SF512 VDD =5.0V±10%, VPP =V PPH (Ta=25°C±5 °C) Symbol Parameter Limits Test ConditionsMin Max Units IDD VDD Erase or Program Current 30 mA CE#=V IL, OE#/V PP =12V±5%, VDD =VDD Max IPP VPP Erase or Program Current 1 mA CE#=V IL, OE#/V PP =12V±5%, VDD =VDD Max ILI Input Leakage Current 1 µA V IN=GND to VDD , VDD =VDD Max ILO Output Leakage Current 1 µA V OUT =GND to VDD , VDD =V DD Max VH Supervoltage for A9 11.4 12.6 V CE#=OE#/V PP =VIL, IH Supervoltage Current for A9 100 µA CE#=OE#/V PP =VIL, A9=V H Max VPPH High Voltage for OE#/VPP Pin 11.4 12.6 V T8.1 502 TABLE 9: P ROGRAM /ERASE DC OPERATING CHARACTERISTICS FOR SST27SF010/020 VDD =5.0V±10%, VPP =V PPH (Ta=25°C±5 °C) Symbol Parameter Limits Test ConditionsMin Max Units IDD VDD Erase or Program Current 30 mA CE#=PGM#=V IL, OE#=V IH, VPP =12V±5%, VDD =VDD Max IPP VPP Erase or Program Current 1 mA CE#=PGM#=V IL, OE#=V IH, VPP =12V±5%, VDD =VDD Max ILI Input Leakage Current 1 µA V IN =GND to VDD , VDD =VDD Max ILO Output Leakage Current 1 µA V OUT =GND to VDD , VDD =VDD Max VH Supervoltage for A9 11.4 12.6 V CE#=OE#=V IL, IH Supervoltage Current for A9 100 µA CE#=OE#=V IL, A9=V H Max VPPH High Voltage for VPP Pin 11.4 12.6 V T9.1 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 AC CHARACTERISTICS TABLE 10: R ECOMMENDED SYSTEM POWER -UP TIMINGS Symbol Parameter Minimum Units TPU-READ 1 Power-up to Read Operation 100 µs TPU-WRITE 1 Power-up to Write Operation 100 µs T10.1 502 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum C I/O1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. I/O Pin Capacitance V I/O = 0V 12 pF C IN1 Input Capacitance V IN = 0V 6 pF T11.0 502 TABLE 12: R ELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N END 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Endurance 1000 Cycles JEDEC Standard A117 TDR 1 Data Retention 100 Y ears JEDEC Standard A103 ILTH1 Latch Up 100 mA JEDEC Standard 78 T12.2 502 TABLE 13: R EAD CYCLE TIMING PARAMETERS VDD = 5.0V±10% (Ta = 0°C to +70°C (Commercial)) Symbol Parameter SST27SF256-70 SST27SF512-70 SST27SF010-70 SST27SF020-70 SST27SF256-90 SST27SF512-90 SST27SF010-90 SST27SF020-90 UnitsM i nM a xM i nM a x T RC Read Cycle Time 70 90 ns TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ 1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. CE# Low to Active Output 0 0 ns TOLZ 1 OE# Low to Active Output 0 0 ns TCHZ 1 CE# High to High-Z Output 25 30 ns TOHZ 1 OE# High to High-Z Output 25 30 ns TOH 1 Output Hold from Address Change 0 0 ns T13.1 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 TABLE 14: PROGRAM /ERASE CYCLE TIMING PARAMETERS FOR SST27SF256 Symbol Parameter Min Max Units TAS Address Setup Time 1 µs TAH Address Hold Time 1 µs TPRT VPP Pulse Rise Time 50 ns TVPS VPP Setup Time 1 µs TVPH VPP Hold Time 1 µs TPW CE# Program Pulse Width 20 30 µs TEW CE# Erase Pulse Width 100 500 ms TDS Data Setup Time 1 µs TDH Data Hold Time 1 µs TVR VPP and A9 Recovery Time 1 µs TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 µs TA9H A9 Hold Time during Erase 1 µs T14.0 502 TABLE 15: PROGRAM /ERASE CYCLE TIMING PARAMETERS FOR SST27SF512 Symbol Parameter Min Max Units TAS Address Setup Time 1 µs TAH Address Hold Time 1 µs TPRT OE#/V PP Pulse Rise Time 50 ns TVPS OE#/V PP Setup Time 1 µs TVPH OE#/V PP Hold Time 1 µs TPW CE# Program Pulse Width 20 30 µs TEW CE# Erase Pulse Width 100 500 ms TDS Data Setup Time 1 µs TDH Data Hold Time 1 µs TVR OE#/V PP and A9 Recovery Time 1 µs TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 µs TA9H A9 Hold Time during Erase 1 µs T15.0 502 TABLE 16: PROGRAM /ERASE CYCLE TIMING PARAMETERS FOR SST27SF010/020 Symbol Parameter Min Max Units TCES CE# Setup Time 1 µs TCEH CE# Hold Time 1 µs TAS Address Setup Time 1 µs TAH Address Hold Time 1 µs TPRT VPP Pulse Rise Time 50 ns TVPS VPP Setup Time 1 µs TVPH VPP Hold Time 1 µs TPW PGM# Program Pulse Width 20 30 µs TEW PGM# Erase Pulse Width 100 500 ms TDS Data Setup Time 1 µs TDH Data Hold Time 1 µs TVR A9 Recovery Time for Erase 1 µs TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 µs TA9H A9 Hold Time during Erase 1 µs T16.0 502

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 4: R EAD CYCLE TIMING DIAGRAM FOR SST27SF256/512/010/020 FIGURE 5: C HIP-ERASE TIMING DIAGRAM FOR SST27SF256 502 ILL F03.0 DATA VALIDDATA VALID TCLZ TOLZ TOH TRC TAA TOE TOHZ TCHZ HIGH-ZDQ 7-0 OE# CE# ADDRESS TCE 502 ILL F04a.1 TA9H TVR TVPH TVPS TEW TPRT VDD VSS VPP VPPH VPPH VIH VIH VIL DQ 7-0 CE# OE# ADDRESS (EXCEPT A 9) TA9S TART TVR

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 6: R EAD CYCLE TIMING DIAGRAM FOR SST27SF512 FIGURE 7: C HIP-ERASE TIMING DIAGRAM FOR SST27SF010/020 502 ILL F04b.1 TA9H TVR TVPH TVPS TEW TPRT VDD VSS OE#/V PP VPPH VPPH VIH VIL DQ 7-0 CE# ADDRESS (EXCEPT A 9) TA9S TART TVR 502 ILL F04c.1 TA9H TVR TVPH TVPS TCEH TPRT VDD VSS VPP PGM# VPPH VPPH VIH VIH VIL DQ 7-0 OE# CE# ADDRESS (EXCEPT A 9) TA9S TART TCES TEW

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 8: B YTE -PROGRAM TIMING DIAGRAM FOR SST27SF256 FIGURE 9: B YTE -PROGRAM TIMING DIAGRAM FOR SST27SF512 502 ILL F05a.1 DATA VALID ADDRESS VALID TAH TPW TDH TAS TDS TVR VDD VPPH VIH HIGH-Z VSS TVPH TPRT TVPS VPP DQ 7-0 CE# OE# ADDRESS 502 ILL F05b.2 DATA VALID ADDRESS VALID TAH TPW TDH TAS TDS TVR VDD VPPH HIGH-Z VSS TVPH TPRT TVPS OE#/V PP DQ 7-0 CE# ADDRESS

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 10: BYTE -PROGRAM TIMING DIAGRAM FOR SST27SF010/020 502 ILL F05c.1 DATA VALID ADDRESS VALID TAH TCEH TAS TDS TDH VDD VPPH HIGH-Z VIH VSS TCES TPW TVPH TPRT TVPS VPP PGM# DQ 7-0 OE# CE# ADDRESS

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 11: AC INPUT /OUTPUT REFERENCE WAVEFORMS FIGURE 12: A TEST LOAD EXAMPLE 502 ILL F06.0 REFERENCE POINTS OUTPUTINPUT VHT VLT VHT VLT VIHT VILT AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test 502 ILL F07.1 TO TESTER TO DUT C L R L LOW R L HIGH VDD

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 13: CHIP-ERASE ALGORITHM FOR SST27SF256 Start VPP = VPPH, A9 = VH VPP = VDD or VSS A9 = VIL or VIH Wait for VPP and A9 Recovery Time Erase 100ms pulse (CE# = VIL) Read Device (CE# = OE# = VIL) Device Passed Compare All bytes to FFH Device Failed 502 ILL F08a.2 No Ye s

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 14: CHIP-ERASE ALGORITHM FOR SST27SF512 OE#/VPP = VPPH OE#/V PP = VDD or VSS A9 = VIL or VIH Wait for OE#/VPP and A9 Recovery Time Erase 100ms pulse (CE# = VIL) Read Device (CE# = OE# = VIL) Device Passed Compare All bytes to FFH Device Failed 502 ILL F08b.2 Start A9 = VH No Ye s

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 15: CHIP-ERASE ALGORITHM FOR SST27SF010/020 Start A9 = VH , VPP = VPPH A9 = VIL or VIH CE# = VIL, OE# = VIH Wait A9 Recovery Time Erase 100ms pulse (PGM# = VIL) Read Device Device Passed Compare all bytes to FFH Device Failed 502 ILL F08c.1 PGM# = V IH No Ye s

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 16: BYTE -PROGRAM ALGORITHM FOR SST27SF256 Start Erase* VPP = VPPH Address = First Location Program 20µs pulse (CE# = VIL) Read Device (CE# = OE# = VIL) Device Passed Compare all bytes to original data Increment Address Device Failed 502 ILL F09a.3 Last Address? Wait for VPP RecoveryTime VPP = VDD or VSS No No Ye s Ye s * See Figure 13

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 17: BYTE -PROGRAM ALGORITHM FOR SST27SF512 Start Erase* OE#/V PP = VPPH Address = First Location Program 20µs pulse (CE# = VIL) Read Device (CE# = OE# = VIL) Device Passed Compare all bytes to original data Increment Address Device Failed 502 ILL F09b.2 Last Address? Wait for OE#/VPP RecoveryTime OE#/V PP = VDD or VSS No No Ye s Ye s * See Figure 14

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 FIGURE 18: BYTE -PROGRAM ALGORITHM FOR SST27SF010/020 Start Erase* VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 20µs pulse (PGM# = VIL) Read Device Device Passed Compare all bytes to original data Increment Address Device Failed 502 ILL F09c.1 Last Address? No No Ye s Ye s * See Figure 15

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 Device Speed Suffix1 Suffix2 SST27SFxxx -X X X -X X -X X Package Modifier G = 28 pins H = 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP Operating Temperature C = Commercial = 0° to +70°C Minimum Endurance 3 = 1000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 256 = 256 Kilobit 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 Valid combinations for SST27SF256 SST27SF256-70-3C-NH SST27SF256-70-3C-WH SST27SF256-70-3C-PG SST27SF256-90-3C-NH SST27SF256-90-3C-WH SST27SF256-90-3C-PG Valid combinations for SST27SF512 SST27SF512-70-3C-NH SST27SF512-70-3C-WH SST27SF512-70-3C-PG SST27SF512-90-3C-NH SST27SF512-90-3C-WH SST27SF512-90-3C-PG Valid combinations for SST27SF010 SST27SF010-70-3C-NH SST27SF010-70-3C-WH SST27SF010-70-3C-PH SST27SF010-90-3C-NH SST27SF010-90-3C-WH SST27SF010-90-3C-PH Valid combinations for SST27SF020 SST27SF020-70-3C-NH SST27SF020-70-3C-WH SST27SF020-70-3C-PH SST27SF020-90-3C-NH SST27SF020-90-3C-WH SST27SF020-90-3C-PH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 PACKAGING DIAGRAMS 32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE : NH 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE : WH .030 .040 .013 .021 .490 .530 .075 .095 .015 Min. .125 .140 TOP VIEW SIDE VIEW BOTTOM VIEW 123 2 .026 .032 .400 BSC 32.PLCC.NH-ILL.2 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. .050 BSC. .050 BSC. .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 Optional Pin #1 Identifier .547 .553 .585 .595 .485 .495 .020 R. MAX. .106 .112 R.x 30˚ 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 BSC 0.15 0.0512.50 12.30 Pin # 1 Identifier 14.20 13.80 0.70 0.50

SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502 28-PIN PLASTIC DUAL -IN-LINE PACKAGE (PDIP) SST PACKAGE CODE : PG 32-PIN PLASTIC DUAL -IN-LINE PACKAGE (PDIP) SST PACKAGE CODE : PH 28.pdipPG-ILL.2 Pin #1 Identifier CL Base Plane Seating Plane Note: 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .170 .200 4 PLCS. .600 BSC.100 BSC .120 .150.016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.445 1.455 .008 .012 15˚ .600 .625 .530 .550 32.pdipPH-ILL.2 Pin #1 Identifier CL Base Plane Seating Plane Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .170 .200 4 PLCS. .600 BSC.100 BSC .120 .150.016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 15˚ .600 .625 .530 .550 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • T elephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com

Selected Specification

Silicon Storage Technol... 27SF020 overview.

Summary

256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

Description

256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

Source title 27SF020 Datasheet(PDF) - Silicon Storage Technology, Inc

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