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P/N: PM1551 REV. 1.2, DEC. 12, 2012 MX25L8035E DATASHEET

P/N: PM1551 REV. 1.2, DEC. 12, 2012

P/N: PM1551 REV. 1.2, DEC. 12, 2012 8M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH

FEATURES

  • Serial Peripheral Interface compatible -- Mode 0 and Mode 3
  • 8M:8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O read mode) structure
  • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually
  • 16 Equal Blocks with 64K byte each - Any Block can be erased individually
  • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
  • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE
  • High Performance - Fast read - 1 I/O: 108MHz with 8 dummy cycles - 2 I/O: 80MHz (2.7V~3.6V) ; 104MHz (3.0V~3.6V) with 4 dummy cycles - 4 I/O: 108MHz with 6 dummy cycles - Fast access time: 108MHz serial clock - Serial clock of two I/O read mode : 80MHz (2.7V~3.6V); 104MHz (3.0V~3.6V) - Serial clock of four I/O read mode : 108MHz, which is equivalent to 432MHz - Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 3s(typ.) /chip
  • Low Power Consumption - Low active read current: 25mA(max.) at 108MHz, and 10mA(max.) at 50MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (typ.) ; 50uA (max.) - Deep power-down current: 3uA (typ.) ; 20uA (max.)
  • Minimum 100,000 erase/program cycles
  • 20 years data retention SOFTWARE FEATURES
  • Input Data Format - 1-byte Command code
  • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4K-bit secured OTP for unique identifier
  • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
  • Status Register Feature
  • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - All REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID

P/N: PM1551 REV. 1.2, DEC. 12, 2012 HARDWARE FEATURES

  • SCLK Input - Serial clock input
  • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
  • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
  • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode
  • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode
  • PACKAGE - 8-pin SOP (200mil) - All devices are RoHS Compliant

P/N: PM1551 REV. 1.2, DEC. 12, 2012 Table 1. Additional Feature Comparison SIO1 pin, SIO2 pin, and SIO3 pin for address/dummy bits input and data output. The MX25L8035E provides sequential read operation on whole chip. bytes) basis, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis. command can be issued to detect completion status of a program or erase operation via WIP bit. Secured OTP and Block Protection, please see security feature and write status register section for more details. 100,000 program and erase cycles. Security Read Performance Identifier Flexible Block Protection (BP0-BP3) 4K-bit secured OTP

2 I/O

4 I/O

(command: AB hex) REMS (command: 90 hex) REMS2 (command: EF hex) REMS4 (command: DF hex) RDID (command: 9F hex) MX25L8035E V V V V 13 (hex) C2 13 (hex) (if ADD=0) C2 13 (hex) (if ADD=0) C2 13 (hex) (if ADD=0) C2 20 14 (hex)

P/N: PM1551 REV. 1.2, DEC. 12, 2012 PIN CONFIGURATIONS PIN DESCRIPTION 8-PIN SOP (200mil) SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O) / Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SO/SIO1 Serial Data Output (for 1 x I/O) Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SCLK Clock Input WP#/SIO2 Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) NC/SIO3 NC pin (Not connect) or Serial Data Input & Output (for 4xI/O read mode) VCC + 3.3V Power Supply GND Ground CS# SO/SIO1 WP#/SIO2 GND VCC NC/SIO3 SCLK SI/SIO0

P/N: PM1551 REV. 1.2, DEC. 12, 2012 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SCLK SO/SIO1 Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer CS# WP#/SIO2 NC/SIO3

P/N: PM1551 REV. 1.2, DEC. 12, 2012 DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power- up and power-down or from system noise.

  • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
  • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Page Program (4PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion
  • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig - nature command (RES).
  • Advanced Security Features: there are some protection and security features which protect content from inad - vertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the QE bit is set, the feature of HPM will be disabled.

Table 2. Protected Area Sizes

  • Security register bit 0 indicates whether the chip is locked by factory or not.

through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition. cured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition

Table 4. Memory Organization (8Mb)

  1. Before a command is issued, status register should be checked to ensure device is ready for the intended op -
  2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode

until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

  1. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
  2. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as Figure 1.

  1. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS,

wise, the instruction will be rejected and not executed.

  1. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect -

ed and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported

Table 5. Command Set Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.

P/N: PM1551 REV. 1.2, DEC. 12, 2012 (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (Please refer to Figure 9) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. (Please refer to Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Quad Page Program (4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to "Table 7. ID Definitions") The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

P/N: PM1551 REV. 1.2, DEC. 12, 2012 (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (Please refer to Figure 12) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. If the program/erase command is applied to a protected memory area, the array data will not be affected and WEL bit will be reset. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP# or is set to "1" to enable Quad SIO2 and SIO3. Once the system goes into Quad I/O mode, the feature of HPM will be disable. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, which is set to "0" (factory default). The SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protec - tion mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register Note 1: Please refer to the "Table 2. Protected Area Sizes". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) QE (Quad Enable) BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable 1=Quad Enable 0=not Quad Enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit Factory default=0 Factory default=0 Factory default=0 Factory default=0 Factory default=0 Factory default=0 Factory default=0 Factory default=0

Hardware Protected Mode (HPM) is entered. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. Table 6. Protection Modes

  1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). BP0, is at software protected mode (SPM). been set. It is rejected to write the Status Register and not be executed.

P/N: PM1551 REV. 1.2, DEC. 12, 2012 Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the QE bit is set, the feature of HPM will be disabled. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Fig- ure 14) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3- byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im - pact on the Program/Erase/Write Status Register current cycle. (8) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi - mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc - tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low → sending 2READ instruction → 24-bit address inter - leave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0 →data out interleave on SIO1 & SIO0→to end 2READ operation can use CS# to high at any time during data out (Please refer to Figure 16).

P/N: PM1551 REV. 1.2, DEC. 12, 2012 While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad - dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol - lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low → sending 4READ instruction → 24-bit address in - terleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 17). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low → sending 4 READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit ran- dom access address (Please refer to Figure 18 for 4x I/O read enhance performance mode timing waveform). In the performance-enhancing mode (Note of Figure 18 ), P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. And afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) in- struction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→sending SE instruction code→ 3-byte address on SI →CS# goes high. (Please refer to Figure 19) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

P/N: PM1551 REV. 1.2, DEC. 12, 2012 (11) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of address byte been latched- in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→sending BE instruction code→ 3-byte address on SI →CS# goes high. (Please refer to Figure 20) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (12) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc - tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary( the eighth bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→CS# goes high. (Please refer to Figure 21) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set to "0". (13) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 22) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the

P/N: PM1551 REV. 1.2, DEC. 12, 2012 tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (14) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in - struction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" be - fore sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the re - quired internal page program time is far more than the time data flows in. Therefore, we suggest that while execut - ing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→at least 1-byte on data on SIO[3:0]→CS# goes high. (Please refer to Figure 23) (15) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter- ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac - tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please refer to Figure 24) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (16) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in "Table 10. AC CHARACTERISTICS". Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instruc - tions. The RDP instruction is only for releasing from Deep Power Down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current pro - gram/erase/write cycle in progress.

The sequence is shown as Figure 25, Figure 26. ommended to use for 4 I/O identification. The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 27. continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 7. ID Definitions Secured OTP data cannot be updated again once it is lock-down. curity OTP is lock down, only read related commands are valid. The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.

at any time (even in program/erase/write status register/write security register condition) and continuously. data out on SO→ CS# goes high. not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. area cannot be update any more. While it is in 4K-bit secured OTP mode, array access is not allowed. Table 8. Security Register Definition cured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction→CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

P/N: PM1551 REV. 1.2, DEC. 12, 2012 POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed.(generally around 0.1uF)

Figure 2. Maximum Negative Overshoot Waveform Figure 3. Maximum Positive Overshoot Waveform

  1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

to absolute maximum rating conditions for extended period may affect reliability.

  1. Specifications contained within the following tables are subject to change.
  2. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.

Table 9. DC CHARACTERISTICS

  1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
  2. Typical value is calculated by simulation.
  3. It is measured under checkboard pattern.

Table 10. AC CHARACTERISTICS

  1. tCH + tCL must be greater than or equal to 1/f (fC or fR or f4PP).
  2. Value guaranteed by characterization, not 100% tested in production.

3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

  1. Test condition is shown as Figure 4, 5.

Figure 14. Read Data Bytes (READ) Sequence (Command 03) Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

24 BIT ADDRESS

Figure 16. 2 x I/O Read Mode Sequence (Command BB)

8 Bit Instruction 12 BIT Address 4 dummy

8 Bit Instruction 6 Address cycles 4 dummy

  1. Hi-impedance is inhibited for the two clock cycles.
  2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will enter the performance enhance mode.
  3. SI/SIO0 or SO/SIO1 should be kept "00" or "11" in the first 2 dummy cycles.

In other words, P2=P0 or P3=P1 is necessary. Figure 17. 4 x I/O Read Mode Sequence (Command EB)

Figure 18. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)

6 Address cycles 4 dummy

Figure 19. Sector Erase (SE) Sequence (Command 20) Figure 20. Block Erase (BE) Sequence (Command D8) Note: SE command is 20(hex). Note: BE command is D8(hex). Figure 21. Chip Erase (CE) Sequence (Command 60 or C7) Note: CE command is 60(hex) or C7(hex).

Figure 22. Page Program (PP) Sequence (Command 02) Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)

6 Address cycle Data

Figure 24. Deep Power-down (DP) Sequence (Command B9) Figure 25. Read Electronic Signature (RES) Sequence (Command AB)

3 Dummy Bytes

(2) Instruction is either 90(hex) or EF(hex) or DF(hex). Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB) Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)

2 Dummy Bytes

Figure 28. Power-up Timing Register contains 00h (all Status Register bits are 0). Note: 1. The parameter is characterized only. Table 11. Power-Up Timing

P/N: PM1551 REV. 1.2, DEC. 12, 2012 RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. (ex: Vcc and CS# ramp up simultaneously) If the timing in the figure is ignored, the device may not operate correctly. Figure A. AC Timing at Device Power-Up Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 10. AC CHARACTERISTICS". SCLK SI CS# VCC MSB IN SO tDVCH High Impedance LSB IN tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSHtCHSL tVR VCC(min) GND Symbol Parameter Notes Min. Max. Unit tVR VCC Rise Time 1 20 500000 us/V

P/N: PM1551 REV. 1.2, DEC. 12, 2012 ERASE AND PROGRAMMING PERFORMANCE Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com - mand. 4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard. LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. Parameter Min. Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 100 ms Sector Erase Cycle Time 60 300 ms Block Erase Cycle Time 0.4 2.2 s Chip Erase Cycle Time 3 15 s Byte Program Time (via page program command) 9 300 us Page Program Cycle Time 0.7 3 ms Erase/Program Cycle 100,000 cycles Parameter Condition Min. Max. Unit Data retention 55˚C 20 years DATA RETENTION

P/N: PM1551 REV. 1.2, DEC. 12, 2012

ORDERING INFORMATION

PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark MX25L8035EM2I-10G 108 -40°C~85°C 8-SOP (200mil) RoHS Compliant

P/N: PM1551 REV. 1.2, DEC. 12, 2012 PART NAME DESCRIPTION MX 25 L 10M2 I G OPTION: G: RoHS Compliant SPEED: 10: 1 I/O 108MHz, 2 I/O 80MHz, 4 I/O 108MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 200mil 8-SOP DENSITY & MODE: 8035E: 8Mb TYPE: L: 3V DEVICE: 25: Serial Flash 8035E

P/N: PM1551 REV. 1.2, DEC. 12, 2012

PACKAGE INFORMATION

P/N: PM1551 REV. 1.2, DEC. 12, 2012

REVISION HISTORY

Revision No. Description Page Date 1.1 1. Modified tSLCH, tCHSL, tCHDX, tCHSH, tSHCH time P28 JUN/13/2012 2. Modified description for RoHS compliance P6,42,43

1.2 Modified Output Hold Time P28 DEC/12/2012

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