2559

2559_07 ALLEGRO

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Technical content

Providing improved output current limiting, the UDK, UDN, and UDQ2559B, EB, and LB quad power drivers combine AND logic gates and high-current bipolar outputs with complete output protection. Each of the four outputs will sink 700 mA in the on state. The outputs have a minimum breakdown voltage (load dump) of 60 V and a sustaining voltage of 40 V. The inputs are compatible with TTL and 5 V CMOS logic systems. Over-current protection for each channel has been designed into these devices and is activated at approximately 1 A. It protects each output from short circuits with supply voltages up to 25 V. When an output current trip point is reached, that output stage is driven linearly resulting in a reduced output current level. If an over-current or short- circuit condition continues, the thermal-limiting circuits will first sense the rise in junction temperature and then the rise in chip temperature, further decreasing the output current. Under worst-case conditions, these devices will tolerate short circuits on all outputs, simultaneously. These devices can be used to drive various loads including incan- descent lamps (without warming or limiting resistors) or inductive loads such as relays, solenoids, or dc stepping motors. The packages offer fused leads for enhanced thermal dissipation. Package B is a 16-pin power DIP with exposed tabs, EB is a 28-lead power PLCC, and LB is a 16-lead power wide-body SOIC for surface- mount applications. The lead (Pb) free versions have 100% matte tin leadframe plating.

FEATURES

■ 700 mA Output Current per Channel ■ Independent Over-Current Protection for Each Driver ■ Thermal Protection for Device and Each Driver ■ Low Output-Saturation Voltage ■ Integral Output Flyback Diodes ■ TTL and 5 V CMOS Compatible Inputs ABSOLUTE MAXIMUM RATINGS at TA = 25°C Over-Current Protected Output Voltage, Package Power Dissipation, Operating Temperature Range, T A Prefix ‘UDK’ . . . . -40°C to +125°C Storage Temperature Range, *Outputs are peak current limited at approximately 1.0 A per driver. See Circuit Description and Application for further information. Data Sheet29317.14F 2559 3 14 8 9 ENABLE GROUND GROUND OUT K GROUND GROUND OUT3 OUT4 K OUT1 V CC IN 1 Dwg. PP-017-1 IN4 IN3 IN 2

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Selection Guide Part Number Pb-free Package Ambient Temperature (°C) UDN2559B – 16-pin DIP, exposed tabs UDN2559B-T Yes 16-pin DIP, exposed tabs UDN2559EB – 28-lead PLCC –20 to 85 UDN2559EB-T Yes 28-lead PLCC UDN2559LB – 16-lead SOIC UDN2559LB-T Yes 16-lead SOIC UDQ2559B – 16-pin DIP, exposed tabs UDQ2559B-T Yes 16-pin DIP, exposed tabs –40 to 85 UDQ2559LB – 16-lead SOIC UDQ2559LB-T Yes 16-lead SOIC UDK2559B – 16-pin DIP, exposed tabs UDK2559B-T Yes 16-pin DIP, exposed tabs UDK2559EB – 28-lead PLCC –40 to 125 UDK2559EB-T Yes 28-lead PLCC UDK2559LB – 16-lead SOIC UDK2559LB-T Yes 16-lead SOIC UDx2559LB 3 14 8 9 ENABLE GROUND GROUND OUT K GROUND GROUND OUT 3 OUT 4 K OUT 1 V CC IN 1 Dwg. PP-017-6 IN 4 IN3 IN 2

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM (1 of 4 Channels) UDx2559EB 50 75 100 125 150 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTSTEMPERATURE IN °°°°C R = 6°C/WθJT Dwg. GP-004-2B SUFFIX 'EB', R = 36°C/WθJA SUFFIX 'B', R = 43°C/WθJA SUFFIX 'LB', R = 90°C/WθJA PD = (VOUT1 x IOUT1 x dc) + … + (VOUTn x IOUTn x dc) + (VCC x ICC) = (TJ - TA)/RθJA VCC <<1 Ω OUT Dwg. FP-041 N IN N THERMAL LIMIT ENABLE K 412 18 26 GROUND GROUND GROUND GROUND Dwg. PP-019-1 K NO CONNECTION ENABLESUPPLY NC NC CCV OUT1 OUT2OUT3 OUT 4 IN4 IN3 IN2 IN1 NO CONNECTION K 255

www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C (prefix ‘UDN’) or over operating temperature range (prefix ‘UDK’ or ‘UDQ’), VCC = 4.75 V to 5.25 V Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Leakage Current I CEX VOUT = 50 V, VIN = 0.8 V, VEN = 2.0 V — <1.0 100 µA VOUT = 50 V, VIN = 2.0 V, VEN = 0.8 V — <1.0 100 µA Output Sustaining Voltage V OUT(SUS) IOUT = 100 mA, VIN = VEN = 0.8 V 40 —— V Output Saturation Voltage V OUT(SAT) All Devices, IOUT = 100 mA —— 300 mV All Devices, IOUT = 400 mA —— 500 mV ‘B’ & ‘EB ’ Packages Only, IOUT = 600 mA —— 700 mV Over-Current Trip I TRIP — 1.0 — A Input Voltage Logic 1 V IN(1) or VEN(1) 2.0 —— V Logic 0 V IN(0) or VEN(0) —— 0.8 V Input Current Logic 1 V IN(1) or VEN(1) = 2.0 V —— 40 µA Logic 0 V IN(0) or VEN(0) = 0.8 V —— -10 µA Total Supply Current I CC All Outputs ON, VIN* = VEN = 2.0 V —— 80 mA All Outputs OFF —— 5.0 mA Clamp Diode Forward Voltage V F IF = 1.0 A —— 1.7 V Clamp Diode Leakage Current I R VR = 50 V, D1 + D2 or D3 + D4 —— 50 µA Turn-On Delay t PHL IOUT = 500 mA —— 20 µs tPLH IOUT = 500 mA —— 20 µs Thermal Limit T J — 165 — °C Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified terminal. As used here, -100 is defined as greater than +10 (absolute magnitude convention) and the minimum is implicitly zero. * All inputs simultaneously, all other tests are performed with each input tested separately.

Worcester, Massachusetts 01615-0036 (508) 853-5000 TYPICAL OUTPUT CHARACTERISTIC CIRCUIT DESCRIPTION AND APPLICATION INCANDESCENT LAMP DRIVER High incandescent lamp turn-ON/in-rush currents can contribute to poor lamp reliability and destroy semiconductor lamp drivers. Warm- ing or current-limiting resistors protect both driver and lamp but use significant power either when the lamp is OFF or when the lamp is ON, respectively. Lamps with steady-state current ratings up to 700 mA can be driven by these devices without the need for warming (parallel) or current-limiting (series) resistors. When an incandescent lamp is initially turned ON, the cold fila- ment is at minimum resistance and would normally allow a 10x to 12x in-rush current. With these drivers, during turn-ON, the high in-rush current is sensed by the internal low-value sense resistor. Drive current to the output stage is then diverted by the shunting transistor, and the load current is momentarily limited to approximately 1.0 A. During this short transition period, the output current is reduced to a value dependent on supply voltage and filament resistance. During lamp warmup, the filament resistance increases to its maximum value, the output stage goes into saturation and applies maximum rated voltage to the lamp. INDUCTIVE LOAD DRIVER Bifilar (unipolar) stepper motors, relays, or solenoids can be driven directly. The internal flyback diodes prevent damage to the output transistors by suppressing the high-voltage spikes that occur when turning OFF an inductive load. For rapid current decay (fast turn-OFF speeds), the use of Zener diodes will raise the flyback voltage and inprove performance. However, the peak voltage must not exceed the specified minimum sustaining voltage (V SUPPLY + V Z + VF ≤ VOUT(SUS) ). FAULT CONDITIONS In the event of a shorted load, the load current will attempt to increase. As described above, the drive current to the affected output stage is reduced, causing the output stage to go linear, limiting the peak output current to approximately 1 A. As the power dissipation of that output stage increases, a thermal gradient sensing circuit will become operational, further decreasing the drive current to the affected output stage and reducing the output current to a value dependent on supply voltage and load resistance. Continuous or multiple overload conditions causing the chip temperature to reach approximately 165°C will result in an additional reduction in output current to maintain a safe level. If the fault condition is corrected, the output stage will return to its normal saturated condition. TYPICAL OUTPUT BEHAVIOR V OUT(SAT) Dwg. GP-013 OUTPUT VOLTAGE, V OUT OUTPUT CURRENT, I OUT T < 150°C T = 165°CJ J JUNCTION TEMP. LIMIT NOT TO SCALE TRIP I THERMAL GRADIENT SENSING NORMAL LAMP IN-RUSH CURRENT TIME THERMAL GRADIENT SENSING CURRENT LIMIT Dwg. WP-008 NOT TO SCALE ITRIP LAMP CURRENT

.070 .045 1.78 1.14 .150 .115 3.81 2.92 .195 .115 4.95 2.92 .014 .008 0.36 0.20 .430 MAX 10.92 .015 MIN 0.38 .005 MIN 0.13 .280 .240 7.11 6.10 .775 .735 19.69 18.67 A B CSEATING PLANE .022 .014 .056 .036 16X .010 [0.25] M C .100 .2.54 .300 .7.62 .210 MAX 5.33 A Preliminary dimensions, for reference only Dimensions in inches Metric dimensions (mm) in brackets, for reference only (reference JEDEC MS-001 BB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Package, 16-pin DIP with internally fused pins 4, 5, 12, and 13 and external thermal tabs

www.allegromicro.com with internally fused pins 5 through 11 and 19 through 25 21 2 8 A Terminal #1 mark area Preliminary dimensions, for reference only (reference JEDEC MS-018 AB) Dimensions in inches Millimeters (mm) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A .120 .090 3.05 2.29 .180 .165 4.57 4.19 11.58 11.43 .456 .450 5.56 4.85 .219 .191 5.56 4.85 .219 .191 5.56 4.85 .219 .191 5.56 4.85 .219 .191 .020 MIN 0.51 C H SEATING PLANE .032 .026 0.81 0.66 28X C.004 [0.10] 28X .007 [0.18] H B A A 12.57 12.32 .495 .485 .007 [0.18] H B A 12.57 12.32 .495 .485 .007 [0.18] H B B.002 [0.05] .050 1.27 .020 0.51 A B 11.58 11.43 .456 .450 .007 [0.18] H B B.002 [0.05] A.007 [0.18] C B .021 .013 0.53 0.33 28X A.007 [0.18] C B

Worcester, Massachusetts 01615-0036 (508) 853-5000 with internally fused pins 4 and 5, and 12 and 13 0.30 0.10 .012 .004 2.65 2.35 .104 .093 7.60 7.40 .299 .291 0.33 0.20 .013 .008 1.27 0.40 .050 .016 10.50 10.10 .614 .598 CSEATING PLANE A B C0.10 [.004] 16X 0.25 .010 0.51 0.31 .020 .012 16X 0.25 [.010] M C A B 10.63 9.97 .419 .393 0.25 [.010] M B M 1.27 .050 GAUGE PLANE SEATING PLANE Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area A Copyright ©1995, 2007, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user i s cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon sibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com