Memory

24LC64T-I/MNY16KVXX

Microchip Technology

64-Kbit I2C Serial EEPROM 09/14/21

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Manufacturer or author: Provided By digicamel.com
PDF pages: 51

Technical content

Features

Single Supply with Operation Down to 1.7V for 24AA64 and 24FC64 Devices and 2.5V for 24LC64 Devices
Low-Power CMOS Technology: - Active current: 3 mA, maximum - Standby current: 1 µA, maximum
Two-Wire Serial Interface, I2C Compatible
Packages with Three Address Pins are Cascadable Up to Eight Devices
Schmitt Trigger Inputs for Noise Suppression
Output Slope Control to Eliminate Ground Bounce
100 kHz and 400 kHz Clock Compatibility
1 MHz Clock for FC versions
Page Write Time: 5 ms, Maximum
Self-Timed Erase/Write Cycle
32-Byte Page Write Buffer
Hardware Write-Protect
ESD Protection > 4,000V
More Than 1 Million Erase/Write Cycles
Data Retention > 200 Years
Factory Programming Available
RoHS Compliant
Temperature Ranges Supported:
Automotive AEC-Q100 Qualified Packages
5-Lead Chip Scale, 8-Lead DFN, 8-Lead DFN-S, 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ, 5-Lead SOT-23, 8-Lead TDFN, 8-Lead TSSOP and 8-Lead X-Rotated TSSOP

Description

The Microchip Technology Inc. 24XX64(1) is a 64-Kbit Electrically Erasable PROM (EEPROM). The device is organized as a single block of 8K x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V, with standby and active currents of only 1 µA and 3 mA, respectively. The 24XX64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512-Kbit address space. Package Types Device Selection Table Part Number V CC Range Max. Clock Frequency Temp. Ranges Packages 24AA64 1.7V-5.5V 400 kHz (1) I, E CS, MC, MS, P , SN, SM, OT, MNY , ST, X/ST 24FC64 1.7V-5.5V 1 MHz (2) I MC, MF, MS, P, SN, SM, OT, MNY, ST 24LC64 2.5V-5.5V 400 kHz I, E MC, MS, P, SN, SM, OT, MNY, ST, X/ST Note 1: 100 kHz for VCC < 2.5V 2: 400 kHz for VCC < 2.5V - Industrial (I): -40 Ct o + 8 5 C - Extended (E): -40 Ct o+ 1 2 5C Note 1: 24XX64 is used in this document as a generic part number for the 24AA64/24FC64/24LC64 devices. VSS VCC WP SCL SDA MSOP/PDIP/SOIC/SOIJ/TSSOP DFN/TDFN VSS WP SCL SDA VCC8 SOT-23 5 WP VCC SCL VSS SDA CS (Chip Scale) 1 2 VCC WP SDASCL VSS (Top Down View, Balls Not Visible) Note 1: Available in I-temp, “AA” only. X-Rotated TSSOP WP VCC SCL SDA VSS (X/ST) (1) 64-Kbit I2C Serial EEPROM

DS20001189U-page 2  1997-2022 Microchip Technology Inc. and its subsidiaries Block Diagram HV EEPROM Array Page YDEC XDEC Sense Amp. Memory Control Logic I/O Control Logic I/O WP SDA SCL VCC VSS R/W Control Latches GeneratorA2A1A0

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 3 24AA64/24FC64/24LC64

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†) † NOTICE: Stresses above those listed und er “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Param. No. Symbol Characteristic Min. Typical Max. Units Conditions D1 V IH High-Level Input Voltage 0.7 V CC —— V D2 V IL Low-Level Input Voltage — — 0.3 V CC VV CC  2.5V — — 0.2 V CC VV CC  2.5V D3 V HYS Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) 0.05 V CC —— V V CC  2.5V (Note 1) D4 V OL Low-Level Output Voltage —— 0 . 4 0 V I OL = 3.0 mA @ VCC = 4.5V —— 0 . 4 0 V I OL = 2.1 mA @ VCC = 2.5V D5 I LI Input Leakage Current —— ± 1 µ A V IN = VSS or VCC, WP = VSS —— ± 1 µ A V IN = VSS or VCC, WP = VCC D6 I LO Output Leakage Current — — ±1 µA V OUT = VSS or VCC D7 CIN, COUT Pin Capacitance (all inputs/outputs) —— 1 0 p F V CC = 5.0V (Note 1) TA = 25°C, FCLK = 1 MHz D8 I CC Write Operating Current —0 . 13 m A V CC = 5.5V, SCL = 400 kHz D9 I CC Read — 0.05 400 µA V CC = 5.5V, SCL = 400 kHz D10 I CCS Standby Current —0 . 0 11 µ A SDA = SCL = VCC A0, A1, A2, WP = VSS, I-Temp. ——5 µ A SDA = SCL = VCC A0, A1, A2, WP = VSS, E-Temp. Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature.

DS20001189U-page 4  1997-2022 Microchip Technology Inc. and its subsidiaries TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to +5.5V TA = -40°C to +85°C Extended (E): VCC = +1.7V to +5.5V TA = -40°C to +125°C Param. No. Symbol Characteristic Min. Max. Units Conditions 1F CLK Clock Frequency —1 0 0 k H z 1 . 7 V  VCC  2.5V —4 0 0 k H z 2 . 5 V  VCC  5.5V —4 0 0 k H z 1 . 7 V  VCC  2.5V (24FC64) — 1000 kHz 2.5V  VCC  5.5V (24FC64) 2T HIGH Clock High Time 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64) 3T LOW Clock Low Time 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64) 4T R SDA and SCL Rise Time — 1000 ns 1.7V  VCC  2.5V (Note 1) — 300 ns 2.5V  VCC  5.5V (Note 1) — 300 ns 1.7V  VCC  5.5V (24FC64) (Note 1) 5T F SDA and SCL Fall Time — 300 ns 24AA64 and 24LC64 (Note 1) — 100 ns 1.7V  VCC  5.5V (24FC64) (Note 1) 6T HD:STA Start Condition Hold Time 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) 7T SU:STA Start Condition Setup Time 4700 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) 8T HD:DAT Data Input Hold Time 0 — ns Note 2 9T SU:DAT Data Input Setup Time 250 — ns 1.7V  VCC  2.5V 100 — ns 2.5V  VCC  5.5V 100 — ns 1.7V  VCC  5.5V (24FC64)

10 T SU:STO Stop Condition Setup Time

4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization.

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 5 24AA64/24FC64/24LC64

11 T SU:WP WP Setup Time

4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  5.5V (24FC64)

12 T HD:WP WP Hold Time

4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  5.5V 24FC64

13 T AA Output Valid from Clock

— 3500 ns 1.7V  VCC  2.5V (Note 2) — 900 ns 2.5V  VCC  5.5V (Note 2) — 900 ns 1.7V  VCC  2.5V (24FC64) (Note 2) — 400 ns 2.5V  VCC  5.5V (24FC64) (Note 2)

14 T BUF

Bus Free Time: The time the bus must be free before a new transmission can start 4700 — ns 1.7V  V CC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64)

15 T OF

CB  100 pF 10 + 0.1CB 250 ns 24AA64 and 24LC64 (Note 1) — 250 ns 24FC64 (Note 1)

16 T SP Input Filter Spike Suppression

(SDA and SCL pins) —5 0 n s 24AA64 and 24LC64 (Note 1 and Note 3)

17 T WC Write Cycle Time

(byte or page) —5 m s 18 Endurance 1,000,000 — cycles +25°C, 5.5V, Page Mode (Note 4) TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to +5.5V TA = -40°C to +85°C Extended (E): VCC = +1.7V to +5.5V TA = -40°C to +125°C Param. No. Symbol Characteristic Min. Max. Units Conditions Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization.

DS20001189U-page 6  1997-2022 Microchip Technology Inc. and its subsidiaries FIGURE 1-1: BUS TIMING DATA (unprotected) (protected) SCL SDA IN SDA OUT WP D3 4 11 12

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 7 24AA64/24FC64/24LC64

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

2.1 A0, A1, A2 Chip Address Inputs

The A0, A1 and A2 inputs are used by the 24XX64 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either V CC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘ 0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘ 0’ or logic ‘1’ before normal device operation can proceed. Address pins are not available in the SOT-23 or Chip Scale packages.

2.2 Serial Address/Data Input/Output

(SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to V CC (typical 10 k  for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

2.3 Serial Clock (SCL)

The SCL input is used to synchronize the data transfer from and to the device.

2.4 Write-Protect (WP)

This pin must be connected to either VSS or VCC. If tied to V SS, write operations are enabled. If tied to V CC, write operations are inhibit ed but read operations are not affected. TABLE 2-1: PIN FUNCTION TABLE Name CS DFN (1) MSOP PDIP SOIC SOIJ SOT-23 TDFN (1) TSSOP Rotated TSSOP Description A0 — 1 1 1 1 1 — 1 1 3 Chip Address Input A1 — 2 2 2 2 2 — 2 2 4 Chip Address Input A2 — 3 3 3 3 3 — 3 3 5 Chip Address Input VSS 2 4 4 4 4 4 2 4 4 6 Ground SDA 5 5 5 5 5 5 3 5 5 7 Serial Address/Data I/O SCL 4 6 6 6 6 6 1 6 6 8 Serial Clock WP 3 7 7 7 7 7 5 7 7 1 Write-Protect Input VCC 1 8 8 8 8 8 4 8 8 2 Power Supply Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.

DS20001189U-page 8  1997-2022 Microchip Technology Inc. and its subsidiaries

3.0 FUNCTIONAL DESCRIPTION

The 24XX64 supports a bidirectional, two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a host device which generates the Serial Clock (SCL), controls the bus access and generates the Start and St op conditions, while the 24XX64 works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

Data transfer may be init iated only when the bus is not busy
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data li ne represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condi tion. The number of data bytes transferred between Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last 32 will be stored when doing a write operation). When an overwrite does occur, it will replace data in a First-In First-Out (FIFO) principle.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX64) will leave the data line high to enable the host to generate the Stop condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS Note: The 24XX64 does not generate any Acknowledge bits if an internal programming cycle is in progress. SCL SDA (A) (B) (D) (D) (A) (C) Start Condition Address or Acknowledge Valid Data Allowed to Change Stop Condition

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 9 24AA64/24FC64/24LC64

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the Start condition from the host device. The control byte consists of a 4-bit control code. For the 24XX64, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX64 devices on the same bus and are used to select which devi ce is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. The combination of the 4-bit control code and the next three bits are called the client address. For the SOT-23 and Chip Scale packages, the address pins are not available. During device addressing, the A2, A1 and A0 Chip Select bits should be set to ‘0’. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A12...A0 are used, the upper three address bits are “don’t care” bits. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX64 monitors the SDA bus, checking the device-type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX64 will select a read or write opera- tion. FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to

512 Kbits by adding up to eight 24XX64 devices on the

same bus. In this case, so ftware can use A0 of the control byte as address bit A13; A1 as address bit A14; and A2 as address bit A15. It is not possible to sequentially read across device boundaries. The SOT-23 and Chip Scale packages do not support multiple device addressing on the same bus. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1010 A2 A1 A0SA C K R/W

A A

0 R/W xxx A

A A A A A Control Byte Address High Byte Address Low Byte Control Code Chip Select bits x = “don’t care” bit

DS20001189U-page 10  1997-2022 Microchip Technology Inc. and its subsidiaries

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start condition from the host, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the host transmitter. This indicates to the addressed client receiver that the address high byte will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the high-order byte of the word address and will be written into t he Address Pointer of the 24XX64. The next byte is the Least Significant Address byte. After receiving another Acknowledge signal from the 24XX64, the host device will transmit the data word to be written into the addressed memory location. The 24XX64 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX64 will not generate Acknowledge signals ( Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal Address Pointer will point to the address location following the one that was just written.

6.2 Page Write

The write control byte, word address and the first data byte are transmitted to the 24XX64 in the same way as in a byte write. However, instead of generating a Stop condition, the host transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory once the host has transmitted a Stop condition. Upon receipt of each word, the five lower Address Pointer bits, which form the byte counter, are inte rnally incremented by one. The higher-order 8 bits of the word address remain constant. If the host should transmit more than 32 bytes prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be over- written. As with the byte write operation, once the Stop condition is received, an in ternal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command.

6.3 Write Protection

The WP pin allows the user to write-protect the entire array (0000-1FFF) when the pin is tied to VCC. If tied to VSS, the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 4-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. Note: When doing a write of less than 32 bytes, the data in the rest of the page are refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

DS20001189U-page 12  1997-2022 Microchip Technology Inc. and its subsidiaries

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the host sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation No Yes

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 13 24AA64/24FC64/24LC64

8.0 READ OPERATION

Read operations are initiated in the same way as write operations, with the exce ption that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read.

8.1 Current Address Read

The 24XX64 contains an Address Pointer that main- tains the address of the last word accessed, internally incremented by one. Theref ore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX64 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX64 discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX64 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX64 will then issue an Acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition, which causes the 24XX64 to discontinue transmission ( Figure 8-2 ). After a random Read command, the internal Address Pointer will point to the address location following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as random reads, except that once the 24XX64 transmits the first data byte, the host issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the 24XX64 to transmit the next sequentially-addressed 8-bit word ( Figure 8-3). Following the final byte bein g transmitted to the host, the host will NOT generate an Acknowledge, but will generate a Stop condition. To provide sequential reads, the 24XX64 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be se rially read during one operation. The internal Address Pointer will automatically roll over from address 1FFF to address 0000 if the host acknowledges the byte received from the array address 1FFF. FIGURE 8-1: CURRENT ADDRESS READ SP Bus Activity Host SDA Line Bus Activity S T O P Control Byte Data Byte A C K N O A C K S T A R T 101 1 A A A

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 15 24AA64/24FC64/24LC64

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 24LC64 I/P 13F 2204 24LC64I SN 2204 13F 8-Lead MSOP Example 4L64I 20413F 8-Lead 2x3 DFN Example 274 204 XXX YWW NN XXXXXT YWWNNN 5-Lead Chip Scale XW Example NN 13 8-Lead 5x6 DFN-S Example 24FC64 I/MF 2204 13F 8-Lead SOIJ Example XXXXXXXX T/XXXXXX YYWWNNN 24LC64 I/SM 220413F

DS20001189U-page 16  1997-2022 Microchip Technology Inc. and its subsidiaries Part Number 1st Line Marking Codes DFN MSOP SOT-23 TDFN TSSOP 24AA64 271 — 4A64T (1) 7HNN(2) 7WNN(2) A71 E10 4AB 4ABX 24FC64 27A — 4F64T (1) 7SNN(2) —A 7 A— 4 F B — 24LC64 274 275 4L64T (1) 7GNN(2) 7JNN(2) A74 A75 4LB 4LBX Note 1: T = Temperature grade (I, E) 2: NN = Alphanumeric traceability code Example A74 527 8-Lead 2x3 TDFN XXX YWW NN 5-Lead SOT-23 XXNN Example 7GNN 8-Lead TSSOP Example XXXX TYWW NNN 4LB I204 13F Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) JEDEC ® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. Note: For very small packages with no room for the JEDEC® designator , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information.

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 17 24AA64/24FC64/24LC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS20001189U-page 18  1997-2022 Microchip Technology Inc. and its subsidiaries Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 19 24AA64/24FC64/24LC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS20001189U-page 20  1997-2022 Microchip Technology Inc. and its subsidiaries /g37/g36 /g19/g17/g20/g24/g38 /g19/g17/g20/g24/g38 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g19/g24/g38 /g11/g39/g36/g55/g56/g48/g3/g37/g12 /g11/g39/g36/g55/g56/g48/g3/g36/g12 /g38 /g54/g40/g36/g55/g44/g49/g42 /g51/g47/g36/g49/g40 /g49/g50/g55/g40/g3/g20 /g49 /g21/g59 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g37/g50/g55/g55/g50/g48/g3/g57/g44/g40/g58 /g49/g50/g55/g40/g3/g20 /g20/g21 /g49 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38 /g19/g17/g19/g27/g38 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g20/g21/g22/g3/g53/g72/g89/g3/g40/g3/g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g39 /g40 /g36 /g11/g36/g22/g12 /g27/g59/g3/g69 /g72 /g21/g59 /g39/g21 /g40/g21 /g46 /g47 /g27/g59 /g36/g20 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g38/g12/g3/g16/g3/g21/g91/g22/g91/g20/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g39/g41/g49/g64 /g20/g21

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 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 25 24AA64/24FC64/24LC64 /g53/g40/g38/g50/g48/g48/g40/g49/g39/g40/g39/g3/g47/g36/g49/g39/g3/g51/g36/g55/g55/g40/g53/g49 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g56/g81/g76/g87/g86 /g50/g83/g87/g76/g82/g81/g68/g79/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75 /g50/g83/g87/g76/g82/g81/g68/g79/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g60/g21 /g59/g21 /g23/g17/g20/g19 /g21/g17/g23/g19 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g20/g17/g21/g26/g3/g37/g54/g38 /g48/g44/g49 /g40 /g48/g36/g59 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75/g3/g11/g59/g21/g19/g12 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75/g3/g11/g59/g21/g19/g12 /g60/g20 /g59/g20 /g20/g17/g20/g24 /g19/g17/g23/g24 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g21/g20/g21/g21/g3/g53/g72/g89/g3/g38 /g49/g50/g48 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g41/g12/g3/g16/g3/g25/g91/g24/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g39/g41/g49/g16/g54/g64 /g54/g44/g47/g46/g3/g54/g38/g53/g40/g40/g49 /g20/g21 /g27 /g38 /g40 /g59/g20 /g60/g20 /g42/g20 /g60/g21 /g59/g21 /g38/g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g24/g17/g25/g19 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g87/g82/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g11/g59/g21/g19/g12 /g42/g20 /g19/g17/g21/g19 /g55/g75/g72/g85/g80/g68/g79/g3/g57/g76/g68/g3/g39/g76/g68/g80/g72/g87/g72/g85 /g57 /g55/g75/g72/g85/g80/g68/g79/g3/g57/g76/g68/g3/g51/g76/g87/g70/g75 /g40/g57 /g19/g17/g22/g19 /g20/g17/g19/g19 /g145/g57 /g40/g57 /g40/g57 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g41/g82/g85/g3/g69/g72/g86/g87/g3/g86/g82/g79/g71/g72/g85/g76/g81/g74/g3/g85/g72/g86/g88/g79/g87/g86/g15/g3/g87/g75/g72/g85/g80/g68/g79/g3/g89/g76/g68/g86/g15/g3/g76/g73/g3/g88/g86/g72/g71/g15/g3/g86/g75/g82/g88/g79/g71/g3/g69/g72/g3/g73/g76/g79/g79/g72/g71/g3/g82/g85/g3/g87/g72/g81/g87/g72/g71/g3/g87/g82/g3/g68/g89/g82/g76/g71/g3/g86/g82/g79/g71/g72/g85/g3/g79/g82/g86/g86/g3/g71/g88/g85/g76/g81/g74 /g85/g72/g73/g79/g82/g90/g3/g83/g85/g82/g70/g72/g86/g86 /g20/g17 /g21/g17 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g54/g68/g90/g3/g54/g76/g81/g74/g88/g79/g68/g87/g72/g71

DS20001189U-page 26  1997-2022 Microchip Technology Inc. and its subsidiaries TOP VIEW VIEW A–A SIDE VIEW Note: http://www.microchip.com/packaging For the most current package drawings, please see the Microchip Packaging Specification located at 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-111-MS Rev D A B 0.25 C 2X 4 TIPS

0.25 C A-B D

A A 0.20 H 0.20 H N SEE DETAIL B NOTE 1 C 0.10 C H 8X b e D D E E A A2 SEATING PLANE Sheet 1 of 2 D

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 27 24AA64/24FC64/24LC64 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 C SEATING PLANE H Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.65 BSC

0.85 0.40 0.22 0.00 0.60 MILLIMETERS MIN NOM 0.80 0.40 1.10 0.15 MAX L1 0.95 REFFootprint Overall Length D 3.00 BSC Terminal Thickness c 0 . 0 8–0 . 2 3 R ș –0.07 –Lead Bend Radius –0.07 –Lead Bend Radius –0° 8°Foot Angle –5° 15°Mold Draft Angle 0.75 0.95

4.90 BSC

3.00 BSC

ș c 4X ș1 4X ș1 L (L1) R Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-111-MS Rev D

DS20001189U-page 28  1997-2022 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units Contact Pitch MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) Y X 1.45 0.45 NOM CContact Pad Spacing 4.40 Contact Pad to Contact Pad (X4) G1 2.95 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E C Contact Pad to Contact Pad (X6) GX 0.20 X Y GX SILK SCREEN 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-2111-MS Rev D

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 29 24AA64/24FC64/24LC64 B A For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] eB E A L 8X b 8X b1 c C PLANE .010 C N D NOTE 1 TOP VIEW END VIEWSIDE VIEW e

DS20001189U-page 30  1997-2022 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing eB -- . 4 3 0 BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .010" per side. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M e DATUM A DATUM A e b e b e ALTERNATE LEAD DESIGN (NOTE 5) 5. Lead design above seating plane may vary, based on assembly vendor.

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 31 24AA64/24FC64/24LC64

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D

DS20001189U-page 32  1997-2022 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 33 24AA64/24FC64/24LC64 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-SN Rev F BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

DS20001189U-page 34  1997-2022 Microchip Technology Inc. and its subsidiaries TOP VIEW VIEW A–A SIDE VIEW Sheet 1 of 2 Note: http://www.microchip.com/packaging For the most current package drawings, please see the Microchip Packaging Specification located at 8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm (.208 Inch) Body [SOIJ] Microchip Technology Drawing C04-056 Rev D A B D C SEATING PLANE 0.20 C 2X 4 TIPS 0.10 C 18X A A

0.10 C D

0.10 C A-B

N SEE DETAIL B 0.10 C NOTE 1 D EE1 e E A A2 A1 8X b

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 35 24AA64/24FC64/24LC64 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 C SEATING PLANE Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff § Units Dimension Limits A b e L E N 0.51 0.36 1.77 0.05 MILLIMETERS MIN NOM 0.76 0.51 2.03 0.25 MAX Overall Length D 5.26 BSC Terminal Thickness c 0 . 1 5–0 . 2 5 ș1 –0° 8°Foot Angle ș2 –Lead Angle 1.75 1.98 ș3 –Mold Draft Angle

7.94 BSC

5.25 BSC

15° 8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm (.208 Inch) Body [SOIJ] Microchip Technology Drawing C04-056 Rev D DETAIL B Dimensions D and E1 do not include mold flash or protrusions. Mold flash or § – Significant Characteristic protrusions shall not exceed 0.25mm per side. SOIJ – JEITA/EIAJ Standard, Formerly called SOIC c 4X ș1 4X ș1 L

DS20001189U-page 36  1997-2022 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units Contact Pitch MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) Y X 1.70 0.65 NOM ZOverall Width 9.00 Contact Pad to Contact Pad (X6) G2 0.62 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm (.208 Inch) Body [SOIJ] Contact Pad to Contact Pad (X4) G1 5.60 Microchip Technology Drawing C04-2056 Rev D CContact Pad Spacing 7.30 E X Y C Z SILK SCREEN

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 37 24AA64/24FC64/24LC64 /g19/g17/g20/g24/g38/g39 /g21/g59 /g49/g50/g55/g40/g3/g20/g20/g21 /g49 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g19/g28/g20/g16/g50/g55/g3/g53/g72/g89/g3/g42/g3/g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g19/g17/g21/g19/g38 /g38 /g54/g40/g36/g55/g44/g49/g42/g3/g51/g47/g36/g49/g40 /g36/g36/g21 /g36/g20 /g72 /g49/g59/g3/g69/g37 /g19/g17/g21/g19/g38/g36/g16/g37/g39 /g72/g20 /g39 /g40/g20 /g40/g20/g18/g21 /g40/g18/g21 /g40 /g39/g36 /g19/g17/g21/g19/g38/g21/g59 /g11/g39/g36/g55/g56/g48/g3/g39/g12 /g11/g39/g36/g55/g56/g48/g3/g36/g16/g37/g12 /g36 /g36 /g54/g40/g40/g3/g54/g43/g40/g40/g55/g3/g21 /g24/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g12/g3/g3/g62/g54/g50/g55/g21/g22/g64

DS20001189U-page 38  1997-2022 Microchip Technology Inc. and its subsidiaries /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g19/g28/g20/g16/g50/g55/g3/g53/g72/g89/g3/g42/g3/g54/g75/g72/g72/g87/g3/g21/g3/g82/g73/g3/g21 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g70 /g47 /g47/g20 /g84 /g57/g44/g40/g58/g3/g36/g16/g36 /g54/g43/g40/g40/g55/g3/g20 /g24/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g12/g3/g3/g62/g54/g50/g55/g21/g22/g64 /g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g3/g86/g75/g68/g79/g79/g3/g81/g82/g87/g3/g72/g91/g70/g72/g72/g71/g3/g19/g17/g21/g24/g80/g80/g3/g83/g72/g85/g3/g86/g76/g71/g72/g17 /g20/g17 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g21/g17 /g41/g82/g82/g87/g3/g36/g81/g74/g79/g72 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g51/g76/g81/g86 /g51/g76/g87/g70/g75 /g50/g88/g87/g86/g76/g71/g72/g3/g79/g72/g68/g71/g3/g83/g76/g87/g70/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g43/g72/g76/g74/g75/g87 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g54/g87/g68/g81/g71/g82/g73/g73 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g58/g76/g71/g87/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g47/g72/g81/g74/g87/g75 /g41/g82/g82/g87/g3/g47/g72/g81/g74/g87/g75 /g41/g82/g82/g87/g83/g85/g76/g81/g87 /g47/g72/g68/g71/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g47/g72/g68/g71/g3/g58/g76/g71/g87/g75 /g49/g82/g87/g72/g86/g29 /g47/g20 /g73 /g69 /g70 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g40 /g40/g20 /g39 /g47 /g72/g20 /g36 /g36/g21 /g36/g20 /g56/g81/g76/g87/g86 /g49 /g72 /g19/g131 /g19/g17/g19/g27 /g19/g17/g21/g19 /g16 /g16 /g16 /g20/g19/g131 /g19/g17/g21/g25 /g19/g17/g24/g20 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g19/g17/g28/g24/g3/g37/g54/g38 /g20/g17/g28/g19/g3/g37/g54/g38 /g19/g17/g22/g19 /g19/g17/g28/g19 /g19/g17/g27/g28 /g16 /g19/g17/g25/g19/g3/g53/g40/g41 /g21/g17/g28/g19/g3/g37/g54/g38 /g16 /g21/g17/g27/g19/g3/g37/g54/g38 /g20/g17/g25/g19/g3/g37/g54/g38 /g16 /g16 /g16 /g48/g44/g49 /g24 /g49/g50/g48 /g20/g17/g23/g24 /g20/g17/g22/g19 /g19/g17/g20/g24 /g19/g17/g25/g19 /g48/g36/g59 /g53/g40/g41/g29/g3/g3/g53/g72/g73/g72/g85/g72/g81/g70/g72/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g15/g3/g88/g86/g88/g68/g79/g79/g92/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g15/g3/g73/g82/g85/g3/g76/g81/g73/g82/g85/g80/g68/g87/g76/g82/g81/g3/g83/g88/g85/g83/g82/g86/g72/g86/g3/g82/g81/g79/g92/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g86/g3/g39/g3/g68/g81/g71/g3/g40/g20/g3/g71/g82/g3/g81/g82/g87/g3/g76/g81/g70/g79/g88/g71/g72/g3/g80/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g17/g3/g48/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 39 24AA64/24FC64/24LC64 /g53/g40/g38/g50/g48/g48/g40/g49/g39/g40/g39/g3/g47/g36/g49/g39/g3/g51/g36/g55/g55/g40/g53/g49 /g24/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g12/g3/g3/g62/g54/g50/g55/g21/g22/g64 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g20/g17/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g49/g82/g17/g3/g38/g19/g23/g16/g21/g19/g28/g20/g16/g50/g55/g3/g53/g72/g89/g3/g42 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75/g3/g11/g59/g24/g12 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g39/g76/g86/g87/g68/g81/g70/g72/g3/g37/g72/g87/g90/g72/g72/g81/g3/g51/g68/g71/g86 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75/g3/g11/g59/g24/g12 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g22/g17/g28/g19 /g20/g17/g20/g19 /g42 /g61 /g60 /g20/g17/g26/g19 /g19/g17/g25/g19 /g48/g36/g59/g48/g44/g49 /g38 /g59 /g40 /g56/g81/g76/g87/g86 /g49/g50/g48 /g19/g17/g28/g24/g3/g37/g54/g38 /g21/g17/g27/g19 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g39/g76/g86/g87/g68/g81/g70/g72/g3/g37/g72/g87/g90/g72/g72/g81/g3/g51/g68/g71/g86 /g42/g59 /g19/g17/g22/g24 /g20 /g24 /g59 /g60 /g61/g38 /g40 /g42/g59 /g42 /g21 /g54/g44/g47/g46/g3/g54/g38/g53/g40/g40/g49

DS20001189U-page 40  1997-2022 Microchip Technology Inc. and its subsidiaries BA 0.15 C 0.15 C

0.10 C A B

0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] D E A (A3) e 8X b L K With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 41 24AA64/24FC64/24LC64 Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: NOM MILLIMETERS

0.50 BSC

2.00 BSC

0.20 REF

Pin 1 visual index feature may vary, but must be located within the hatched area. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Contact-to-Exposed Pad Contact Thickness Exposed Pad Width Exposed Pad Length 4. Dimensioning and tolerancing per ASME Y14.5M 3. Package is saw singulated 2. Package may have one or more exposed tie bars at ends. Notes: Contact Width Overall Width Overall Length Contact Length Standoff Number of Pins Overall Height Pitch K 0.20 Units N e A Dimension Limits D b E L 0.20 1.35 1.25 0.25 0.00 0.70 MIN 0.25 0.30 1.30 1.40 1.35 0.30 0.45 1.45 0.75 0.02 0.05 0.80 MAX With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

DS20001189U-page 42  1997-2022 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 1.50 1.60 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.85 0.25 Microchip Technology Drawing No. C04-129-MN Rev. B NOM 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] CContact Pad Spacing 2.90 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: C E EV EV ØV SILK SCREEN With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

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DS20001189U-page 46  1997-2022 Microchip Technology Inc. and its subsidiaries APPENDIX A: REVISION HISTORY Revision U (03/2022) Added Product Identification System section for Auto- motive; Updated DFN, PDI P, SOIC, SOT-23, TDFN and TSSOP package drawings; Added DFN-S product offering; Replac ed terminology “Mas ter” and “Slave” with “Host” and “Client”, respectively; Replaced “Auto- motive (E):” designation with “Extended (E):” designa- tion; Reformatted some sections for better readability. Revision T (12/2012) Revised automotive E-temp; Product ID System. Revision S (01/2012) Updated package drawings: Updated Product ID. Revision R (03/2010) Added TS SOP X-Rotated package; Updated pac kage drawings; Updated Product ID. Revision Q (06/09) Revised Features section; Revised Table 1-2, Para. 18; Added note to Table 2-1; Revised SOT-23 package example. Revision P (03/2009) Added 5-lead Chip Scale Package Dia gram and Land Pattern; Revised Block Diagram. Revision N (03/2009) Added 5-lead Chip Scale package. Revision M (01/2009) Updated pac kage drawings; Added 8-lead TDFN an d 5-lead SOT-23 packages. Revision L (03/2007) Added 24FC64 Part; Revised Device Selec tion Table; Revised Features section; Deleted Rotated TSSOP Package; Revised Table 1-2; Revised Table 7-1; Revised Package Information; Replaced pack age drawings; Revised Product ID section. Revision K (08/2005) Revised Sections 7.1 and 7.4. Revision J (04/2005) Added DFN package. Revision H (12/2003) Corrections to Section 1.0, Electrical Characteristics.

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 47 24AA64/24FC64/24LC64 THE MICROCHIP WEBSITE Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

Product Support – Data sheets and errata, appli- cation notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com . Under “Support”, click on “Cus- tomer Change Notification” and follow the registra- tion instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support Customers should contact their distributor, representa- tive or Field Application Engineer (FAE) for support. Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support

DS20001189U-page 48  1997-2022 Microchip Technology Inc. and its subsidiaries PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTape and ReelDevice Device: 24AA64 = 24AA64X = 24FC64 = 24LC64 = 24LC64X = 1.7V, 64-Kbit I2C Serial EEPROM 1.7V, 64-Kbit I2C Serial EEPROM in alternate pin- out (ST only) 1.7V, 64-Kbit I2C Serial EEPROM 2.5V, 64-Kbit I2C Serial EEPROM 2.5V, 64-Kbit I2C Serial EEPROM in alternate pinout (ST only) Tape and Reel Option: Blank = T = Standard packaging (tube) Tape and Reel Temperature Range: -40C to +85C (Industrial) -40C to +125C (Extended) MC = MF = MS = SN = SM = OT = MNY = ST = Chip Scale Package – 5-Lead (CS) (Tape and Reel only) Plastic Dual Flat, No Lead – 2x3x1 mm Body, 8-Lead (DFN) Plastic Dual Flat, No Lead – 6x5 mm Body, 8-Lead (DFN-S) Plastic Micro Small Outline – 8-Lead (MSOP) Plastic Dual In-Line – 300 mil Body, 8-Lead (PDIP) Plastic Small Outline - Narrow, 3.90 mm Body, 8-Lead (SOIC) Plastic Small Outline - Medium, 5.28 mm Body, 8-Lead (SOIJ) Plastic Small Outline Transistor – 5-Lead (SOT-23) (Tape and Reel only) Plastic Dual Flat, No Lead Package – 2x3x0.8 mm Body, 8-Lead (TDFN) Plastic Thin Shrink Small Outline – 4.4 mm Body, 8-Lead (TSSOP) Examples a) 24AA64-I/P: 64-Kbit I 2C Serial EEPROM, Industrial temp., PDIP package. b) 24AA64-I/SN: 64-Kbit I 2C Serial EEPROM, Industrial temp., SOIC package. c) 24AA64-I/SM: 64-Kbit I 2C Serial EEPROM, Industrial temp., SOIJ package. d) 24AA64T-I/ST: 64-Kbit I 2C Serial EEPROM, Tape and Reel, Industrial temp., TSSOP package. e) 24LC64-I/P: 64-Kbit I 2C Serial EEPROM, Industrial temp., PDIP package. f) 24LC64-E/SN: 64-Kbit I 2C Serial EEPROM, Extended temp., SOIC package. g) 24LC64-E/SM: 64-Kbit, I 2C Serial EEPROM, Extended temp., SOIJ package. h) 24LC64-I/ST: 64-Kbit, I 2C Serial EEPROM, Industrial temp., TSSOP package. i) 24AA64T-I/CS16K: 64-Kbit, I 2C Serial EEPROM, Tape and Reel, Industrial temp., CS package. j) 24AA64T-E/SN: 64-Kbit, I 2C Serial EEPROM, Tape and Reel, Extended temp., SOIC package. Option Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Micro- chip Sales Office for package availability with the Tape and Reel option. 2: “16K” indicates 160K technology (1) (1) Temperature Range

 1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 49 24AA64/24FC64/24LC64 PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTape and ReelDevice Device: 24AA64 = 24LC64 = 1.7V, 64-Kbit I2C Serial EEPROM 2.5V, 64-Kbit I2C Serial EEPROM Tape and Reel Option: Blank = T = Standard packaging (tube) Tape and Reel Temperature Range: I = E = -40C to +85C (AEC-Q100 Grade 3) -40C to +125C (AEC-Q100 Grade 1) Package: MS = SN = OT = ST = MNY = Plastic Micro Small Outline – 8-Lead (MSOP) Plastic Small Outline - Narrow, 3.90 mm (.150 ln) Body, 8-Lead (SOIC) Plastic Small Outline Transistor – 5-Lead (SOT-23) (Tape and Reel only) Plastic Thin Shrink Small Outline – 4x4 mm Body, 8-Lead (TSSOP) Plastic Dual Flat, No Lead Package – 2x3x0.8 mm Body, 8-Lead (TDFN) Variant: (2,3) 15KVAO = 15KVXX = 16KVAO = 16KVXX = Standard Automotive, 15K Process(4) Customer-Specific Automotive, 15K Process(4) Standard Automotive, 16K Process Customer-Specific Automotive, 16K Process Examples a) 24LC64T-E/SN16KVAO: 2.5V, 64-Kbit I 2C Serial EEPROM, Automotive Grade 1, Tape and Reel, SOIC package. b) 24LC64T-I/ST16KVAO: 2.5V, 64-Kbit I 2C Serial EEPROM, Automotive Grade 3, Tape and Reel, TSSOP package. c) 24AA64T-E/MNY16KVAO: 1.7V, 64-Kbit I 2C Serial EEPROM, Automotive Grade 1, Tape and Reel, TDFN package. d) 24LC64T-E/OT16KVAO: 2.5V, 64-Kbit I 2C Serial EEPROM, Automotive Grade 1, Tape and Reel, SOT-23 package. Option Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Micro- chip Sales Office for package availability with the Tape and Reel option. 2: The VAO/VXX automotive variants have been designed, manufactured, tested and qualified in accordance with AEC-Q100 requirements for automotive applications. 3: For customers requesting a PPAP, a cus- tomer-specific part number will be generated and provided. A PPAP is not provided for VAO part numbers. 4: Not recommended for new designs. (1) (1) Temperature Range XXX Variant (2,3)

DS20001189U-page 50  1997-2022 Microchip Technology Inc. and its subsidiaries This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtai n additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1997-2022, Microchip Technology Incorporated and its subsidiar- ies. All Rights Reserved. ISBN: 978-1-5224-9792-9 Note the following details of the code protection feature on Microchip products:

Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure w hen used in the intended manner, within operating specifications, and under normal conditions.
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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Selected Specification

Microchip Technology 24LC64T-I/MNY16KVXX overview.

Overview

24LC64T-I/MNY16KVXX is listed in the Memory category. Available datasheets include documents from Microchip Technology. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

64-Kbit I2C Serial EEPROM 09/14/21

Description

64-Kbit I2C Serial EEPROM 09/14/21

Source title 24LC64T-I/MNY16KVXX Datasheet(PDF) - Microchip Technology

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