20XS4200

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Document overview

• Manufacturer or author: NXP B.V.
• PDF pages: 71

Technical content

Features

• Two fully-protected 20 m Ω (@ 25 °C) high-side switches
• Up to 4.4 A steady state current per channel
• Separate bulb and DC motor latched overcurrent handling
• Individually programmable internal/external PWM clock signals
• Overcurrent, short-circuit, and overtemperature protection with programmable autoretry functions
• Accurate temperature and current sensing
• Openload detection (channel in OFF and ON state), also for LED applications (7.0 mA typ.)
• Normal operating range: 8.0 to 36 V, extended range: 6.0 to 58 V
• 3.3 V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz

Figure 1. Simplified application diagram

23 PIN PQFN

3 NXP Semiconductors

1 Orderable parts

Table 1. Simplified orderable part variations table (1)

1. To order parts in tape and reel, add the R2 suffix to the part number.
2. Recommended for all new designs.
3. Version B and D, BA and BD devices can support negative voltage battery and ground loss down to -32V, the overcurrent profile can be selected
4. Version BA and BD devices have faster slew rates to reduce switching losses.

2 Internal block diagram

Figure 2. Internal block diagram

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3 Pin assignment

Figure 3. 20XS4200 device pin assignments Table 2. 20XS4200 pin description

1 CSNS Output Output Current/

connected between CSNS and GND. to GND by internal pull-down resistors.

4 FSOB Output Fail-safe Output

7 FSB Output Fault Status

device enters Fault mode (see Fault mode).

8 CLOCK Input PWM Clock

This pin has an internal pull-down current source.

9 RSTB Input Reset

by direct input signals.This pin is connected to GND by an internal pull-down resistor.

10 CSB Input Chip Select

internally connected to a pull-down current source IDWN.

12 SI Input Serial Input

connected to a pull-down current source IDWN. 13 VDD Power Digital Drain Voltage This is the positive supply pin of the SPI interface.

16 SO Output Serial Output

current consumption in case of GND disconnection. circuitry. It is recommended to also connect these pins on the PCB. them. Pin 15 is the device’s primary thermal pad. HS0 Output Power Switch Outputs Output pins of the switches, to be connected to the load.

23 SYNC Output

operating mode. SYNC is open-drain and requires a pull-up resistor to VDD. Table 2. 20XS4200 pin description (continued)

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4 Electrical characteristics

4.1 Maximum ratings

Table 3. Maximum ratings All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

• Load dump at 25 °C (350 ms)
• Reverse battery at 25 °C 20XS4200FK 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK
• Fast negative transient pulses (ISO 7637-2 pulse #1, V PWR=28 V & Ri=10 Ω) VPWR -28 -32 -60 V VDD supply voltage range V DD -0.3 to 5.5 V Voltage on input pins (5) (except IN[0:1]) and Output pins (6)) (except HS[0:1]) V MAX,LOGIC (5) -0.3 to 5.5 V Voltage on Fail-safe output (FSOB) V FSO -0.3 to 58 V Voltage on SO pin VSO -0.3 to VDD+0.3 V Voltage (continuous, max. allowable) on IN[0:1] inputs V IN,MAX 58 V Voltage (continuous, max. allowable) on output pins (HS [0:1]) 20XS4200FK 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK VHS[0:1] -28 to 58 -32 to 58 V Rated continuous output current per channel (7) IHS[0:1] 4.4 A Maximum allowable energy dissipation per channel and two parallel channels, single- pulse method (8) ECL[0:1]_SING 70 mJ Notes: 5. Concerned Input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, and CSB. 6. Concerned Output pins are: CSNS, SYNC, and FSB. 7. Output current rating valid as long as ma ximum junction temperature is not exceeded. For computation of the maximum allowable output current, the thermal resistance of the package & the underlying heatsink must be taken into account 8. Single pulse Energy dissipation, Single-pulse short-circuit method (LL = 0.5 mH, R = 48 mΩ VPWR =2 8V , TJ = 150 °C initial).

• Human Body Model (HBM) for HS[0:1], VPWR and GND
• Human Body Model (HBM) for other pins
• Charge Device Model (CDM) Package corner pins All other pins V ESD1 VESD2 VESD3 VESD4 ±8000 ±2000 ±750 ±500 V Thermal ratings Operating temperature
• A m b i e n t
• J u n c t i o n T A TJ -40 to 125 -40 to 150 Storage temperature TSTG -55 to 150 °C Thermal Resistance Junction to Case Bottom / VPWR Flag Surface R θJC 0.32 °C/W Peak package reflow temperature during reflow(10),(11) TPPRT Note 11 °C Notes: 9. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 10. Pin soldering temperature limit is for 40 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 11. NXP’s Package Reflow capability meets Pb -free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes), and the core ID to view all orderable parts, and review parametrics.

Table 3. Maximum ratings (continued) All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

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4.2 Static electrical characteristics

Table 4. Static electrical characteristics values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

• Full specification compliant
• Extended mode(12) VPWR 8.0 6.0 58 V VPWR supply current, device in wake-up mode, channel on, openload
• Outputs in ON state, HS[0:1] open, IN[0:1] > VIH IPWR(ON) –6 . 5 8 . 0 mA VPWR supply current, device in wake-up mode (Standby), channel Off openload in OFF state detection disabled, HS[0:1] shorted to ground with VDD = 5.5 V and RSTB > VWAKE 20XS4200FK 20XS4200BAFK and 20XS4200BDFK IPWR(SBY) 6.5 6.5 8.0 8.5 mA Sleep state supply current VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0:1] connected to ground
• T A =2 5° C
• T A =1 2 5° C IPWR(SLEEP) – 3.0 10.0 60.0 μA VDD supply voltage V DD(ON) 3.0 – 5.5 V VDD supply current at VDD = 5.5 V
• No SPI communication
• 8.0 MHz SPI communication(13) IDD(ON) – 5.0 2.2 mA VDD sleep state current at VDD = 5.5 V with or without VPWR IDD(SLEEP) –– 5 . 0 μA Overvoltage shutdown threshold V PWR(OV) 39 42 45.5 V Overvoltage shutdown hysteresis V PWR(OVHYS) 0.2 0.8 1.5 V Undervoltage shutdown threshold(14) VPWR(UV) 5.0 – 6.0 V VPWR power-on reset (POR) voltage threshold(14) VPWR(POR) 2.2 2.6 4.0 V VDD power-on reset (POR) voltage threshold(14) VDD(POR) 1.5 2.0 2.5 V VDD supply failure voltage threshold (assumed VPWR > VPWR(UV))V DD(FAIL) 2.2 2.5 2.8 V Notes 12. In extended mode, availability of several device functions (channel control, value of RDS(ON), overtemperature protection) is guaranteed, but compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown). Above VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled. 13. Typical value guaranteed per design. 14. When the device recovers from undervoltage and returns to normal mode (6.0 V < V PWR < 58 V) before the end of the auto-retry period (see Auto- retry), the device performs normally. When VPWR drops below VPWR(UV), undervoltage is detected (see Undervoltage fault (Latchable fault) and EMC Performances).

• V PWR =8 . 0V
• V PWR =2 8V
• V PWR =3 6V RDS(ON)25 – mΩ ON-Resistance, Drain-to-Source (I HS =3 . 0A , TJ = 150 °C) CSNS_ratio = 0
• V PWR = 8.0 V
• V PWR =2 8V
• V PWR =3 6V RDS(ON)150 – mΩ ON-Resistance, Drain-to-Source difference from one channel to the other in parallel mode (I HS =1 . 0A , TJ = 150 °C) CSNS_ratio = X ΔRDS(ON)150 -0.9 – +0.9 mΩ ON-Resistance, Source-Drain (IHS =- 3 . 0A , TJ = 150 °C, VPWR =- 2 4V ) RSD(ON)150 ––3 6 m Ω Max. detectable wiring length (2.5 mm²) for severe short-circuit detection (see Severe short-circuit fault (Latchable fault)): 20XS4200FK, 20XS4200BFK and 20XS4200DFK
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected 20XS4200BAFK and 20XS4200BDFK
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected L SHORT 100 200 110 130 260 500 100 175 365 300 600 1200 180 300 620 cm Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0) I _OCH1_0 I_OCH2_0 I_OCM1_0 I_OCM2_0 I_OCL1_0 I_OCL2_0 I_OCL3_0 27.5 17.5 10.8 6.7 4.5 3.0 1.5 33.0 21.0 13.0 8.0 5.4 3.6 1.8 38.5 24.5 15.2 9.3 6.3 4.2 2.1 A Overcurrent detection thresholds with CSNS_ratio bit = 1(CSR1) I _OCH1_1 I_OCH2_1 I_OCM1_1 I_OCM2_1 I_OCL1_1 I_OCL2_1 I_OCL3_1 9.2 5.8 3.6 2.2 1.5 1.0 0.48 11.0 7.0 4.3 2.7 1.8 1.2 0.6 12.8 8.2 5.1 3.1 2.1 1.4 0.72 A

Table 4. Static electrical characteristics (continued) values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

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• V HS,OFF =0V ( VHS,OFF = output voltage in OFF state)
• V HS,OFF =V PWR, device in sleep state (VPWR =2 4V ) 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK
• V HS,OFF =0V ( VHS,OFF = output voltage in OFF state)
• V HS,OFF =V PWR, device in sleep state (VPWR =2 4V )
• V HS,OFF =V PWR, device in sleep state (VPWR =3 6V ) IOUT_LEAK -40.0 -120 -1400 +16 +5.0 +16 +5.0 +5.0 µA Output biasing current in OFF state (positive value = outgoing) 20XS4200BFK and 20XS4200DFK with OL_OFF disabled (worst case for V PWR = 36 V, VHS,OFF = 34 V)
• Fast slew rate selected
• Medium slew rate selected
• Slow slew rate selected
• With OL_OFF disabled and ECU ground disconnected (V PWR = 32 V) 20XS4200BAFK and 20XS4200BDFK with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
• Fast slew rate selected Medium slew rate selected Slow slew rate selected I OUT_OFF -500 -370 -300 -620 -440 -330 -400 -300 -250 -495 -360 -280 -300 -230 -200 1000 -380 -280 -230 µA Switch turn-on threshold for supply overvoltage (V PWR -GND) V D_GND(CLAMP) 58 – 66 V Switch turn-on threshold for Drain-Source overvoltage (measured at IOUT =5 0 0m A VDS(CLAMP) 58 – 66 V Switch turn-on threshold for Drain-Source overvoltage difference from one channel to the other in parallel mode (@ IHS = 500 mA) ΔVDS(CLAMP) -2.0 – +2.0 V Current sensing ratio(15)
• CSNS_ratio bit = 0 (high current mode)
• CSNS_ratio bit = 1 (low current mode) CSR0 CSR1 Minimum measurable load current with compensated error(16) I _LOAD_MIN ––5 0 m A CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0)I CSR_LEAK -4.0 – +4.0 µA Systematic offset error (see Current sense errors)
• 20XS4200FK
• 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK I _LOAD_ERR_SYS – 5.5 mA Random offset error I _LOAD_ERR_RAND -125 – 125 mA Notes: 15. Current Sense Ratio C SRx =I CSNS / (IHS[x] +I_LOAD_ERR_SYS) 16. See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration.

values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A T J=125 °C
• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A T J=25 to 125 °C
• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A E SR0_ERR -13 -12 -17 -31 -10 -9.0 -12 -19 -10 -9.0 -12 -22 9.0 9.0 E SR0 output current sensing error (% after offset compensation(17) at output current level (sense ratio CSR0 selected): TJ=-40 °C
• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A T J=125 °C
• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A T J=25 to 125 °C
• 3 . 0 A
• 1 . 5 A
• 0 . 7 5 A
• 0.375 A E SR0_ERR(Comp) -10 -10 -10 -10 -9.0 -8.0 -8.0 -9.0 -9.0 -8.0 -8.0 -9.0 9.0 8.0 8.0 9.0 9.0 8.0 8.0 9.0 Notes: 17. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS

values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

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• 0 . 7 5 A TJ=125 °C
• 0 . 7 5 A TJ=25 to 125 °C
• 0 . 7 5 A ESR1_ERR -15 -12 -12 E SR1 output current sensing error (% after offset compensation(19) at output current level (sense ratio CSR1 selected): TJ=-40 °C
• 0 . 7 5 A
• 0 . 2 5 A
• 0.125 A
• 0.075 A T J=125 °C
• 0 . 7 5 A
• 0 . 2 5 A
• 0.125 A
• 0.075 A T J=25 to 125 °C
• 0 . 7 5 A
• 0 . 2 5 A
• 0.125 A
• 0.075 A E SR1_ERR(Comp) -10 -11 -18 -29 -8.0 -10 -12 -16 -8.0 -10 -13 -21 8.0 8.0 E SR0 output current sensing error in parallel mode (%, uncompensated(20)) at outputs current level (Sense ratio CSR0 selected): TJ=-40 °C
• 6 . 0 A
• 3 . 0 A T J=125 °C
• 6 . 0 A
• 3 . 0 A T J=25 to 125 °C
• 6 . 0 A
• 3 . 0 A E SR0_ERR_PAR -10 -11 -8.0 -8.0 -8.0 -8.0 8.0 8.0 8.0 8.0 Notes: 18. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS 19. See note (21), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration 20. Minimum required value of openload impedance for detection of openload in OFF state: 200 k Ω.(VOLD(THRES) =V HS @ IOLD(OFF))

values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

• CSNS_ratio bit = 0 20XS4200FK 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK
• CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this function) I OLD(ON) 60 5.0 150 150 7.0 300 300 mA Time period of the periodically activated openload in ON state detection for CSNS_ratio bit = 1 tOLLED 105 150 195 ms Output shorted-to-VPWR detection voltage threshold (channel in OFF state) V OSD(THRES) VPWR-1.2 V PWR-0.8 V PWR-0.4 V Switch turn-on threshold for negative output voltages (protects against negative transients) - (measured at IOUT = 100 mA, Channel in OFF state) 20XS4200FK 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK, and 20XS4200BDFK VCL -35 -38 -24 -32 V Switch turn-on threshold for Negative Output Voltages difference from one channel to the other in parallel mode - (measured at IOUT = 100 mA, channel in OFF state) ΔVCL -2.0 – +2.0 V Switching state (ON/OFF) discrimination thresholds V HS_TH 0.45*VPWR 0.5*VPWR 0.55*VPWR V Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V) T SD 160 175 190 °C Notes: 21. Minimum required value of openload impedance for detection of openload in OFF state: 200 k Ω.(VOLD(THRES) =V HS @ IOLD(OFF))

values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

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• ( IOH =1 . 0m A ) VSOH VDD-0.4 – – V SYNC, SO, FSOB and FSB low state output voltage
• ( IOL =- 1 . 0m A ) VSOL – – 0.4 V SYNC, SO, CSNS, FSOB and FSB tri-state leakage current:
• (0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or V(CSNS) = 0.0 V ISO(LEAK) -2.0 0.0 2.0 μA CONF[0:1]: required values of the external pull-down resistor
• Lighting applications
• DC motor applications RCONF 1.0 Infinite kΩ Notes 22. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN [0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR and can tolerate voltages up to 58 V. 23. Voltage above which the device wakes up 25. Valid for V CSB < 2.0 V. CSB has an internal pull-up current source derived from VDD 26. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V). 27. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production.

values evaluated under nominal conditions TA =2 5° C , VPWR =2 8V & VDD = 5.0 V, unless specified otherwise.

4.3 Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 20XS4200BAFK and 20XS4200BDFK
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V SRR_00 SRF_00 0.164 0.28 0.34 0.25 0.45 0.5 0.65 0.79 0.90 1.1 1.4 1.5 V/μs Rising and falling edges low slew rate (SR[1:0] = 01) (28) 20XS4200FK, 20XS4200BFK and 20XS4200DFK
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 20XS4200BAFK and 20XS4200BDFK
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V SRR_01 SRF_01 0.081 0.14 0.17 0.125 0.225 0.25 0.32 0.395 0.45 0.55 0.7 0.75 V/μs Rising and falling edges high slew rate / SR[1:0] = 10) (28) 20XS4200FK, 20XS4200BFK and 20XS4200DFK
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 20XS4200BAFK and 20XS4200BDFK
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V SRR_10 SRF_10 0.29 0.55 0.68 0.5 0.9 1.0 1.30 1.58 1.80 2.2 2.8 3.0 V/μs Notes 28. Rising and Falling edge slew rates specified for a 20 % to 80 % voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay).

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• 1 6 V < VPWR < 36 V 20XS4200FK 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK ΔSR 0.75 0.75 1.0 1.0 1.2 1.25 Edge slew rate difference from one channel to the other in parallel mode(29) 20XS4200FK, 20XS4200BFK and 20XS4200DFK

16 V < VPWR < 36 V

16 V < V

• 1 6 V < VPWR < 36 V 20XS4200FK, 20XS4200BFK and 20XS4200DFK 20XS4200BAFK and 20XS4200BDFK tDLY_00 32 128 120 μs Output turn-on and turn-off delays (low slew rate / SR[1:0] = 01)(30)
• 1 6 V < VPWR < 36 V 20XS4200FK, 20XS4200BFK and 20XS4200DFK 20XS4200BAFK and 20XS4200BDFK tDLY_01 59 245 240 μs Output turn-on and turn-off delays (high slew rate / SR[1:0] = 10)(30)
• 1 6 V < VPWR < 36 V 20XS4200FK, 20XS4200BFK and 20XS4200DFK 20XS4200BAFK and 20XS4200BDFK tDLY_10 18 μs Turn-on and turn-off delay time matching (tDLY(ON) - tDLY(OFF))
• f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 00 ΔtRF_00 -25 0.0 25 μs Turn-on and turn-off delay time matching (tDLY(ON) - tDLY(OFF))
• f PWM = 200 Hz, 16 V < V PWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 01 20XS4200FK, 20XS4200BAFK and 20XS4200BDFK 20XS4200BFK and 20XS4200DFK ΔtRF_01 -50 -90 0.0 μs Notes 29. Rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay). 30. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0:1] = 1) and the associated risi ng edge of the output voltage up to: VHS[0:1] = VPWR / 2 (where RL = 10.0 Ω). Turn-OFF delay time is measured as time between a falling edge of the channel control signal (IN[0:1] = 0) and the associated falling edge of the output voltage up to the instant at which: VHS[0:1] = VPWR / 2 (RL = 10.0 Ω)

Table 5. Dynamic electrical characteristics (continued) values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

• f PWM = 1.0 kHz, 16 V < V PWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 10 ΔtRF_10 -13 0.0 13 μs Delay time difference from one channel to the other in parallel mode(31)

1. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and
2. Time required to detect and report the fault to the FSB pin.
3. Time required to switch off the channel after detection of over temperature (OT), overcurrent (OC), SC or UV error (time measured between start
4. Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = tSYNCVAL_XX) and Read-out delay ( = tSYNREAD_XX) are defined for a stepped load

Output current monitoring (CSNS). values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

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1. Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = tSYNCVAL_XX) and Read-out delay ( = tSYNREAD_XX) are defined for a stepped load

Output current monitoring (CSNS). VHS =5 0% VPWR. For low duty-cycle values, the effective value also depends on the value of the selected slew rate. values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

• O L _ O F F
• O L _ O N
• O S R PWM_1K_H 0.0 0.0 100 Available duty cycle range, f PWM = 400 Hz, medium slew rate, PWM mode(37)
• O L _ O F F
• O L _ O N
• O S R PWM_400_M 0.0 0.0 100 Available duty cycle range, f PWM = 400 Hz, high slew rate, PWM mode(37)
• O L _ O F F
• O L _ O N
• O S R PWM_400_H 0.0 0.0 100 Available duty cycle range, f PWM = 200 Hz, low slew rate mode, PWM mode(37)
• O L _ O F F
• O L _ O N
• O S R PWM_200_L 0.0 0.0 100 Available duty cycle range, f PWM = 200 Hz, medium slew rate, PWM mode(37)
• O L _ O F F
• O L _ O N
• O S R PWM_200_M 0.0 0.0 100 Available duty cycle range, f PWM = 100 Hz in low slew rate, PWM mode(37)
• O L _ O F F
• O L _ O N
• O S R PWM_100_L 0.0 8.0 0.0 100 Deviation of the internal clock PWM frequency after calibration (38) AFPWM(CAL) -10 – +10 % Default output frequency when using an uncalibrated oscillator f PWM(0) 280 400 520 Hz Minimal required low time during calibration of the internal clock through CSB t CSB(MIN) 1.0 1.5 2.0 μs Maximal allowed low time during calibration of the internal clock through CSB t CSB(MAX) 70 100 130 μs Recommended external clock frequency range (external clock/PWM module) f CLOCK 15 – 512 kHz Upper detection threshold for external clock frequency monitoring f CLOCK(MAX) 512 730 930 kHz Lower detection threshold for external clock frequency monitoring f CLOCK(MIN) 5.0 7.0 10 kHz Notes 37. The device can be operated outside the spec ified duty cycle and frequency ranges (basic protective functions OC, SC, UV, OV, OT remain active) but the availability of the diagnostic functions OL_ON, OL_OFF, OS is affected. 38. Values guaranteed from 60 Hz to 1.0 kHz (recommended sw itching frequency range for internal clock operation).

values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

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• Auto_period bits = 00
• Auto_period bits = 01
• Auto_period bits = 10
• Auto_period bits = 11 t AUTO_00 tAUTO_01 tAUTO_10 tAUTO_11 105 52.5 26.2 13.1 150 37.5 17.7 195 97.5 47.8 24.4 ms GND pin temperature sensing function Thermal prewarning detection threshold (40) TOTWAR 110 125 140 °C Temperature sensing output voltage @ TA = 25 °C (470 Ω < RCSNS < 10 kΩ) TFEED 918 1078 1238 mV Gain temperature sensing output @ TA = 25 °C (470 Ω < RCSNS < 10 kΩ)(40) DTFEED 10.7 11.1 11.5 mV/°C Temperature sensing error, range [-40 °C, 150 °C], default(40) TFEED_ERROR -15 – +15 °C Temperature sensing error, [-40 °C, 150 °C] after 1 point calibration @ 25 °C(40) TFEED_ERROR _CAL -5.0 – +5.0 °C Notes 39. Only when the WD_dis bit set to logic [0] (default). Watchdog timeout defined from the rising edge on RST to rising edge HS[0,1] 40. Values were obtained by lab. characterization

values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

• C L =8 0p F tRSO – – 20 ns SO fall time
• C L =8 0p F tFSO – – 20 ns SI, CSB, SCLK, max. rise time allowing operation at fSPI =8 . 0M H z(45) tRSI – – 11 ns SI, CSB, SCLK, max. fall time allowing operation at fSPI =8 . 0M H z(45) tFSI – – 11 ns Time from rising edge of SCLK to reach a valid level at the SO pin(46) tVALID – – 44 ns Time from falling edge of CSB to reach low-impedance on SO (access time)(47) tSOEN – – 30 ns Notes: 41. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k 42. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V) ceramic speed-up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, CS 43. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs inactive). 44. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state. 45. Rise and Fall time of incoming SI, CSB, and SCLK signals. 46. Time required for output data to be availa ble for use at SO, measured with a 1.0 kΩ series resistor connected CSB. 47. Time required for output data to be terminated at SO measured with a 1.0 k Ω series resistor connected CSB.

values evaluated under nominal conditions TA = 25 °C,VPWR =2 8 V & VDD = 5.0 V, unless specified otherwise.

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4.4 Timing diagrams

Figure 4. Output voltage slew rate and delay Figure 5. Overcurrent protection profile for bulb applications Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V). Static overcurrent protection profile activated once per turn-on.

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Figure 8. Timing diagram for Serial Output (SO) data communication Figure 9. Synchronous and Track & Hold current sensing modes: associated delay and settling times

5 Functional description

5.1 Introduction

The 20XS4200 is a two-channel, 24 V high side switch with integrated control and diagnostics designed for truck, bus, and industrial applications. The device provides a high number of protective functions. Both low RDS(on) channels (<20 mΩ) can independently drive various load types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy chain capability. Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels can independently be operated in three different switching modes: internal clock and internal PWM mode (fully autonomous operation), external clock and internal PWM mode, and direct control switching mode. Current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (LED) monitoring. By activating the Track & Hold Mode, current monitoring can be performed during the switch-Off phase. This allows random access to the current sense functionality. A patented offset compensation technique further enhances current sense accuracy. To avoid turning off upon inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be protected from overheating by activating a specific window-shaped overcurrent profile that allow stall currents of limited duration. Whenever communication with the external micro-controller is lost, the device enters Fail-safe operation mode, but remains operational, controllable, and protected.

5.2 Pin assignment and functions

Functions and register bits that are implemented independently for both channels have extension “_s”. Max. ratings of the pins are given in Table 3.

5.2.1 Output current monitoring (CSNS)

The CS pin allows independent current monitoring of channel 0 or channel 1 up to the steady state overcurrent threshold. It can also be used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate value (Table 23). When the CSNS pin is sensed during switch-off in the (optional) track & hold mode (see Figure 9), it outputs the scaled value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of devices the current of which is not monitored must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in the GCR register (Table 10). Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage’s rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS-pin has settled to ±5.0% of its final value. Anytime an overcurrent window is active, the CSNS pin is disabled (see Overcurrent detection on resistive and inductive loads). The current and temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In order to generate a voltage output, a pull-down resistor is required (R(CSNS)=1.0 kΩ typ. and 470 < R(CSNS) < 10 k). When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents up to about 5.6 mA.

5.2.2 Current sense synchronization (SYNC)

To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. SYNC is asserted logic low when the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the specified accuracy tSYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is generated. The rising edge that is generated by the SYNC pin at the turn-OFF instant (internal or external) may also be used to implement synchronization with the external MCU. Parameter tSYNCVAL_XX is defined as the time between the instant at the middle of the output- voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC pins of different devices can be connected together to save µ-controller input channels. However, in this configuration, the CSNS function of only one device should be active at a time. Otherwise, the MCU does not determine the origin of the SYNC signal. The SYNC pin is open drain and requires an external pull-up resistor to VDD.

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5.2.3 Direct control inputs (IN0 and IN1)

The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on (Channel control in Normal mode). When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wake it up (Sleep mode). If it is desired to automatically turn on the channels after a transition to Fail-safe mode, inputs IN[0] and IN[1] must be externally connected internally connected to a pull-down resistor.

5.2.4 Configuration inpu ts (CONF0 and CONF1)

The CONF[0:1] input pins allow configuring both channels for the appropriate load type. CONF = 0 activates the bulb overcurrent protection profile, and CONF = 1 the DC motor profile. These inputs are connected to an internal voltage regulator of 3.3 V by an internal pull-up current source IUP. Therefore, CONF = 1 is the default value when these pins are disconnected. Details on how to configure the channels are given in Table 9.

5.2.5 Fault status (FSB)

This open-drain output is asserted low when any of the following faults occurs (see Fault mode): overcurrent (OC), overtemperature (OT), Output connected to VPWR, Severe short-circuit (SC), openload in ON state (OL_ON), openload in OFF state (OL_OFF), External Clock- fail (CLOCK_fail), overvoltage (OV), undervoltage (UV). Each fault type has its own assigned bit inside the STATR, FAULTR_s, or DIAGR_s register. Fault type identification and fault bit reset are accomplished by reading out these registers. They are part of the SO register (Fault mode) and are accessed through the SPI port.

5.2.6 PWM clock (CLOCK)

This pin is the input for an external clock signal that controls the internal PWM module.The clock signal is monitored by the device. The PWM module controls ON-time and turn-ON delay of the selected channels. The CLOCK pin should not be confused with the SCLK pin, which is the clock pin of the SPI interface. CLOCK has an internal pull-down current source (IDWN) to GND.

5.2.7 Reset (RSTB)

All SPI register contents are reset when RSTB = 0. When RSTB = 0, the device returns to Sleep mode tIN sec. after the last falling edge of the last active IN[0:1] signal. As long as the Reset input (RSTB pin) is at logic 0 and both direct input states are low, the device remains in Sleep mode (Channel configuration through the SPI). A 0-to-1 transition on RSTB wakes up the device and starts a watchdog timer to check the continuous presence of the SPI signals. To do this, the device monitors the contents of the first bit (WDIN bit) of all SPI words following that transition (regardless the register it is contained in). When this contents is not alternated within a duration tWDTO, SPI communication is considered lost, and Fail-safe mode is entered (Entering Fail-safe mode). RSTB is internally pulled-down to GND by resistor RDWN.

5.2.8 Chip Select (CSB)

Data communication over the SPI port is enabled when the CSB pin is in the logic [0] state. Data from the Input Shift registers are locked in the addressed SI registers on the rising edge of CSB. The device transfers the contents of one of the eight internal registers to the SO register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is at logic [0] (Figure 7 and Figure 8). CSB is internally pulled up to VDD through IUP.

5.2.9 SPI serial clock (SCLK)

The SCLK pin clocks the SPI data communication of the device. The serial input pin (SI) transfers data to the SI shift registers on the falling edge of the SCLK signal while data in the SO registers are transferred to the SO pin on the rising edge of the SCLK signal. The SCLK pin must be in low state when CSB makes any transition. For this reason, it is recommended to have the SCLK pin in the logic [0] state when the device is not accessed (CSB is at logic [1]). When CSB is set to logic [1], the signals at the SCLK and SI pins are ignored and the SO output is tri-stated (high-impedance). The SCLK pin is connected to an internal pull-down current source IDWN.

5.2.10 Serial input (SI)

Serial input (SI) data bits are shifted in at this pin. SI data is read on the falling edge of SCLK. 16-bit data packages are required on the SI pin (see Figure 7), starting with bit D15 (MSB) and ending with D0 (LSB). All the internal device registers are addressed and controlled by a 4-bit address (D9-D12) described in Table 14. Register addresses and function attribution are described in Table 15. The SI pin is internally connected to a pull-down current source, IDWN.

5.2.11 Supply of the digital circuitry (VDD)

This pin supplies the SPI circuit (3.3 V or 5.0 V). When lost, all circuitry becomes supplied by a VPWR derived voltage, except the SPI’s SO shift-register that can no longer be read.

5.2.12 Ground (GND)

This is the GND pin common for both the SPI and the other circuitry.

5.2.13 Positive supply pin (VPWR)

This pin is the positive supply and the common input pin of both switches. A 100 nF ceramic capacitor must be connected between VPWR and GND, close to the device. In addition, it is recommended to put a ceramic capacitor of at least 1.0 µF in parallel with this 100 nF capacitor.

5.2.14 Serial output (SO)

The SO pin is a tri-stateable output pin that conveys data from one of the 13 internal SO registers or from the previous SI register to the outside world. The SO pin remains in a high-impedance state (tri-state) until the CSB pin becomes logic [0]. It then transfers the SPI data (device state, configuration, fault information). The SO pin changes state at the rising edge of the SCLK signal. For daisy-chaining, it can be read out on the falling edge of SCLK. VDD must be present before the SO registers can be read. The SO register assignment is described in Table 13.

5.2.15 Power switch outp ut pins (HS0 and HS1)

HS0 and HS1 are the output pins of the power switches, to be connected to the loads. A ceramic capacitor (<= 22 nF (+/- 20%) is recommended between these pins and GND for optimal EMC performances.

5.2.16 Fail-safe output (FSOB)

This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This open-drain output requires an external pull-up resistor to VPWR.

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5.3 Functional internal block description

Figure 10. Internal block description

5.3.1 Power supply

guarantees a low quiescent current in Sleep mode.

5.3.2 Switch output pins HS0 and HS1

active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available. parallel, which guarantees good switching synchronization.

5.3.3 Communication interface and device control

or by a 3.3 V voltage supply. For direct input control, VDD is not required. communication is required to set these options.

6 Functional device operation

6.1 Operation and operating modes

The device possesses two high side switches (channels) each of which can be controlled independently. The device has four fundamental operating modes: Sleep, Normal, Fail-safe, and Fault mode, as shown in Table 6. Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal (autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required (VDD = 5.0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD isn’t required.

6.1.1 Device start-up sequence

To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However, it should not be woken up earlier than the moment at which VPWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting RSTB=1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ]= 1 (see Figure 11). After wake-up, all SPI register contents are reset (as defined in Table 12 and Table 13) and Normal mode is entered. All the device functions are available 50 µs later (typically). If the start-up sequence is not performed at device start-up, its configuration may be undetermined and correct operation is not guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment VPWR has reached the undervoltage threshold.

6.1.2 Channel configuration through the SPI

6.1.2.1 Setting the channel configuration

The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent (OCR_s) registers. They allow setting, among others, the following parameters: duty-cycle, delay, Slew Rate, PWM enable (PWM_en), clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension “_s” means that these registers exist for each of both channels. Function assignment is described in detail in the section SI register addressing.

6.1.2.2 Reading back the chan nel’s status and settings

The channel’s global switching and operating states (ON/OFF, normal/fault) are all contained in the SO-STATR register (see Table 16). The precise fault type can be found by reading out the FAULTR_s and STATR registers. The current channel settings (channel configuration) can be known by reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG registers (see section Serial output register assignment and beyond).

6.1.3 Normal mode

Normal mode (bit NM = 1) can be entered in two ways: either by driving the device through the direct inputs (IN[x]) or by establishing SPI communication (requires RSTB =high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the device in Normal mode, communication must take place regularly (see Entering and maintaining Normal mode). The device is in Normal mode (NM) when:

• V PWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• f a u l t = 0 .

6.1.3.1 Channel contr ol in Normal mode

In direct input mode, the channel’s switching state (ON/OFF) is controlled by the logic state of the direct input signal with the default values (00) of turn-on delay and slew rate, specified in Table 5.

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In internal clock mode, the switching state is controlled by an internal clock signal (Internal clock and internal PWM (Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and turn-on delay are programmable independently for both channels. delay are still programmable.

6.1.3.2 Factors determining the channel’s switching state

controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)].

• short-circuits to GND, before automatic turn-Off (t < t FAULT)
• short-circuits to V PWR when the channel is set to Off
• V PWR < 13 V when openload in OFF state detection is selected and the load is actually lost
• during the turn-on transition as long as V(HS[x])< V PWR/2
• during the turn-off transition as long as V(HS[x]) > V PWR/2

6.1.3.3 Entering and maintaining Normal mode

must take place on a regular basis. mode), provided reset = RSTB =0 . Figure 11. Relation between signals IN(x) and IN_ON[x]

6.1.3.4 Direct control mode

6.1.3.5 Going from Normal to Fa il-safe, Fault or Sleep mode

value of the following signals (see Table 6).

• wake-up = RSTB or IN_ON[0] or IN_ON[1]
• fail-safe = (V DD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0)
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis ) It enters Fail-safe mode in case of a timeout on SPI communication or when VDD is lost after having been initially present (if this function was previously enabled by setting: VDD_FAIL_EN bit = [1]). Setting watchdog disabled (WD_dis = 1, D4 of the GCR register) avoids entering Fail-safe mode after watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults (Fault mode).

Figure 12. Device operating modes

6.1.4 Sleep mode

In Sleep mode, the channels and the SPI interface are turned off to minimize current consumption. Table 6. Device operating modes Sleep 0 x x All channels are OFF. Fault 1 X 1 The channels are OFF, see Fault mode.

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• V PWR (and VDD) are within the normal range, and
• wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1])
• and
• fail-safe = X and
• f a u l t = X When employed, V DD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during sleep mode.

6.1.5 Fail-safe mode

6.1.5.1 Entering Fail-safe mode

Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD out of range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR & PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions:

• V PWR is within the normal voltage range, and
• wake-up = 1, fault = 0, and
• fail-safe = 1 ((V DD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0). The last condition describes the loss of SPI communication which is detailed in the next section.

6.1.5.2 Watchdog on SPI communi cation and Fail-safe mode

When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration tWDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator.

6.1.5.3 Returning from Fail-safe to Normal mode

To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained in and regardless the values of the other bits in this register). Next, a second data word must be received within the timeout period (tWDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched.

6.1.6 Fault mode

The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode:

• Overtemperature fault, (latchable fault)
• Overcurrent fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to V PWR in OFF state (default: disabled)
• OpenLoad fault in OFF state (default: disabled)
• OpenLoad fault in ON st ate (default: disabled)
• External Clock Failure (default: enabled)
• Overvoltage fault (enabled by default)
• Undervoltage fault, (latchable fault) The Fault Status pin asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence results in a turn-off of the incurred channel, except for the following faults: openload (ON and OFF state), External Clock Failure and Output(s) shorted to V PWR. Under and overvoltage occurrences cause simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults can be found in Protection and diagnostic features.

Fault mode (Operation and operating modes) is entered when:

• V PWR (+VDD) were within the normal voltage range, and
• wake-up = 1, and
• fail-safe = X, and
• fault = 1 (see Going from Normal to Fail-safe, Fault or Sleep mode)

6.1.6.1 Resetting FAULT bits

Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register the fault bit is contained in clears it, provided failure cause disappearance was detected and the fault wasn’t latched.

6.1.6.2 Entering Fault m ode from Fail-safe mode

When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct inputs control the channels.

6.1.6.3 Returning from Faul t mode to Fail-safe mode

When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail-safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset.

6.1.7 Latchable faults

An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto- retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t latched). If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can then still be reset by reading the SPI register it is contained in. However, the fault actually gets latched if the failure cause has not disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Auto-retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be reset by reading out the associated SPI register prior to performing a delatch sequence (Fault delatching).

6.1.7.1 Fault delatching

To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure cause. Delatching resets the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). See Reset of the auto-retry counter. Delatching then actually occurs at the rising edge of the turn-on event. Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device.

• In direct-input controlled mode (DIR_dis_s = 0), the IN[x ] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies f<4.0 Hz.
• In SPI-controlled mode, the ON_bit state (D8 of the PWMR_s r eg.) must be alternated (‘toggled’). No minimum OFF state duration is required in this case. Performing a delatch sequence anytime during an ongoing auto-retry sequence (before latching) allows turning the channel on unconditionally. When a power-on event occurs (see Loss of VPWR, loss of VDD, and power-on reset (POR)), latched channels are also delatched and faults are reset.

35 NXP Semiconductors

and latched channels are not delatched until a delatching sequence has been performed (see Protection and diagnostic features).

6.1.8 Programmable PWM module

Each channel has a fully independent PWM module activated by setting PWM_en_s. It modulates an internal or external clock signal. Setting Clock_int_s = 1 (bit D6 of the OCR_s register) activates the internal clock, and setting Clock_int_s = 0 activates the external clock. Figure 13. Internal and external clock operation EMC is to use an external clock with a staggered switch on delay. Table 7. PWM duty cycle value assignment Table 8. Switch-on delay in PWM mode

6.1.8.1 External clock and internal PWM (CLOCK_int_s = 0)

single clock signal. Simultaneously setting PWM_en_1=1 and PWM_en_0=1 synchronizes the channels. clock has to be within the authorized range again.

6.1.8.2 Internal clock and internal PWM (Clock_int_s bit = 1)

about +/-30% to +/-10%. The programming procedure is initialized by sending a dedicated word to the SI-CALR register (see Table 7). value of the channel’s switching period is obtained by multiplying the internal clock period by 256. Figure 14. Internal clock calibration and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level.

6.1.8.3 Synchronization of both channels

switch on delay (see Table 8).

6.1.9 Parallel operation

There are two ways to configure the On/Off control: SPI-configured PWM control and Direct Input Control.

• SPI configured Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1 CSB SI CALR_s SI command ignored Internal clock period of channel s tCSB tCSB

37 NXP Semiconductors

register (configuration of the openload/output short-circuited diagnostics). It is recommended to disable the OFF state openload for the HS1 output (not necessary for 20XS4200B). After setting PARALLEL=1, contents of SO registers in bank 0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4 and OD5 of both FAULTR_s registers (OLON, OLOFF, OS) are always reported independently.

• Direct Input controlled Parallel mode: The IN0 and IN1 pins must be connected externally. 2- Diagnostics in Parallel mode: The diagnostics in Parallel mode operate as follows:
• Openload in OFF state and - openload in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently report failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register.
• Current sensing: See Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register.
• output shorted to battery: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in Parallel mode:
• Overcurrent: -Only the configuration of overcurrent thresholds & blanking windows of channel 0 are considered. -In case overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of OC, both OC-bits (OD0) in the FAULT registers are simultaneously set to logic 1.
• severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1.
• overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1.
• auto-retry: Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched.

6.2 Protection and diagnostic features

6.2.1 Protective functions

6.2.1.1 Overtemperature fault (Latchable fault)

The channels have individual overtemperature detection. As soon as a channel’s junction temperature rises above TSD (175 °C typ.), it is turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction temperature of both channels has dropped below the threshold: TJ<TSD. Overtemperature is detected in ON and in OFF state:

• If the channel is ON, the associated output is switched OFF, the OT bit is set, and FSB = 0.
• If the channel is OFF: FSB goes to logic [0] and remain low until the temperature of both channels is below TSD and any of the channels is turned on again. The auto-retry function (if activated) automatically turns the channel on when the junction temperature has dropped below TSD. The OT fault bit can only be reset by reading out the FAULTR register, provided that TJ<TSD and FSB = 1 again.

6.2.1.2 Overcurrent faul t (Latchable fault)

When overcurrent (OC) is detected, the channel is immediately turned Off (after tFAULT seconds). The OC-bit is set to 1 and FSB becomes low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and windows tOCM_x and tOCH (programmable by SPI bits). The steady-state overcurrent protection level I_OCL is defined by the settings of the OCL and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked and SYNC becomes 1.

6.2.1.3 Overcurrent duration counter

The load current can spend only a defined amount of time in a particular window of the overcurrent profile. If the time in the window exceeds the selected window width (tOCx) or the overcurrent threshold is crossed, the channel is turned off (OC fault), followed by auto- retry (if enabled). An internal overcurrent duration counter is employed for this function.

6.2.1.4 Overcurrent detection on resistive and inductive loads

According to the load type (resistive or inductive), one of two different overcurrent profiles should be selected. This is done by connecting a resistor with the appropriate value between the CONF[0:1] pins and GND (Table 9).

39 NXP Semiconductors

active at the end of the selected overcurrent window (duration tOCM2_L). Figure 15. Current sense blanking during overcurrent window activity Activation of the lighting profile is time driven and activation of the DC motor profile is event driven, as explained below. or a window width is exceeded. Figure 6. This window is opened anytime the output current exceeds the selected lower overcurrent threshold (IOCLx). In this case, the allowed overcurrent duration is defined by parameters tOCM1_M, tOCM2_M, tOCH1 and tOCH2.

6.2.1.5 Auto-retry after overcurrent shut off

retries (described in section Auto-retry).

6.2.1.6 Switch mode operati on and overcurrent duration

Table 9. Overcurrent profile selection

much later in switch mode than in fully-on mode, since the duration counter only counts overcurrent during on-times. Figure 16. Overcurrent shutdown in PWM mode (solid line) and Fully-on mode (dashed line)

6.2.1.7 Reset of the duration counter

is also reset automatically at each auto-retry (but not in DC motor mode). overcurrent ([hson[x]=1 for any duration). Reset then actually occurs at the first turn-off instant following that on-period. In switch mode, the duration counter is not reset by normal PWM activity unless delatching is performed.

6.2.1.8 Severe short-circuit fault (Latchable fault)

When a severe short-circuit (SC) is detected at turn-ON (wiring length LLOAD< LSHORT, see Table 4), the channel is shut off immediately. auto-retry. SC is of the latchable fault type (see Protection and diagnostic features and Fault delatching).

6.2.1.9 Overvoltage detecti on (enabled by default)

the ranges specified in Table 4.

6.2.1.10 Undervoltage fa ult (Latchable fault)

(common) UV bit is set to [1].

• If the channel’s internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned on (warning).
• If the channel’s control signal is on, the channel is turned on if a delatch or POR sequence is performed prior to the turn on request. The UV bit can then only be reset by reading out the STATR register. Auto-retry (if enabled) starts as soon as the UV condition disappears.

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6.2.1.11 Extended mode protection

detection should be disabled (by setting OV_dis = 1 in the GCR register).

• V DD < VDD(FAIL) with VPWR in the normal voltage range
• V DD and VPWR are below the VSUPPLY(POR) voltage threshold
• The corresponding SPI register is read after the disappearance of the failure cause (and delatching)

6.2.1.12 Drain/source overvoltage protection

6.2.1.13 Supply overvoltage protection

feature is not operational in cases of ground loss.

6.2.1.14 Negative output voltage protection

VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. Figure 17. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the current in the supply-voltage measurement-diode (zener) and the current injected into the MOSFET’s gate to turn it on. Figure 17. Supply and output voltage protections

6.2.1.15 Reverse voltage protection on V PWR

The device can withstand reverse supply voltages on VPWR down to -28 V. Under these conditions, the outputs are automatically turned On and the channel’s on-resistance (RDS(on)) is similar to that during positive supply voltages. No additional components are required to protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR, in case they are connected to VPWR. The VDD pin needs reverse voltage protection from an externally connected diode (Figure 23).

6.2.1.16 Load and system ground loss

In case of load ground loss, the channel’s state does not change, but the device detects an openload fault. In case of a system GND loss, the channels are turned off.

6.2.1.17 Device ground loss

In the (improbable) case the device loses all of its three ground connections (pins 14, 17, and 22), the channels’ state (ON/ OFF), depends on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device’s momentary current consumption (influenced by the SPI settings) and the state of other high side switches on the board when there are pins in common like FSB, FSOB, and SYNC. In the following description, all voltages are referenced to the system (module) GND. When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s) are tied to VPWR. Fail-safe is entered under the following conditions:

• all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k
• any device pin connected to external syst em components has a series resistors > 8.0 k (except pins Vpwr, VDD, HS[0], HS[1], and R(CSNS)>2.0 k)
• the FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means that none of the other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes logic low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH.

6.2.2 Supply voltages out of range

6.2.2.1 V DD out of range

If the external VDD supply voltage is lost (or falls outside the authorized range: VDD<VDD(FAIL)), the device enters Fail-safe mode, provided the VDD_FAIL_en bit had been set. Consequently, the contents of all SPI registers are reset. The channels are controlled by the direct inputs IN[0:1] (if VPWR is within the normal range). Since the VPWR pin supplies the circuitry of the SPI, current sense and most of the protective functions (overtemperature, overcurrent, severe short-circuit, short to VPWR, and OpenLoad detection circuitry), these faults are still detected and reported at the FSB pin. However, without VDD, the SO pin is no longer functional. The SPI registers can no longer be read and detailed fault information is unavailable. Current sensing also becomes unavailable. If VDD_FAIL_EN wasn’t set before VDD was lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current flows from the VPWR to the VDD pin.

6.2.2.2 V PWR supply voltage out of range

In case VPWR is below the undervoltage threshold VPWR(UV), it is still possible to address the device by the SPI port, provided VDD is within the normal range. It does not prevent other devices from operating when a device is part of a daisy-chain. To accomplish this, RSTB must be kept at logic [1]. When the device operates at supply voltages above the maximum supply voltage (VPWR=36 V), SPI communication is not affected (see Overvoltage detection (enabled by default)). The internal pull-up and pull-down current sources on the SPI pins are not operational. Executing a Power-on-Reset (POR) sequence is recommended when VPWR re-enters its authorized range. No current flows from the VDD to the VPWR pin.

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6.2.2.3 Loss of V PWR, loss of VDD, and power-on reset (POR)

• V PWR > VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after)
• V DD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently).

Figure 18. State machine: fault occurrence and auto-retry

6.2.3 Auto-retry

Retry[x] = OC[x] or SC[x] or OT[x] or UV. If Auto-retry is disabled, latchable faults are immediately latched upon their occurrence (see Protection and diagnostic features).

6.2.3.1 Auto-retry configuration

and the retry condition applies (Retry[x]=1, see Auto-retry). bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection.

6.2.3.2 Amount of auto-retries

remains powered. The channel never latches off. diagnostic features and Fault delatching). The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4).

6.2.3.3 Reset of the auto-retry counter

• Fail-safe is entered ( Fail-safe mode)
• Sleep mode is left ( Sleep mode)
• POR occurs ( Supply voltages out of range)
• the retry function is set to unlimit ed (bit Retry-unlimited_s = 1 (D1 = 1))
• the retry function is disabled (retry_s bit= D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for CONF = 0). If the channel is latched at the moment the auto-retry counter was reset (case 4), the channel is delatched, and turned on after one retry period (if retry was enabled).

6.2.3.4 Auto-retry a nd overcurrent duration

threshold profile, as described in the section on overcurrent protection (See Overcurrent fault (Latchable fault)). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). counter). Figure 18 gives a description of the retry state machine with the various transitions between operating modes. Table 10. Auto-retry activation for lamps (CONF=0) and DC motors (CONF=1)

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6.2.4 Diagnostic features

Diagnostic functions openload-in-ON state (OLON), openload-in-OFF state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 5 for PWM mode, but the precise values also depend on the way the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the openload-in-ON state detection. As an example, in direct input (DIR_dis_s = 0), Low-Current mode (CSR1), OLON, OLOFF and OS detection are performed for duty cycle values up to: RPWM_400_h = 85% (instead of 90%) when openload in ON state detection is enabled (OLON_dis=0). Occurrence of an OLON, OLOFF or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any of these diagnostic functions can be disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or OS_dis_s=1 (bits D8...D6 of the CONFR reg.). The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%).

6.2.4.1 Output shorted-to-V PWR fault

The device detects short-circuits between the output and VPWR. The detection is performed during the OFF state. The output-shorted- to-VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit is not cleared until the FAULTR register is read. The function may be disabled by setting OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features. This type of event shall be limited to 1000 min. during the vehicle lifetime. In case of permanent output shorted to the battery condition, it is needed to turn-on the corresponding channel.

6.2.4.2 Openload detection in OFF state

Openload-in-OFF state detection (OL_OFF) is performed continuously during each OFF state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the openload fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features.

6.2.4.3 Openload detection in ON state (OL_ON)

Openload-in-ON state detection (OLON) is performed continuously during the ON state for CSR0 over the ranges specified in section Diagnostic features. An openload-in-ON state fault is detected when the load current is lower than the openload current threshold IOLD(ON). This happens at IOLD(ON) = 150 mA (typ.) for high current sense mode (CSR0), and at 7.0 mA (typ.) for low current mode. FSB is asserted low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), openload-in-ON state detection is done continuously during the On state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the OFF state, even if the fault hasn't disappeared. The OLON-bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has disappeared. In low current mode (CSR1), OL_ON is done periodically instead of continuously and only operates when fast slew rate is selected. When the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used (case 2), the period is that of the input signal. The detection instants in both cases are given by the following: 1. In internal PWM (int./ext. clock), low current mode (CSR1), OpenLoad in ON state detection is not performed each switching period, but at a fixed frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%. OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event (before OS and OL_OFF). 2. In direct input, low current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel’s direct input must be disabled by setting Dir_dis_s=1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read after occurrence of an OL_ON detection event without fault presence.

6.2.4.4 Openload detection in discontinuous conduction mode

If small inductive loads (solenoids/DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired openload in ON state errors may then be detected, as the inductor current needs some time to rise above the openload detection threshold after turn-on. This problem can be solved by increasing the switching frequency or by disabling the function and activating openload in OFF state detection instead. When small DC motors are driven in discontinuous conduction mode, undesired openload in OFF state detection may also occur when the load current reaches 0.0 A during the OFF state. This problem can be solved by increasing the switching frequency or by enabling openload in OFF state detection only during a limited time, preferably directly after turn-off (see Diagnostic features). The signal on the SYNC pin can be used to identify the turn-off instant.

6.2.5 Current and temperature sensing

The scaled values of either of the output currents or the temperature of the device’s GND pin (#14) can be made available at the CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits (see Table 23) in the General Configuration Register (GCR) must be set to the appropriate values. When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high.

6.2.5.1 Instantaneous and sampled current sensing

The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and track & hold mode (see Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output current monitoring (CSNS)) and is therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In track & hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1.

6.2.5.2 Current sense ratio selection

The load current is mirrored through the CSNS pin with a sense ratio (Figure 19) selected by the CSNS_ratio bit in the OCR register. To achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, must be selected. In that case, the overcurrent threshold levels are decreased. The best accuracy that can be obtained for either ratio is shown in Figure 20. The amount of current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 Ω < R(CSNS) <10 kΩ, 1.0 kΩ typical), in order to generate a voltage output. A small low-pass filter can be used for filtering out switching transients (Figure 23). Current sensing operates for load currents up to the lower overcurrent threshold (OCLx A).

6.2.5.3 Synchronous current sensing mode

For activation of synchronous mode, T_H_en must be set to 0 (default). After turn-on, the CSNS output current accurately reflects the value of the channel’s load current after the required settling time. From this moment on (CSNS valid), the SYNC pin goes low and remains low until a switch off signal (internal/external) is received. This allows synchronization of the device’s current sensing feature with an external process running on a separate device (see Current sense synchronization (SYNC)). After turn-off, the load current does not flow through the switch, and the load current cannot be monitored.

6.2.5.4 Track & Hold current sensing mode

In Track & Hold mode (T&H) (T_H_en = 1), conversely from synchronous mode, the CSNS output current is available even after having switched off the load. This feature is useful when the device operates autonomously (internal clock/PWM), since it allows current monitoring without any synchronization of the device. An external sample and hold (S/H) capacitor is not required. After turn on, the CSNS output current reflects the channel’s load current with the specified accuracy after occurrence of the negative edge on the SYNC pin, as in synchronous mode (see Current sense synchronization (SYNC)). However, at the switch-off instant, the last observed CSNS current is sampled and its value saved, thanks to an internal S/H capacitor. The SYNC pin goes high (SYNC = 1). If the channel on which Track & Hold current sensing is performed is changed to another, the internal S/H hold capacitor is first emptied and then charged again to allow current monitoring of the other channel. Consequently, T&H current monitoring of a channel is lost when this channel is in the OFF state at the moment the current is monitored on the other channel. Track & Hold mode should not be used for frequencies below 60 Hz. When Track and Hold is used to sense the temperature and then to sense a current, the Track & Hold mode has to be reset by a turn off, then turn on before sensing a new current.

47 NXP Semiconductors

Figure 19. Current sensing ratio versus output current

6.2.5.5 Current sense errors

compensated current sensing value is illustrated in the next sections.

6.2.5.6 Activation and use of offset compensation

I_LOAD_ERR_SYS (see ESR0_ERR).

6.2.5.7 Current sense error model

nominal values, specified in ESR0_ERR.

6.2.5.8 Offset compensation in Track & Hold mode

have been turned on at least once prior to sensing the output current with an opposite value of the OFP bit.

6.2.5.9 System requirements for current monitoring

that is used to read the current sense voltage V(csns) must have sufficient resolution to avoid introducing additional errors.

6.2.5.10 Accuracy with and without offset compensation

accuracy with offset compensation and dotted lines without offset compensation). Figure 20. Current sense accuracy versus output current as a function of the switch-off time is displayed, for CSR0 and CSR1). Track & Hold mode shouldn’t be used below f= 60 Hz.

49 NXP Semiconductors

Figure 21. Track and Hold current sense accuracy

6.2.5.11 Temperature prewarning detection

moment that temperature T °C < TOTWAR.

6.2.5.12 Switching state monitoring

determining the channel’s switching state).

6.2.6 EMC Performances

up to 200 V/m and Bulk Current Injection (BCI) up to 200 mA per ISO11452.

6.3 Logic commands and SPI registers

6.3.1 SPI protocol description

and SPI pins (Table 3) aren’t exceeded. Unused SPI pins must be tied to GND, eventually by resistors (see Device ground loss).

Figure 22. 16-bit SPI interface timing diagram

6.3.2 Serial input communication protocol

1. Messages with a length different from a multiple of 16 or with a parity error is ignored. The device has thirteen input registers for device

assignment. Bit names with extension “_s” refer to functions that have been implemented independently for each of both channels.

6.3.3 Serial port operation

contents. This allows daisy chaining and data integrity verification.

6.3.3.1 Daisy chain operation

addressed device, it can be executed by setting CSB=1.

1. RST must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

Notes 1. RSTB must be in a logic [1] state during data transfer.

1. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
2. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

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Table 11. SI message bit assignment Table 12. Serial input register addresses and function assignment

10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 PWM_en_0 PARALLEL T_H_en WD_dis V DD_FAIL_en CSNS1_en CSNS0_en OV_dis

contents

after reset* 0 X 0 XXX0 0 0 0 * * 0 0 0 0 0 0 *=R S T B=0 o r VDD(FAIL) after VDD = 5.0 V or POR ** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before X = register address, P = parity bit Notes 48. Bit D4 of RETRY_s Serial Input register MC20XS4200FK = 0 MC20XS4200BFK and MC20XS4200DFK,MC20XS4200BAFK and MC20XS4200BDFK=CONF_SPI_s Setting bit D4 to 0 (CONF_SPI_s=0) will configure the overcurrent profile as the CONF pin. Setting bit D4 to 1 (CONF_SPI_s=1) will configure the overcurrent profile as the opposite of CONF pin. After device reset, the overcurrent profile is defined by the CONF input pin. The SPI-SO CONF bit reporting shall combine external hardware configuration and SPI setting.

6.3.4 SI register addressing

The address in the title of the following sections (A0xxx) refer to bits D[13:10] of the SPI word required to address the associated SI register. Bit A0 = D13 selects between registers of bank 0 and bank 1 (Table 14). The function assignment of register bits D[8:0] is described in the associated section. The “_s” behind a register name indicates that the variable applies to the register contents of both banks. Table 13. Serial output register bit assignment

0 NM OV UV POR R_FUL

0 NM OTW 0 0 OLON_

0 NM ON_s PWM

0 NM OS_d

0 NM HOC

0 NM OFP R3 R2 R1 R0 Auto_period1

0 NM CON

failure* A A A A 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 *=R S T B=0 o r VDD(FAIL) after VDD = 5.0 V, or POR = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs provided VDD = 5.0 V and VDD_Fail_en = 1 before * = except bit D7 (POR) of the STATR register that is saved when VDD(FAIL) occurs after VDD = 5.0 V and VDD_Fail_en = 1 (fail-safe mode) x = register address, PF = parity Fault Notes 49. DIAGR Serial Output register bits D5 and D6 for produc t identification will report: MC20XS4200FK and MC20XS4200BFK and MC20XS4200DFK:01, MC20XS4200BAFK and MC20XS4200BDFK:00 Table 14. Value of bit A0 required for addressing register Banks 0 or 1

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6.3.5 Address A 0000—Status register (STATR_s)

PWMR_s, CONFR_s, OCR_s, RETRY_s, GCR, and DIAGR (Table 13).

6.3.6 Address A 0001— PWM control register (PWMR_s )

as shown in Table 7.To start the PWM function at a known point in time, the PWM_en_s bit (both in the GCR register) must be set to 1.

6.3.7 Address A 0010—Channel configurati on register (CONFR_s)

value [0] enables the feature. enables this feature (Table 15). that case, the channel state is determined by the settings of the internal PWM functions. slew rate. Rising and falling edge slew rates are identical.

6.3.8 Address A 0100— Overcurrent protection configuration register (OCR_s)

Table 15. Selection of openload detection features Table 16. Slew rate selection

applicable overcurrent protection profile (see I_OCH1_0). windows are active, current sensing is not available. causes the external clock to be divided by 512. When PR_s = 0, the divider is 256. range. The default value [0] activates the “high-current” sensing ratio CSR0 (Table 17). configuration as shown in Table 18. (CONF[x]=0: bulb, CONF[x]=1: DC motor). first of these windows is either tOCH1 or tOCH2. The width of the second window is either tOCM1_L or tOCM2_L (see Table 18). case, the maximum overcurrent duration is selected among four values: tOCM1_M, tOCM2_M, tOCH1 and tOCH2. highest value, and [1] to the lowest value (Table 19). lowest value (Table 20). In DC motor mode, there is no middle overcurrent threshold and the value of this bit has no influence. Table 17. Current sense ratio selection

0 CRS0 (default)

1 CRS1

Table 18. Dynamic overcurrent threshold activation times for bulb and DC motor profiles Table 19. OCH upper current threshold selection

0 I_OCH1_s (default)

1 I_OCH2_s

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Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest overcurrent threshold, as shown in Table 21.

6.3.9 Address A 0101— Auto-retry register (RETRYR_s)

current (pin CSNS). Setting bit D8 to 0 results in the offset current being subtracted from the sensed current. Setting D3 and D2 (Table 22) to the appropriate values allows selection of the value of the auto-retry period among four predefined values. neither resets after delatching, nor when the fault disappears. Setting bit D0 (retry_s) enables or disable auto-retry, accordingly to setting of the CONF pin. For CONF[x] = 0 (Lighting profile configured), setting retry_s = 1 disables auto-retry. The default value [0] enables it. For CONF[x] = 1 (DC motor), setting retry_s = 1 enables auto-retry. The default value [0] disables it.

6.3.10 Address 0110—global co nfiguration register (GCR)

The GCR register is used to activate various functions and diagnostic functions. operation should be followed. information of bank 0 (A0 = 0) is available in this setting (see Parallel operation). Table 20. OCM current threshold selection

0 I_OCM1_s (default)

1 I_OCM2_s

Table 21. OCL current threshold selection Table 22. Auto-retry period

is kept available after turn-off. Setting bit D4 (WD_dis = 1) disables the SPI watchdog function. A logic [0] enables the SPI watchdog. selected (bit D8 of the OCR register, HOCR = 0), the device’s CSNS pin only outputs scaled values of a single channel’s load current. Setting bit D0 (OV_dis = 1 of the GCR reg.) disables overvoltage protection. Setting this bit to [0] (default), enables it.

6.3.11 Address A 0111—Calibration register (CALR_s)

specific calibration procedure. See Internal clock and internal PWM (Clock_int_s bit = 1).

6.3.12 SO register addressing

diagnostics status (Table 13). These registers are FAULTR_s, PWMR_s, CONFR_s, OCR_s, and RETRYR_s. determines which register bank is addressed (bank 0 or 1). Data is made available the next cycle after register addressing. the previous SPI cycle was invalid. In this case, the device outputs the contents of the last successfully addressed SO register.

6.3.13 Serial output register assignment

The output register shifted out through the SO pin is previously addressed by bits D13, D2, D1, and D0 of the STATR_s SI register. STATR_s required to address it.

• Bit OD15 (MSB) reports the state of the watchdog bit from the previously clocked-in SPI message.
• Bit OD14 (PF, active 1) reports an eventual parity e rror on the previously transferred SI register contents.
• Bits OD13:OD10 echo the state of bits D13, D2, D1, and D0 (SOA3:SOA0) of the previously received SI word.
• Bit OD9: Normal mode (NM) reports t he device state. In Normal mode, NM = 1.
• Bits OD8:OD0 are the contents of the selected SO register (addressed by bit D13 and bits D2:D0 of the previous SI STATR register).

Table 23. Current sense pin functionality selection

57 NXP Semiconductors

6.3.14 Previous address SOA 3:SOA0 = 0000 (STATR)

When bits SOA3…SOA0 of the previously re ceived SI STATR_s register = 0000, the SO STATR register is addressed. Bits OD8:OD0 contain the relevant channel information: Faults, channel state, and supply voltage errors.

• Bits OD8:OD6 report failures common to both channels
• Bit OD8 = OV = 1: overvoltage fault
• Bit OD7 = UV = 1: undervoltage fault
• Bit OD6 = POR = 1: power-on reset (POR) has occurred Power-ON-Reset occurs when V PWR<VSUPPLY(POR). The OV, UV, and POR bits can be reset by a reading the STATR register. Bits OD5:OD4 (RFULL) of the STATR register are set to logic [1] when the auto-retry counter of the corresponding channel is full. These bits are automatically cleared by resetting the corresponding auto-retry counter (see Reset of the auto-retry counter) Bits OD3 (FAULT1) and OD2 (FAULT0) are set to logic [1] when channel-specific (non-generic) faults are detected: FAULTs = OC_s + SC_s + OT_s + OS_s + OLOFF_s + OLON_s. The FAULTs bit can be reset by reading out the common STATR register or the individual FAULTR_s register (provided the fault has disappeared). Bits OD1:OD0 (OUT1 and OUT0) report the channel’s switching state (ON/OFF) in real time.

6.3.14.1 Previous address SOA 3:SOA0 =A 0001 (FAULTR_s)

Bit OD8 of both Fault registers (FAULTR_s) is set simultaneously when the overtemperature prewarning (OTW) condition occurs, but the channels are not switched off (temperature of the common GND pin (#14)> TOTWAR). Reading either FAULT register clears both OTW bits. Bits OD5:OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0 (Table 14).

• bit OD0 = OC_s: overcurrent fault on channel s,
• bit OD1 = SC_s: severe short-circuit on channel s,
• bit OD3 = OS_s: output shorted to V PWR on channel s,
• bit OD4 = OLOFF_s: OpenLoad in OFF state on channel s,
• bit OD5 = OLON_s: OpenLoad in ON state on channel s. (The thre shold value above which this fault is triggered depends on the selected current sense ratio; for CSR0 @ 150 mA typ. and for CSR1 @ 7.0 mA typ.). The Fault Status pin ( FSB) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be delatched by the procedure described in Fault delatching. The FAULTR_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults have been delatched.

6.3.15 Previous address SOA 3:SOA0 =A 0010 (PWMR_s)

The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.16 Previous address SOA 3:SOA0 =A 0011 (CONFR_s)

The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.17 Previous address SOA 3:SOA0 =A 0100 (OCR_s)

The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.18 Previous address SOA 3:SOA0 =A 0101 (RETRYR_s)

The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7:OD4 contain the real time value of the auto-retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur.

6.3.19 Previous address SOA 3:SOA0 = 0110 (GCR)

The device outputs the contents of the general configuration register (GCR) common to both channels.

6.3.20 Previous address SOA 3:SOA0 = 0111 (DIAGR_s)

Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels’ configuration bits (0 = bulb, 1 = DC motor). For 20XS4200FK, 20XS4200BFK, and 20XS4200DFK

• Bits OD6:OD5 contain the product identification (I D) number, equal to 01 for the present dual 20 mΩ product. For 20XS4200BAFK and 20XS4200BDFK
• Bits OD6:OD5 contain the product identification (I D) number, equal to 00 for the present dual 20 mΩ product. Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0. Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0). Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel’s internal clock period.

59 NXP Semiconductors

7 Typical applications

control in case Fail-safe mode is activated (FSOB goes low). This circuit allows keeping full control of both channels in case of SPI failure. Figure 23. Typical application with two different load types

Figure 24. Two channels in parallel/recommended external current sense circuit

61 NXP Semiconductors

8 Packaging

8.1 Soldering information

The FK package is a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for Printed Circuit Board design and assembly.

8.2 Package mechanical dimensions

perform a keyword search for the drawing’s document number. Table 24. Packaging information

63 NXP Semiconductors

65 NXP Semiconductors

67 NXP Semiconductors

69 NXP Semiconductors

9 Revision history

Revision Date Description of Changes 1.0 5/2012 • Initial release 2.0 6/2012 • Updated values in Table 4, Static electrical characteristics 3.0 5/2013

• Grammatical accuracy and form consist ency changes made. No changes to content.
• Revised back page. Updated document properti es. Added SMARTMOS sentence to first paragraph. 4.0 8/2013
• Added a table
• Introduction of parameters related to 20XS4200 device (Table 1).
• Removed R DSON values at 1.0 A.
• Rectification of the inversion between ∆tDLY values at slow and medium slew rate.
• Added the 20XS4200 to the Systematic offset error (see Current sense errors) parameter. 5.0 11/2013
• Removed EK package information
• Removed all references to the SOIC package
• Added 20XS4200BAFK to the ordering information
• Introduction of parameters related to 20XS4200BAFK device
• Removed Ecl_rep energy values
• Update Ecl_sing value 6.0 5/2018
• Updated as per CIN 201805019I
• Changed steady state current value from 3.0 to 4.4 A listed under features on page 1
• Updated I HS[0:1] value in Table 3 (changed 3.0 to 4.4)
• Added clarification for diagnostic range to Table 5
• Updated load dump duration (changed 500 ms to 350 ms) and changed V PWR from 14 V to 28 V in Table 3
• Updated Track & Hold current sensing mode
• Typo correction in Table 4 (corrected current limit range for ESR0_ERR) 7.0 10/2022
• Updated as per CIN 202209028I
• Added Orderable part numbers in Table 1: MC20XS4200DFK and MC20XS4200BDFK
• Added footnote to Table 1
• Updated part numbers under VPWR supply voltage range and Voltage (continuous, max. allowable) on output pins (HS [0:1]) in Table 3: Second bullet under each heading changed from 20XS4200BFK, and 20XS4200BAFK to 20XS4200BFK and 20XS4200DFK, 20XS4200BAFK and 20XS4200BDFK
• Updated Table 4 to include new part numbers
• Updated Table 5 to include new part numbers
• Updated footnote in Table 12
• Updated footnote in Table 13
• Updated part numbers in Previous address SOA3:SOA0 = 0111 (DIAGR_s)
• Updated images in Package mechanical dimensions

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to anyproducts herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP Semiconductors B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2022. Document Number: MC20XS4200 Rev. 7.0