1T362A SONY

Document overview

  • Manufacturer or author: Provided By digicamel.com
  • PDF pages: 4

Technical content

Features

  • Super miniature package
  • Low series resistance 0.65 Ω Max. (f=470 MHz)
  • Large capacitance ratio 6.5 Typ. (C 2/C25)
  • Small leakage current 10 nA Max. (VR =28 V)
  • Capacitance deviation within 2 %

Applications

Electronic tuning of TV and CATV Structure Silicon epitaxial planar type diode Silicon Variable Capacitance Diode M-235 1T362A Electrical Characteristics (Ta=25 °C) Item Reverse current Diode capacitance Capacitance ratio Series resistance Capacitance deviation in a matching group Symbol I R C 2 C 25 C 2/C25 rs Conditions VR =28 V VR =2 V, f=1 MHz VR =25 V, f=1 MHz f=1 MHz C D =14 pF, f=470 MHz VR =2 to 25 V, f=1 MHz Min. Typ. Max. Unit 10 nA 14.01 15.00 16.33 pF 2.10 2.27 2.39 pF 6.5 0.57 0.65 Ω ∆C:The capacitance deviation of continuous 20 pcs of 1T362A is ranged within 2% in any place of the taping package.

— 2— 1T362A Product Name and Package Specification for the 1T362A. According to the classification number for the combination of capacitance deviations (hereafter ∆C), assembly method and automatic mounting equipment section, the following product names are assigned. Note1) In taping packaging of products groups according to the ∆C classification, products must be divided according to the group. If taping is performed without grouping into categories, products from two different groups may be mounted on the same tuner, so that ∆C cannot be assured during tuning, making tuning defective. A: Panasert method; Sections are divided by four blank spaces on the carrier tape. B: Sanyo method; Black tape is affixed to one blank space on the carrier tape to mark sections. Note 2)∆C kit number When taping each group, taping is performed in kit number multiples. 01; Incomplete kit (∆C not guaranteed) 04; 4 kits 20; 20 kits Recommended kit number; 4 and 20 Other)Minimum number of kits per group is 240 (60 or more at the beginning of the carrier tape). Up to nine sections on one reel. Note 3)“MAP” is the method where the neighboring chips are assembled continuously in order to enhance the concentration of the capacitance deviation in a matching group. 1T362ABase m odel 04 T8 A A1T362AD erived m odel 20M A T8 N ote 1 : Package specification as ordered by custom er ∗ Taping direction ∗ T8 only to consolidate specifications Special selection sym bol N ote 2 : ∆C kit num ber N ote 3 : Assem bly m ethod M =M AP

— 3— 1T362A D iode capacitance vs. R everse voltage D iode capacitance (pF) R everse voltage (V) Ta=25°C f=1M H z 1 2 5 10 20 D iode capacitance vs. Am bient tem perature 1.03 1.02 1.01 1.00 0.99 0.98 Ta-Am bient tem perature (°C ) VR =1V f=1M H z VR =25V VR =2V VR =10V –20 0 20 40 60 80 100 R everse voltage vs. Am bient tem perature VR -R everse voltage (V) Ta-Am bient tem perature (°C ) IR =10µA –20 0 20 40 60 80 D iode capacitanceC (Ta) C (25°C ) R everse current vs. Am bient tem perature 1000 100 Ta-Am bient tem perature (°C ) VR =28V –20 0 20 40 60 80 IR -R everse current (pA) Therm al coefficient of diode capacitance 1000 100 Therm al coefficient (ppm /°C ) VR -R everse voltage (V) 10 30 f=1M H z R everse current vs. R everse voltage 100 IR -R everse current (pA) VR -R everse voltage (V) 10 100 Ta=60°C Ta=25°C

JED EC C O D E PAC KAG E W EIG H T /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesM -235 ∗1.25 + 0.2 – 0.1 0.3 + 0.1 – 0.05 ∗1.7 ± 0.1 2.5 ± 0.2 0.3 + 0.1 – 0.05 ∗0.9 ± 0.1 0.2 0 ± 0.05 0° to 10° 0.11 + 0.1 – 0.06 M -235 0.1g N O TE: D im ension “∗” does not include m old protrusion. Package Outline Unit : mm 1T362A — 4— Marking 2C ATH O D E M AR K B Notes 1) B:Lot No.(Year and Month of manufacture) Year;Last one digit Month;A,B,C(for Oct. to Dec.) 1 to 9(for Jan.to Sept.)