1EDN7136G

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Document overview

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Technical content

. ™ EiceDRIVER 1EDN71x6G

200 V high-side TDI gate driver IC for GaN SG HEMTs and MOSFETs

F eatures Q rors © tisiozent + Optimized for driving GaN SG HEMTs and Si MOSFETs + Fully differential logic input circuitry to avoid false triggering in low-side or high-side operation y « High common-mode input voltage range (CMR) up to + 200 V for high side operation + — High immunity to common-mode voltage transitions (100 V/ns) for robust operation during fast switching + Compatible with 3.3 V or 5 V input logic + — Four driving strength variants to optimize switching speed Ye without external gate resistors - up to 2 A source/sink current Jo. vor} capability T flees oursre| qT WW + Active bootstrap clamp to avoid bootstrap capacitor Sort vonmh, | overcharging during dead-time Oo—ww ae - ot + Active Miller clamp with 5 A sink capability to avoid induced Ow a vss VOL} turn-on Ct = + Adjustable charge pump for negative turn-off supply voltage Ww * Qualified for industrial applications according to the relevant tests of JEDEC47/20/22

Description

The 1EDN71X6G is a single-channel gate-driver IC optimized for driving Infineon CoolGaN™ Schottky Gate HEMTs, as well as other GaN SG HEMTs and Si MOSFETs. This gate driver includes several key features that enable a high-performance system design with fast-switching transistors, including Truly Differential Input (TDI), four driving strength options, active Miller clamp, bootstrap voltage clamp, and adjustable charge pump. Potential applications + Single channel: + Half-bridge (2 x 1EDN71x6G): - Synchronous rectifier - DC-DC converter - Class-E resonant wireless power - BLDC/PMSM motor drive - Class-D audio amplifier - Class-D resonant wireless power Product portfolio Part number Peak source/ sink current Input pulse blanking time Package 1EDN7146G 0.5A 80 ns PG-VSON-10 Datasheet Please read the Important Notice and Warnings at the end of this document Rev. 2.1 www.infineon.com 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Datasheet 2 Rev. 2.1 2021-10-12

EiceDRIVER’ 1EDN71x6G Infineon

1 Pin configuration and description

| 1otot — te!) tuo a 7 | -- CF- 1) “ \\ (10 | VOFF l | cre [ 2) | ! (79 | ouTsrc l | vOFF_ADJ | 3.) | VSS ; (8 | OUT_SNK = =- \\ (11) Lt A i | -- = \\ _ a | | -> t--4 of po orc7 J total Figure 1 Pin configuration 1EDN71X6G in PG-VSON-10 package, top view Table 1 Pin definitions and functions 1 Flying capacitor charge pump negative connection. 2 Flying capacitor charge pump positive connection.

3 VOFF_ADJ Connect a resistance between this pin and VSS to select the negative rail

voltage. 4 IN+ Connected to PWM output of controller via 47 kQ or 75 kQ resistor. 5 IN- Connected to controller ground via 47 kQ or 75 kO resistor. 6 VDD Gate drive supply.

7 BST Bootstrap diode anode connection point, when used as a low-side driver

in a half-bridge configuration. 8 OUT_SNK Low-impedance gate pull-down to Vo,r (including active Miller clamp). 9 OUT_SRC Low-impedance gate pull-up to Vpp. 10 VOFF Negative rail voltage for the turn-off. 11 Return path for VDD and thermal dissipation pad. Datasheet 3 Rev. 2.1 2021-10-12

EiceDRIVER’ 1EDN71x6G Infineon

2 Product information

2.1 Functional description

The 1EDN71X6G is a single-channel gate-driver IC optimized for driving Infineon CoolGaN™ SG HEMTs, as well as other GaN SG HEMTs and Si MOSFETs. Thanks to the truly differential input feature, the gate driver output state is exclusively controlled by the voltage difference between the two inputs, independent of the driver’s reference (ground) potential as long as the common-mode voltage is below 150 V (static) and 200 V (dynamic). This eliminates the risk of false triggering due to ground bounce in low-side applications, while also allowing 1EDN71x6G to address even high-side applications. The product is equipped with several key features especially designed to enhance the performance of GaN SG HEMTs: + four driving strength variants to optimize switching speed without external gate resistors * active bootstrap clamping to avoid overcharging the bootstrap capacitor during dead-time + anactive Miller clamp with exceptionally strong pull-down to avoid induced turn-on + and an optional charge pump to provide an adjustable negative turn-off supply, for additional induced turn-on immunity when needed. Vop i . / Tl | I ons in a T] OUT_SNK Lf | VOFF_ADJ LI PT IN+ BsT[ | L . IN- eg VDD[_ | Figure 2 Typical circuit for low-side single-channel application using 1EDN71X6G to drive a GaN SG HEMT

2.2 Truly differential input (TDI)

The TDI feature offers common-mode voltage rejection up to 150 V for static voltage and 200 V for dynamic voltage transients, enabling both low-side and high-side gate driving without the need for a digital isolator at the input. The dynamic voltage rating is relevant for any voltage spikes shorter than the specified blanking time (that is, minimum pulse width). When used as a low-side gate driver, the TDI greatly enhances ground bounce immunity during fast GaN switching transitions. Datasheet 4 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon At the positive and negative signal inputs two symmetrical resistor dividers are used to scale down and compensate common mode bouncing voltages. A fully differential amplifier stage provides high common mode rejection and high sensitivity to differential input signals. The amplified differential output voltage is finally evaluated by the subsequent differential Schmitt-Trigger circuit. At the IN+ and IN- pins, two external resistors Rin; and Rin? are used to scale down common mode voltages of up to + 150 V to a level which can be processed by low voltage CMOS circuitry. These input resistors serve the function of "blocking" the high common-mode voltage, so that the IN+ and IN- pins of the driver are not exposed to this high voltage. As such, the selection of these resistors is critical to the proper operation of the TDI circuit. | > 7 2 | In+[_] itt. Am Control it q + LPF > teal d driver {| OUT_sRC Adj. Charge {_ ] OUT_sNK Pump pre- ois eee ai CF- CF+ VOFF_ADJ VOFF Figure 3 Functional block diagram The resistance values for Rin, and Rin2 Must be selected based on the logic level of the input signals. For a 3.3 V logic, both external input resistors must be 47 kQ. For a 5 V logic, they must be 75 kQ. Furthermore, Riny and Rin2 must be very closely matched. A tolerance of + 0.1 % is required to maintain control over the full common mode swing. Resistors with wider tolerance limit the common-mode range of the TDI driving circuit. Any asymmetries in these resistors may cause a a common-mode voltage to be interpreted as an input signal, including stray impedances in the PCB layout. Recommendations for a PCB layout are given later in this datasheet. To compensate for small asymmetries in the TDI circuit, low pass filters are used to further enhance the high frequency common mode rejection. Two different input filter options are available to accommodate different designs, with a total blanking time of 20 ns for 1EDN7116G, 40 ns for 1EDN7126G, 60 ns for 1EDN7136G, and 80 ns for LEDN7146G.

2.3 Undervoltage lockout

The undervoltage lockout (UVLO) functions ensure that the output can be switched to its high level only if the supply voltage exceeds the UVLO threshold voltages. In the 1EDN71x6G, two UVLOs are implemented: one for the VDD pin, and one for the adjustable charge pump voltage. The UVLO for VDD ensures that the transistors are not switched on if the driving voltage is too low, thereby avoiding excessive power dissipation due to linear-mode operation. The charge pump UVLO ensures the desired negative voltage is available for VOFF before any switching activity starts. Both UVLOs must be inactive to allow the propagation of the input control signals (IN+, IN-) to the output. The VDD UVLO level is set to a typical value of 3.85 V, with a maximum of 4.0 V. The maximum value of the rising edge is the value that ensures all the device among the production is turned on during start up. The designer Datasheet 5 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon must provide a voltage higher than 4.0 V to turn on all the devices in the production of their equipment within the specified temperature range. On the opposite side, the minimum voltage necessary to switch off all the devices is the minimum of the falling edge, which is 3.6 V. Therefore, a voltage lower than 3.6 V ensures that the driver does not start switching. Once the driver has exceeded the UVLO, the supply voltage must remain above the maximum falling edge level of 3.9 V to avoid a UVLO shutdown. The hysteresis is the voltage gap between rising edge and falling edge, which ensures some margin on noise effects such as false turn off. The charge pump also have a UVLO function that is only active at the power-up of the 1EDN71x6G. If the charge pump is disabled, then this UVLO can be ignored. If it is enabled, then the driver does not transfer signals to the output until the charge pump UVLO threshold has been exceeded. After that time, the UVLO latches and does not trigger a shutdown of the driver, even if the charge pump voltage drops below its UVLO threshold later. The UVLO threshold level is a function of the voltage selected for the adjustable charge pump. The output states depend on the inputs configuration and the status of the two UVLOs. The truth table of the driver is represented below. Table 2 Input logic truth table cP Differential UVLO VDD UVLO VOFF OUT_SNK OUT_SRC BST input ENABLED xX ACTIVE ACTIVE HiZ HiZ HiZ ENABLED xX ACTIVE INACTIVE HiZ HiZ HiZ ENABLED xX INACTIVE ACTIVE L HiZ L ENABLED L INACTIVE INACTIVE L HiZ L ENABLED H INACTIVE INACTIVE HiZ H H DISABLED xX ACTIVE x HiZ HiZ HiZ DISABLED L INACTIVE x L HiZ L DISABLED H INACTIVE x HiZ H H Where: + UVLO active means Vpp < UVLOVDDL + UVLO inactive means Vpp > UVLOVDDH + Differential input = L means (Vjy. - Vin.) < input logic threshold + Differential input = H means (Vjy4- Vin.) > input logic threshold

2.4 Minimum input pulse

The minimum input pulse is the shortest duration pulse at the differential input that will generate an output pulse. Pulses with durations shorter than the minimum pulse are neglected and therefore will not generate any output pulse. Once the input pulse has sufficient duration to be propagated, the duration of the output pulse is equal to the duration of the input pulse, having therefore a linear transfer function between input and output. The minimum input pulse is specified here as "shortest input pulse transferred to the output." The maximum value for this parameter is the pulse width at which all the drivers in production will provide an output signal. In other words, the designer must provide a pulse width longer than the maximum specified value to ensure an output pulse for every driver of their equipment. Likewise, any pulses shorter than the minimum specified value will be ignored by all drivers in production. This minimum specification can be treated as the guaranteed blanking time for de-glitching, which helps to prevent spurious switching during common-mode transient events.

2.5 Driver outputs

The output stage of the driver has a peak source and sink current as defined for the given product variant, which corresponds to an equivalent resistance of the pull-up and pull-down transistor. The designer can Datasheet 6 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon optimize the switching speed of the driven transistor by selecting one of the four product variants, without the need for external gate resistors. If external gate resistors are used, it is highly recommended to avoid placing a resistor in the output sinking path, as this limits the effectiveness of the active Miller clamp described in the next section. Source and sink outputs are actively held low with a clamp in case of floating inputs or during startup or power down. Under any situation, outputs are held under defined conditions to avoid unstable or unknown behavior of the driven transistor.

2.6 Active Miller clamp

The sink output of the gate driver has an active Miller clamp feature to provide high immunity to spurious turn-on events. During a turn-off transition, the peak sinking current and equivalent pull-down resistance is defined according to the product variant. However, once the driver detects that the gate voltage (at the sink output) has fallen below 0.4 V, the active Miller clamp is engaged within 3 ns, increasing the strength of the Sink output significantly. With the clamp engaged, all four product variants can sink up to 5 A, with an equivalent pull-down resistance of 0.3 9. This feature allows the designer to optimize the turn-off speed without sacrificing the driver's "keep-off" strength. If an external gate resistor is placed at the sink output, the effectiveness of the active Miller clamp is reduced.

2.7 Adjustable negative charge pump

GaN HEMTs are more susceptible to spurious turn-on events, owing to their low threshold voltage, lower gate capacitance, and faster switching transitions. A good PCB layout with low parasitic inductances can help to minimize the risk, but this is not feasible in all designs. In situations where spurious turn-on is likely to occur, the 1EDN71x6G gate driver provides an adjustable negative power supply to reinforce the off-state of the driven transistor during a fast switching event. This is achieved by the integrated negative charge pump. The negative voltage is adjustable to allow designers to optimize the tradeoff between spurious turn-on risk and higher reverse conduction losses during dead-time. GaN HEMTs have a reverse conduction mechanism that mimics a MOSFET body diode, with the exception that the "body diode" voltage drop is directly proportional to the negative voltage applied. Therefore, applying a more negative off-state voltage than necessary produces higher losses during the dead-time. The negative voltage can be adjusted according to the resistance value connected to VOFF_ADJ in according to the following table: Table 3 Resistance value connected to VOFF_ADJ Rvorr_aps Negative voltage Unit @VOFF <0.75 ka Disabled 15 ka -0.5 Vv 33 v 6.8 ka -15 Vv 15 ka -2.0 Vv 33 v With a resistance of lower than 0.75 kQ, the negative charge pump is disabled, and the VOFF output is floating with respect to VSS. In this case, the VOFF pin must be directly connected to VSS on the PCB. Resistances with + 10% accuracy are recommended to avoid overlapping of different levels. The resistance value is sampled during the startup transition of the gate driver, so the charge pump voltage cannot be adjusted on-the-fly during operation. As described in the absolute maximums and recommended operating condition tables, the driver's supply voltage rating is specified as the voltage swing between VDD and VOFF. If the charge pump is active with VOFF = - 3 V, the maximum voltage supplied to VDD is 3 V lower than it would be with the charge Datasheet T Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon pump disabled. In this way, designers can supply the driver with up to 11 V (for example for normal-level MOSFETs) when the charge pump is disabled, or they can instead choose to enable the charge pump and slightly reduce the positive supply voltage accordingly. The charge pump is designed to absorb current coming from the Miller capacitance C¢p, with a typical rms value of 50 mA and a peak value up to 5 A, while maintaining + 5% regulation.

2.8 Active bootstrap clamp

When using the bootstrapping technique to supply the high-side gate driver in a half-bridge topology, it is sometimes necessary to regulate the bootstrap capacitor voltage to avoid damaging the gate of the high-side transistor. This is especially important for GaN HEMTs for two reasons: 1. GaN SG HEMTs are often sensitive to gate over-voltage, with driving voltages typically in the range of 5 V +/-1V. 2. The "body diode" mechanism of GaN HEMTs causes a higher voltage drop than MOSFETs, which leads to excessive over-charging of the bootstrap capacitor during dead-time conduction. Ina half-bridge configuration, the bootstrap capacitor is normally charged during the low-side switch conduction time. Figure 4 shows this charging path, which includes the power supply (VDD), the bootstrap diode, current-limiting resistor, the bootstrap capacitor, and the low-side switch. When the low-side switching is turned fully on, the voltage applied to the bootstrap capacitor is slightly lower than VDD, due to the drop across the bootstrap diode, which can be partially compensated by the drop across the low-side transistor. However, during dead-time intervals, the low-side transistor operates in "body diode" mode, with a voltage drop in the range of 1.5 ~ 2.5 V, or even higher when a negative off-state V¢s is applied. This causes over-charging of the bootstrap capacitor during the dead-time, resulting in a bootstrap voltage that varies significantly with dead-time duration and operating current, with a high risk of exceeding the maximum rated V¢g of the driven transistor. This is not a problem for a typical MOSFET, since the operating range of the gate is fairly wide. However, this variable bootstrap capacitor voltage may pose a serious risk of damage to the Schottky gate of a GaN SG HEMT. Therefore, it is necessary to apply some form of regulation to this circuit. For example, a Zener diode can be used as shown in Figure 4, as long as the dead-time interval is well-controlled and paired with a current-limiting resistor that avoids overheating the Zener diode. The 1EDN71X6G driver offers an alternative bootstrap clamping scheme. Figure 5 shows the implementation of this bootstrap clamping scheme in a half-bridge circuit. The clamp circuit avoids over-charging the bootstrap capacitor instead of directly regulating the capacitor voltage, which would likely contribute additional losses. Rather than connecting the bootstrap diode to the VDD supply rail, it is connected to the BST output of the low-side driver. The BST output operates as a clone of the source and sink output pins, synchronized to the timing of the low-side transistor turning on and off. Therefore, the bootstrap diode can only conduct current when the low-side transistor is turned fully on, but not when it is operating in "body diode" mode during dead-time. The active bootstrap clamping scheme is very useful in regulating the high-side driving voltage without the need for additional components. However, in applications where over-charging of the bootstrap capacitor is desired, the bootstrap diode can be connected to the VDD pin instead of the BST pin. A Zener-based regulation scheme is recommended in this case, as shown in Figure 4 . Datasheet 8 Rev. 2.1 2021-10-12

EiceDRIVER™ 1EDN71x6G Infineon Cvoff_Q1 cf£.Ql MN Ul

100 Lo l a _10

Rinl_Q1 2 Vie aera? tgon_QI elit & HI _47i0hm rll Genes High-aite Ls | . | b 6 Dboot Rboot scnp<| — 1 EZ DD} dq = Rin2_Q1 E 47 kOhm 1EDN71X6G []Radj_Q1 i \\ Hanan et | ita Cvoff_Q2 C£_Q2 i 100nF 1}, | = 10 Rint_@] 2 |e meee, 9 __Rgon. 2 ef le Li "im 3 i | “Li — ri oF ] UT SNK / sy Low-side Rin2_Q2 r 47 40pm 1EDN7IX6G foul Cvdd [JRadj_Q2? PGND Figure 4 Half-bridge with Zener bootstrap regulation (CP enabled) Datasheet 9 Rev. 2.1 2021-10-12

EiceDRIVER” 1EDN71x6G Infineon Cvoff_Q1 cf Qi was UL 100 nFy les ou nag bere re H_47 hm VOFF_ADJ| OUT_SNK' High-side st BST| A Dboot ; Rin? Ql > 47 kOhm 1EDN71X6G []Radj_Ql ‘ sam | ans 1 Vphase. Cvoff_Q2 100nF 1 alr CF- VOFF Rinl_Q2 y Rgon_Q2 Sim —5 [oe | a SS oo ileal = lz a SGND = IN- a VDD q Rin2_Q? >

47 KOR IEDN71X6G #7 ze

[]Radj_Q2 PGND Figure 5 Half-bridge with active bootstrap clamping (CP enabled)

2.9 Unpowered gate clamp

The unpowered gate clamp circuit ensures that the driver output is pullowed low when no supply voltage is applied to the driver. It is common practice to place a resistor between the gate and source of transistors to ensure that there is no spurious voltage when the system is powered off. However, this is not necessary with the 1EDN71x6G. The driver has an internal pull-down MOSFET between the OUT_SNK pin and VSS pin, which pulls down the gate voltage to VSS with a peak current capability of 3 mA, whenever VDD is not sufficiently supplied to turn on the driver. Once the 1EDN71x6G is fully powered on, this pull-down MOSFET is disabled. OUT_SNK Power_on VSs Figure 6 Functional diagram of unpowered gate clamp circuit Datasheet 10 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

3 General product characteristics

3.1 Absolute maximum ratings

All voltages are referred to VSS unless otherwise specified. Table 4 Absolute maximum ratings Parameter Symbol Values Note or condition Positive supply | Vpp 0.30 |- 12 Vv voltage Driver supply | Vpop- Vor - - 12 Vv to negative rail LS, DC Driver supply | Vpp - Voge - - 13.2 |V <3ns to negative rail LS, AC Negative Vor - Vss -4 - 0.3 Vv charge pump output voltage Negative VoFF_aDJ 0.3 |- Vop+ |V charge pump 0.3 offset adjust voltage Voltage at CF+ | Vor+ 0.3 [- 4 Vv pin Voltage at CF- | Veg. Vorr- |- 0.3 Vv pin 0.3 Voltage at IN+ | Vins 8.5 |- 85 |v pin Voltage at IN- | Vin. 8.5 |- 85 |v pin Voltage at Vout_src» Vorr- |pins |VDD+]V OUT_SRC, Vout snk | 0.3 0.3 OUT_SNK, BST | Vast pins Junction Ty 40 |- 150 |°C temperature Storage Ts -55 - 150 |°C temperature Soldering - 260 |°C temperature Datasheet u Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

3.2 Recommended operating conditions

The following operating conditions must not be exceeded to ensure correct operation and reliability of the device. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise. Table 5 Recommended operating conditions Parameter Symbol Values Note or condition Driver output | Vpp - Voer - - 11 Vv voltage swing Operating Fow - - 15 MHz |?) frequency w/o charge pump Operating Fow - MHz With C.=1nF.” frequency with charge pump Common CMR -150 |- 150 |v Rext = 47k + 0.1%, Vogic= 3.3 V. mode voltage range (static) Common CMRayn -200 |- 200 |v Roxt= 47k + 0.1%, Viogic = 3.3 V. mode voltage Duration of voltage transient event must be range shorter than specified blanking time. ’ (dynamic) Common CMSR - - 100 |v/ns_ |” mode voltage slew rate Junction Ty -40 - 125 |°C temperature

3.3 ESD ratings

ESDugm | Human Body Model sensitivity as per ANSI/ESDA/JEDEC JS-001 v ESDepm __ | Charged Device Model sensitivity as per ANSI/ESDA/JEDEC JS-002 v 1 Verified by design/characterization. Not subject to production test. Datasheet 12 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

3.4 Thermal resistance

Table 7 Thermal resistance Parameter Symbol Values Note or condition Junction-to- | Rinya - 102. | - °C/W | JEDEC 2s2p with thermal vias. 2) ambient thermal resistance Junction-to- Rthsc(Bor) - 46 - °C/W case thermal resistance - bottom Junction-to- Rthsc(Top) - 117—sf- °C/W case thermal resistance - top

3.5 Static electrical characteristics

Vop = 5 V, Vorr = Veg = 0 V, Te = - 40°C to 125°C unless otherwise specified. Table 8 Static electrical characteristics Parameter Symbol Values Note or condition Undervoltage lockout thresholds VDD supply UVLOyppy = 3.7-—«| 3.85 | 4 v UVLO rising threshold VDD supply UVLOypp, =«|3.6 «3.75 3.9 Vv UVLO falling threshold Current consumption VDD quiescent | /gpp - - 2.6 mA Charge pump disabled, VOFF and VOFF_ADJ current w/o shorted to VSS. charge pump IN+=IN-=0V. VDD quiescent | /gpp_cp - - 19 mA Charge pump set to - 0.5 V (worst case). current w/ No load at VOFF. charge pump Cvore = 680 nF, Cfly = 100 nF. See plots. (table continues...)

2 Obtained in a simulation on a JEDEC-standard 2s2p four-layer PCB with thermal vias, as specified in

JESD51-7, in an environment described in JESD51-2a. Datasheet 13 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 8 (continued) Static electrical characteristics Parameter Symbol Values Note or condition Min. | Typ. | Max. VDD current lopp - - 3.5 mA Charge pump disabled. consumption fey = 500 kHz, no load on OUT_SRC/ when — OUT_SNK and no load on BST. switching w/o Apply PWM to IN+, set IN-=0V. charge pump Common mode =0V. VDD current lopp_cp - - 20.5 |mA Charge pump set to -0.5 V (worst case). consumption fey = 500 kHz, no load on OUT_SRC/ when — OUT_SNK and no load on BST. switching w/ Apply PWM to IN+, set IN-=0V. charge pump Common mode =0V. See plots. Input characteristics Differential AVeink 17 1.95 |2.2 Vv Thresholds valid for Rexr = 47 kQ. input voltage VCM =0Vand T=25°C. threshold for low-high transition Differential Vein 12 195 |2.65 |V Thresholds valid for Rext = 47 kQ. input voltage VCM =-150V to 150V. threshold for low-high transition Differential Wein 11 135 |16 |V Thresholds valid for Rey = 47 kQ. input voltage VCM =0Vand T= 25°C. threshold for high-low transition Differential Wein 0.7 135 |2.15 |V Thresholds valid for Rexr = 47 kQ. input voltage VCM =-150V to 150V. threshold for high-low transition Negative charge pump Negative rail Vorr_RANGE |-3 - 0 Vv adjusting range Negative rail Vorr_accurac | -5 - 5 % voltage y accuracy (table continues...) Datasheet 4 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 8 (continued) Static electrical characteristics Parameter Symbol Values Note or condition Charge pump - 50 mA steady-state average sink capability VOFF_ADJ Pin | laps oFF - - 800 |uA Only for 17 us pulse at initial startup of IC. 7 output current

3.6 Driver output characteristics

VDD = 5 V, VOFF = VSS = 0 V, Tc = 25°C unless otherwise specified. Table 9 Driver output characteristics Parameter Typical values Note or Peaksource | lour_src [2 15 1 0.5 A OUT_SRC=0V3) current Peak sink lour_snk |2 15 1 0.5 A OUT_SNK=5V3) current Peak sink lour_snk |5 5 5 5 A OUT_SNK=5 V3) current w/ MC Miller clamp Pull-up Rpy 1.0 15 3.0 a I_LSRC= 100 mA resistance Pull-down 1.0 15 3.0 fe) ILSNK= 100 mA resistance Pull-down Rep_mc |0.3 0.3 0.3 0.3 Q I_SNK= 100 mA resistance w/ Miller clamp Active Miller VuctH | 0.4 0.4 0.4 0.4 Vv 3) clamp voltage threshold Active Miller Tuco 3 3 3 3 ns No load. 3) clamp propagation delay Unpowered lout_snk |3 3 3 3 mA _ |VDD floating. gate clamp _UGC 1.2Vapplied sinking current externally to OUT_SNK. (table continues...) 3 Verified by design/characterization. Not subject to production test. Datasheet 15 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 9 (continued) Driver output characteristics Parameter Symbol Typical values Note or 1EDN71166 | 1EDN71266 | 1EDN71366 | 1EDN71466 condition Fall time Te 3 4 5.5 11 ns OUT_SNK shorted. C.=1nF?) BST peak Iest_sre |2 2 2 2 A BST=0Vv3) source current BST peak sink | /gst_ sx |2 2 2 2 A BST=5V3) current BST pull-up Rest_pu a |_BST_SRC = 100 resistance mA BST pull-down | Rest_pp fe) I_BST_SNK = 100 resistance mA

3.7 Timing characteristics

Timings are obtained considering OUT_SRC and OUT_SNK shorted together, Cop = 0 nF and over common mode range -150 V to 150 V, VDD = 5 V, VOFF = 0 V, Rex = 47 kO unless specified otherwise. Table 10 Timing characteristics Parameter Symbol Values Note or condition Startup time, | tst 17 25 us VSS = OV, Tj= 25°C. after UVLO - Including VOFF_ADJ readout. threshold is reached (charge pump disabled) Startup time, | tsrcp - 55 135 | us VSS = OV, Tj= 25°C, Vorr =-2 V. after UVLO Criy = 100 nF, Cyor¢ = 680 nF, including VOFF_ADJ threshold is readout. reached (charge pump enabled) Turn-on AT LH_st -2 - 2 ns Calculated as TLH - TLHgsr. propagation VCM = OV, T; = 25°C. delay matching OUT to BST Turn-off ATyu_pst -2 - 2 ns Calculated as THL - THLgsr. propagation VCM = OV, 7; = 25°C. delay matching OUT to BST (table continues...) Datasheet 16 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 10 (continued) Timing characteristics Parameter Symbol Values Note or condition 1EDN7116G Turn-on TLH 53 55 57 ns VCM =0V, Tj = 25°C. propagation delay Turn-off THL 53 55 57 ns VCM = OV, Tj = 25°C. propagation delay Propagation ATLH_HL -2.2 10 2.2 ns Calculated as TLH - THL. delay matching VCM = OV, 7; = 25°C. Shortest input | TPW_MIN 20 - 25 ns VCM = OV, Tj= 25°C. pulse transferred to the output 1EDN7126G Turn-on TLH 73 75 77 ns VCM = OV, Tj = 25°C. propagation delay Turn-off THL 73 75 77 ns VCM = OV, T= 25°C. propagation delay Propagation ATLH_HL -2.8 |- 2.8 ns Calculated as TLH - THL. delay matching VCM = OV, 7; = 25°C. Shortest input | TPW_MIN 40 - 47 ns VCM = OV, 7; = 25°C. pulse transferred to the output 1EDN7136G Turn-on TLH 101 105 109 ns VCM =0V, Tj = 25°C. propagation delay Turn-off THL 101 |105 (109 [ns VCM = OV, Tj = 25°C. propagation delay Propagation ATLH_HL 3.40 [- 3.4 ns Calculated as TLH - THL. delay matching VCM = OV, 7; = 25°C. Shortest input | TPW_MIN 60 - 71 ns VCM = OV, Tj= 25°C. pulse transferred to the output (table continues...) Datasheet 7 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 10 (continued) Timing characteristics Parameter Symbol Values Note or condition Min. | Typ. | Max. 1EDN7146G Turn-on TLH 121 125 |129 ns VCM = OV, Tj= 25°C. propagation delay Turn-off THL 121 125 129 ns VCM = OV, Tj= 25°C. propagation delay Propagation ATLH_HL 3.8 [- 3.8 ns Calculated as TLH - THL. delay matching VCM = OV, 7; = 25°C. Shortest input | TPW_MIN 80 - 93 ns VCM = OV, Tj= 25°C. pulse transferred to the output Datasheet 18 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

4 Typical characteristics

Voo= $V = = ON threshold Riya = Riya = 47 kQ —— OFF threshold 2 _ oo eee eee eee sis 14 ne -50 -25 0 25 50 75 100 125 150 Tr Figure 7 Differential input voltage threshold versus temperature 3 eee enneeeseeeset oS so4 Voo=5V

0.5 AVin wax = 3-3V

Rina = Rina = 47 kQ ~--ON threshold T,= 25°C — OFF threshold -150 -100 -50 0 50 100 150 Vem [V] Figure 8 Differential input voltage threshold versus common mode voltage Datasheet 19 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Vop=5V — 18 ~ 417 Nee Ee -50 -25 ie) 25 50 75 100 125 150 Figure 9 Quiescent current versus temperature (with charge pump disabled) T,=25°C — 18 — 17 a 4 5 6 7 8 9 10 1 Voo lV] Figure 10 Quiescent current versus supply voltage (with charge pump disabled) Datasheet 20 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Vop=5V

18 Cyoag= 1 nF

T,=25°C £10 s — 8 0 5 10 15 fay [MHz] Figure 11 Operating current with load versus frequency (with charge pump disabled) 16 ¢ Vop=5V Cioag= 1 nF 14 fo = 500 kHz 12 : * = 10 : 2 8 = > 6 rs o o a 2 + cp disabled Vee [V] Figure 12 Operating current with load versus charge pump voltage Datasheet 21 Rev, 2.1 2021-10-12

™ ie EiceDRIVER 1EDN71x6G Infineon bo . sv fevesnnsnennnnnfensnee soosssne 100 ae re en re cee rr ¢ 80 a a 2 = ooo = 60 4 $< $3. 40 —1EDN7116G Voo=5V AVyymax=3.3V - - -1EDN7126G

20 Riya = Rina = 47 KQ ~+~ 1EDN7136G

Vou = OV ses JEDN7146G -50 -25 0 25 50 75 100 125 150 Tred Figure 13 Turn-on propagation delay versus temperature 140 bo a

100 Se ee ee ee eee eee

Z 80 ssocdoccccect 2 SS Coo 40 ——1EDN7116G Voo=5V ~ = -1EDN7126G AViny ax = 3.3 V __

20 Ris = Rg = 47 KO 1£DN7136G

Vow = OV se TEDN7146G -50 -25 0 25 50 75 100 125 150 TP) Figure 14 Turn-off propagation delay versus temperature Datasheet 22 Rev, 2.1 2021-10-12

™ ie EiceDRIVER 1EDN71x6G Infineon yo . sasnsnstnstnsfeennennenvenneveinnnntee 100 neem a 80 oo = nn es eee £ 60 _—— 40 vo=5V — 1EDN7116G AViymax=3-3V ~~ -1E£DN7126G 20 Rina = Ring = 47k ~. = 1EDN7136G T,=25°C 1EDN7146G -150 -100 -50 0 50 100 150 Vow [V] Figure 15 Turn-on propagation delay versus common mode voltage 140 wo . asses . svn a . 100 Se a a —1EDN7116G Vpo= 5V ~ - -1EDN7126G » AViy max = 3-3V =.= 1£DN7136G Runs = Rin2 = 47 kQ Te2sec 1EDN7146G -150 -100 -50 0 50 100 150 Vow [V] Figure 16 Turn-off propagation delay versus common mode voltage Datasheet 23 Rev, 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon 4s —1EDN7116G Vop=5V 4 - - -1EDN7126G lour_sac = 100 mA = += 1EDN7136G nnn 35 “- EDN7146G prc

15 SE EETeCEr EEE EERE

-50 -25 0 25 50 75 100 125 150 Lr Figure 17 OUT_SRC pull-up resistance versus temperature saad —1EDN7116G Vop= 5V 4 ---1EDN7126G lour_snk = 100 mA —ppernt ~.~ 1EDN7136G ne _ sows JEDN7 1466 — 15 ——spovererer pes = OS -50 -25 oO 25 SO 75 100 125 150 Tr Figure 18 OUT_SNK pull-down resistance versus temperature (before active Miller clamp is engaged) Datasheet 24 Rev, 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

0.45 Voo= 5V

04 lour_sux= 100 mA 0.35 0.3 Gos of 0.2 0.15 0.1 0.05 -50 -25 0 25 50 75 100 125 150 TCC) Figure 19 OUT_SNK pull-down resistance versus temperature (after Miller clamp is engaged) ---RPU Voo= SV Igsr= 100 mA —— 1 ——RPD se _ 08 S § 06 Fd ES 0.4 0.2 -50 -25 t) 25 50 75 100 125 150 TPC Figure 20 BST pull-up and pull-down resistance versus temperature Datasheet 25 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon ---UVLO on — UVLO off 3.9 38 —— 771 S > — 3.7 3.6 3.5 -50 -25 0 25 50 75 100 125 150 Figure 21 Undervoltage lockout threshold versus temperature 0 ee a ee eee elie eee ated TTT > = - = 1£DN7126G £50 - += 1£DN7136G z ~~ 1EDN7146G

240 Toor gsscccsstesssccerecscccaccescecccceess anew e ncn

-50 -25 0 25 50 75 100 125 150 TPC] Figure 22 Minimum input pulse versus temperature Datasheet 26 Rev. 2.1 2021-10-12

EiceDRIVER” 1EDN71x6G Infineon

5 Application information

5.1 Typical application circuits

The 1EDN71x6G can be used as a single low-side driver or a single high-side driver, and two can be used together to drive a half-bridge. Figure 23 and Figure 24 depict example circuit schematics for single-device drivers with the optional charge pump enables and disabled respectively, giving the designer the option to generate a negative off-state voltage within the IC if this is required to avoid false triggering. Figure 4 and Figure 5 show two examples of half-bridge circuit schematics with two 1EDN71x6G, with conventional bootstrapping and Zener regulation in the first, and active bootstrap clamping enabled in the second. Figure 25 shows an additional example of half-bridge implementation, in this case with cross-connected PWM inputs for the high-side and low-side drivers. This option adds robustness against accidental cross-conduction in case the controller ever generates overlapping PWM signal. However, it may also limit the minimum dead-time as measured at the gate signals of the driven devices, due to asymmetrical turn-on and turn-off delay times of the driven transistors. It is important to note that the charge pump is enabled in all three of these example half-bridge circuits, however it can be easily disabled by modifying each individual driving circuit according to Figure 24. Cvoff CE Ul 100 nF 1 10 Rinl . \\CF- ‘VOFF| i Rgon fy 7 tobm ——CE+ OUT_SRC| — S Qi pwa mom 3 [OE | OUT sng 7 z= BsTP ! : SGND’ = IN- 2 vppt-* Rin2 > > VDR 47 kOnm 1EDN71X6G Cvdd []Radj Figure 23 Single channel with charge pump enabled CF- | VOFF o Rinl 2 Rgon a 2 Sort out_src}= = loi PWM_IN 47 40hm Mo o| a INt BsIP 7 i SGND =) oS | z VDD m2 a‘ 47 kOhm P >VDR Cvdd Figure 24 Single channel with charge pump disabled Datasheet 27 Rev. 2.1 2021-10-12

EiceDRIVER” 1EDN71x6G In fi neon Cvoff_Ql Cf_Ql uN UL 100 nF i | 10 Rint_Ql 2 surcane 2. Reon QI Qi HI 474m WORRLADT|| OUTTENK Hipivside r BSI Dboot _— Ea y paaé 4 Rin2_Q1 L > 47 kOhm 1EDN71X6G # [}Radj_Ql ‘Choot Vphase Cvoff_Q2 C£_Q2 100nF 1 | |_10 Rinl_Q2 2 9 Rgon_Q2 © @ _ | OFF ADJ} OUT_SNK Low-side ‘eee BE 2 vppi-4 Rin2_Q2 L : . ar ¥Onm 1EDN7IX6G =P vO: Cvdd []Radj_Q2 PGND Figure 25 Half-bridge with cross-connected signal inputs (CP enabled, active bootstrap clamping) Datasheet 28 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon 3.3V ' tty 1 1.3kQ H 7 IN+ i T Rint T 3 [ ]o.eska ' AVR, AVRa/ k Pa i | H Le bb fi 0.65kQ ' H 1.3kQ H H Coo Figure 26 TDI application circuit, including input external resistors and stray capacitance

5.2 Selection of TDI input resistors

The 1EDN71X6G requires precise input resistors at the IN+ and IN- pins, with resistance values of 47 kQ or 75 kQ, depending on the voltage level of the input logic signals. The driver is compatible with either a 3.3 V ora5V logic. These resistors are not optional, even if the application does not require the TDI function (for example low-side applications with no ground bounce concerns). The input logic thresholds at the IN+ and IN- pins are designed to be paired with the specified input resistor values. These input resistors should be selected with a 0.1% tolerance, especially in high-side applications, where the common-mode voltage rating is contingent upon tight matching of Ri; and Riy;. Extra care should be taken to ensure that these resistors are symmetrical, so that stray capacitance across them is also tightly matched. Figure 26 shows an example of how stray capacitances C,; and Cp, could interfere with the symmetry and matching of Riy; and Rjy2. To optimize this symmetry, the two resistors should have identical part numbers with the same package and footprint. Further PCB layout recommendations for ensuring symmetry are given later. In high-side applications, the input resistors must also be rated for the power dissipation expected in the worst-case operating conditions, The common-mode voltage observed by the high-side transistor is "blocked" by each input resistor, so that the 1EDN71X6G is not exposed to the high voltage. The resistors dissipate power during the intervals where CM voltage is high, typically during the high-side transistor's duty ratio of each switching period. The power rating of the resistors should therefore be selected based on Vite,max” ind Equation 1 where: Prin = Required power rating for Rina Prin2 = Required power rating for Rinz D=High-side duty ratio Vac,max = Maximum expected dc bus voltage, experienced as CM voltage during the high-side duty ratio It is important to consider that the duty ratio may not be constant, so D should be selected as the duty ratio when operating at the maximum dc bus voltage. The table below lists some examples for selecting the input resistors, based on logic voltage level, expected dc bus voltage, and duty ratio. For most applications, the power requirement is quite low, thereby allowing the designer to select very small resistor packages such as 0402 or 0603. In some extreme scenarios with a high dc voltage and high duty ratio simultaneously, larger packages with higher power ratings may be needed. Datasheet 29 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Table 11 Examples for selected input resistors Maximum dc bus Logic . TDI input Resistor Minimum Rin Duty ratio . . voltage voltage resistance tolerance power rating 60V 3.3V 0.25 4TkO 0.1% 0.02 W

5.3 Selection of VDD bypass capacitor

The Vpp bypass capacitor provides the gate charge to drive the transistor, as well as additional power consumption by the driver itself and the charge pump (if enabled). It should be placed as close as possible to the VDD and VSS pins of the gate driver, which may require a particular footprint size for most applications. The minimum value for this bypass capacitor can be calculated based on the maximum allowable voltage ripple in the design. This ripple should be minimized such that the lowest possible Vpp is above the UVLO limit of the gate driver as well as above the safe driving voltage of the transistor. The charge dissipated per switching event is the total of the driven transistor's gate charge and the additional consumption by the charge pump (if enabled). The minimum value can therefore be calculated as Qo + Qep Cvaa > Vad AVpp, max Equation 2 where the charge pump consumption can be determined through linear approximation. The typical operating consumption for the gate driver with a particular charge pump voltage is given in Figure 12 for 500 kHz with 1 nF of gate capacitance. The equivalent charge for the same charge pump voltage when operating at a different frequency with a different gate capacitance (C\\ss) can be approximated as ~ Top ) ( Ciss ) Qcv® (se kHz) *\\T nF Equation 3 If the charge pump is disabled, Qcp can be ignored. Ina half-bridge configuration, the Vpp bypass capacitor also provides the charge for the bootstrap capacitor during the charging period. Therefore, the Vpp bypass capacitor should be sized to be much larger than the bootstrap capacitor. The minimum value should be calculated as Qe + Qer + Qzoor Cvag > vaa AV pp, max Equation 4 where Qgoor is the charge consumed by the bootstrapping circuit each cycle. This value is calculated in a later section. In practice, this capacitance value should be increased somewhat to account for dc bias effects in the capacitor and other non-idealities in the circuit. Datasheet 30 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon

5.4 Selection of external bootstrap diode

When used in a half-bridge configuration, a bootstrapping circuit is often used to supply the high-side driver's Vpp- A fast recovery or schottky diode with low forward voltage drop is recommended in order to minimize the losses and leakage current. It should be chosen such that it can handle the peak transient current during start-up conditions and the blocking voltage rating should be higher than the maximum input voltage (Vix) with added margin. It is important to consider that the output capacitance and reverse recovery of this bootstrap diode contributes to the total switch-node capacitance of the half-bridge, thereby increasing the total switching losses of the application circuit. A schottky diode with low output capacitance is therefore the best choice for most applications. The 1EDN71x6G gate driver provides two options for bootstrap diode connection. The conventional approach is to connect the anode of the diode to the low-side Vpp rail, often with a current-limiting resistor between them to limit surge current during startup. However, the recommended approach with 1EDN71x6G is to connect the anode of the bootstrap diode to the BST pin of the low-side driver as shown in Figure 4 . This enables the integrated bootstrap clamping function of the driver, and it also provides current-limiting at startup without the need for an added resistor.

5.5 Selection of bootstrap capacitor

The bootstrap capacitor provides the necessary charge to drive the high-side transistor. It must be sized in such away that its lowest voltage will be much higher than the UVLO threshold as well as above the minimum safe driving voltage of the transistor, during transient and normal operations. To determine the minimum required bootstrap capacitance, the maximum allowable ripple in Vgoor must be calculated as follows. AVpoot, max = Vop — Ve — Vaoot, min Equation 5 where: Vpp = Low-side gate driver supply voltage V_ = Bootstrap diode forward voltage drop Vgootmin is the minimum allowable voltage for the bootstrap capacitor, including transient events. This voltage must be at least high enough to avoid UVLO shutdown, as given by: Equation 6 where: Vuer = High-side driver UVLO rising threshold Vuey = High-side driver UVLO threshold hysteresis However, the driven transistor may require a higher voltage than this UVLO minimum, in order to remain fully on and avoid linear-mode operation. If the calculated minimum Vgoor is lower than the safe driving voltage of the transistor, then Vgootmin Should be increased accordingly. Next, determine the total charge (Qgoor) that must be delivered by the bootstrap capacitor at maximum duty cycle. There are several factors that contribute to the discharge of the bootstrap capacitor such as the high-side transistor’s total gate charge and gate-source leakage current, charge pump consumption, bootstrap diode reverse bias leakage current, and bootstrap capacitor leakage current. For the sake of simplicity, the bootstrap capacitor leakage current can typically be neglected. The total bootstrap charge can be estimated as follows: Tvaa + Xi xD, Qnoor ® Qo + Qcp + ed Cuaioae max) Fw Equation 7 Datasheet 31 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon where: Qc = High-side transistor total gate charge Qcp = Additional consumption by charge pump, if enabled (equation given in earlier section) Ivaa = High-side driver maximum quiescent current Idiode = Bootstrap diode reverse bias leakage current Dmax = Maximum high-side duty cycle fow = Switching frequency The minimum bootstrap capacitor value can then be calculated using the formula: Qboor C > Boot AV goor, max Equation 8 In practice, this capacitance value should be increased somewhat to account for dc bias effects in the capacitor and other non-idealities in the circuit.

5.6 Selection of external gate resistors

The turn-on and turn-off external gate resistors control the turn-on and turn-off current of the gate driver providing an external way to control the switching speed of the MOSFET for purposes such as voltage overshoot control, ringing reduction, EMI mitigation, spurious turn-on protection, shoot -through protection, etc. In most designs, no external gate resistor is needed. Each of the four product variants offers a different pull-up and pull-down resistance, along with a corresponding peak source and sink current. However, in cases where the designers prefers a different source and sink driving strength, an external gate resistor may be used. The following formulas show the effect of the external gate resistor to the output current capability of the gate driver. Vop I, ¢ <r SRO-PK * Rey + RG, int + Reon, ext Equation 9 Vop Isnx. ex S$ SS SNK,PK ~ Rp + Ra,int + Roof f.ext Equation 10 where: Ispc,pk = Peak source current Isnx,px = Peak sink current Rpy = Gate driver pull-up resistance Rpp = Gate driver pull-down resistance Vpp = Gate driver supply voltage (equivalent to Vgoor for high-side transistor) Rg,int = Internal gate resistance of driven transistor Reon,ext = External gate resistance connected between Source output and gate Roffext = External gate resistance connected between Sink output and gate It is important to consider that the peak current may not reach this level during a fast switching transition, as is typical with GaN HEMTs. It is also worth nothing that this peak current cannot exceed the specified peak source/sink current of the gate driver, as the pull-up and pull-down transistors within the driver saturate at that current. However, the selection of product variant according to pull-up and pull-down resistance provides a close approximation to selection of external gate resistance in most cases. Datasheet 32 Rev. 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon Use of a non-zero R¢of_ext is not recommended for most designs, as this limits the effectiveness of the active Miller clamp feature. It is therefore preferable to choose the product variant based on the desired sinking or pull-down strength, and then add Rgon_ext only if needed to optimize the design.

5.7 Selection of adjustable charge pump circuit components

The charge pump is an optional feature of the 1EDN71X6G gate driver. At power-up of the driver (for example system startup), the driver senses the resistance at the VOFF_ADJ pin, then it enables the charge pump circuit if it senses a resistance greater than 750 Q. If the charge pump is not enabled at system startup, then the output of Vo¢r is floating with respect to VSS. There is no configuration that causes the Vor output to be 0 V with respect to VSS, so this short-circuit connection must be provided externally on the PCB. Otherwise, the off-state gate voltage of the transistor may not be OV. If the driver senses a resistor greater than 750 Q, the charge pump is enabled with a negative Vor voltage determined by the resistor value. This resistance must be selected based on the table given earlier in the datasheet. In this scenario, the designer must add a 100 nF flying capacitor between CF+ and CF- pins to support the internal charge pump circuit. Furthermore, a bypass capacitor must be placed between Vor; and VSS to provide a stable VOFF voltage and to supply the dynamic gate current during turn-off transitions. This capacitance value should selected based on the gate charge of the driven transistor, similar to the VDD bypass capacitor. The minimum required Vor¢ bypass capacitance can be determined by Ciss X Vorr Cvor sp > VIS R Vor, max Equation 11 where: Ciss = Input capacitance of the driven transistor Vorr = Selected charge-pump output voltage AVorr,max = Maximum deviation in Vo¢r allowable in the design As with the other bypass capacitors, it is recommended to add some margin to this capacitance value to account for capacitor dc bias effects and other circuit non-idealities.

5.8 PCB layout recommendations

The combination of the gate driver, bypass capacitors, and driven transistor forms a high-frequency current loop that defines the parasitic inductance in series with that loop. Likewise, in a half-bridge, the combination of the high-side and low-side transistors forms a high-frequency current loop with the bypass capacitors for the dc bus (for example Vin for a buck converter). The relative location on the PCB of those components is essential to reach high level of performance. The parasitic inductances within these loops can cause serious efficiency degradation due to dynamic effects. In addition, any coupling between the gate driving loops and half-bridge power loop can cause spurious switching events or other performance degradation. Coupling between either of these loops and the signal paths feeding to the TDI input resistors can also cause spurious switching. Finally, as mentioned previously, the TDI input circuit may be affected by stray capacitance and other asymmetries in the PCB design. Careful layout can help minimize or eliminate such unwanted effects. The following recommendations help the designer to optimize the PCB layout, as demonstrated in the half- bridge example pictures below. 1. Keep all high-frequency loops as short as possible, and use differential returns for current paths to cancel the magnetic fields and reduce parasitic inductance. 2. Minimize stray inductance, especially on low impedance lines. All high-current traces (VDD, VSS, OUT_SRC, OUT_SNK, VOFF) should be short and wide, and copper pours are recommended over traces when the design allows. 3. To optimize heat spreading, electrical shielding, and magnetic field cancellation, a VSS-connected copper pour should be placed directly underneath the IC as well as all components encompassed by the gate driving loop (for example bypass capacitors, gate and source pads of transistor). For the low-side Datasheet 33 Rev. 2.1 2021-10-12

EiceDRIVER” 1EDN71x6G Infineon driver, this shielding pour should be connected to PGND. For the high-side driver, it should be connected to the switch-node, which is the mid-point of the half-bridge. 4. To avoid interference between the power loop and gate loops, separate shielding layers should be used for each loop, even if they are both connected to the same net. 5. To optimize the symmetry of the TDI input resistors, they should be placed directly beside each other and symmetrically shielded on the first inner layer. The controller-side of the two resistors should be shielded by the controller ground net (SGND), and the driver-side of the two resistors should be shielded by the same VSS-connected copper used to shield the rest of the driving circuit. 6. The dielectric spacing between the top copper layer and first inner layer should be minimized to enhance the magnetic field cancellation effects. A spacing of 80 ~ 100 microns is used in the example below. Fi BE eS s decoupling : apacitors ae t Optional Q1 Rios Ca | | lemperature sensor Ve, BM EDN71x6G2 PB Ot (HS) = Ril 4 Roo a Lee Coad gale? aL f Rao 5 ms el. - MR a R a a u g off = et. Brcon71x6cu fee) | MOPN SE ne © 1 3 Optional Q2 t | temperature sensor Figure 27 3D top-side view of example half-bridge implementation Datasheet 34 Rev, 2.1 2021-10-12

EiceDRIVER 1EDN71x6G Infineon “ i Filled vias O . 8 mil holes one 12 mil diameter 00 ? 0 O fe) ) Figure 28 Top copper layer of example half-bridge implementation Dedicated high- : q ra oh he frequency current return | paths (V;, to GND and | V,-V, to driver) i | All TDI input resistors a ee Of ° o Y shielded on first inner layer: : | + Controller side shielded 00 | by SGND copper = > Driver side shielded by |« rere | | VSS-connected copper ie Oi gl” ol” island (PGND or VSW) tees | : . Figure 29 First inner copper layer of example half-bridge implementation Datasheet 35 Rev, 2.1 2021-10-12

om. EiceDRIVER 1EDN71x6G Infineon

6 Package information

Base part | Package type Orderable part number Marking code number 1EDN7116G | PG-VSON-10 | Tape and reel 4000 1EDN7116GXTMAL 1EDN7116G 1EDN71266 | PG-VSON-10 | Tape and reel 1EDN7126GXTMAL 1EDN71266 1EDN7136G | PG-VSON-10 | Tape and reel 1EDN7136GXTMAL 1EDN7136G 1EDN7146G | PG-VSON-10 | Tape and reel 1EDN7146GXTMAL 1EDN7146G Pint marking | et | 03 > || O|}® ©]0O Y | Sy Zz y 3.3 1 _ All dimensions are in units mm. The drawing is in compliance with ISO 128-30, Projection Method 1 [<+@] Figure 30 PG-VSON-10 packaging Datasheet 36 Rev. 2.1 2021-10-12

EiceDRIVER™ 1EDN71x6G Cin fineon 5 ms 0.9 Max. 3 | a) | UUUUU 8 ) L é FA l LJ F a : pa | ah ! | maninana Seating Be E | 0.3%45° Pint marking = 10x ° 10x lajposlq i MORE soplanarity 0.05 Max. Stand off All dimensions are in units mm The drawing is in compliance with ISO 128-30, Projection Method 1 [<>] Figure 31 PG-VSON-10 package dimensions ®) ope : 05 0.25 OR ZL US) ‘8x 10x AM = —-annons pst Ja ome 4 41 Jaa , Z . WH &\\. Vy Z Ts: guy if dst it Pint [BB copper 7] solder mask stencil apertures All dimensions are in units mm Figure 32 PG-VSON-10 recommended landing pattern Datasheet 37 Rev. 2.1 2021-10-12

—_— ) fi

200 V high-side TDI gate driver IC for GaN SG HEMTs and MO I n eo n

Revision History

Revision: 2021-10-18, Rev. 2.1 Previous Revision Revision [Date __| Subjects (major changes since last revision) 2.0 2021-07-26 Release of final version 21 2021-10-18 | Title changed, added package dimension image, other editorial revisions Trademarks All referenced product or service names and trademarks are the property of their respective owners. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG

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© 2021 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (‘Beschaffenheitsgarantie’) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 38 Rev. 2.1, 2021-10-18