1EDI20N12AF_15 INFINEON
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Technical content
Rev. 2.0, 2015-06-01 1EDI20N12AF Single Channel MOSFET and GaN HEMT Gate Driver IC 1EDI20N12AF 1EDI EiceDRIVER™ Compact
81726 Munich, Germany
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1EDI EiceDRIVER™ Compact 1EDI20N12AF Data Sheet 3 Rev. 2.0, 2015-06-01 Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, Ca nPAK™, CIPOS™, CIPURSE™, COMN EON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRI DGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFE T™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PR O-SIL™, PROFET™, RASIC™, Re verSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEW IS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GO LD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Te chnologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVC o, LLC (Visa Holdings In c.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corp oration. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrot echnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics of MURATA MANUFACTURING CO., MICROWAVE OFFI CE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Open wave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sate llite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Sy mbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. T EKTRONIX™ of Tektroni x Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26
Revision History
Page or Item Subjects (major changes since previous revision) Rev. 2.0, 2015-06-01 p17 dynamic parameter update Rev. 1.03, 2014-10-14 all pages parameter completion Rev. 1.02, 2014-02-14 p 8 application diagram
1EDI EiceDRIVER™ Compact 1EDI20N12AF Data Sheet 4 Rev. 2.0, 2015-06-01 Table of Contents
1EDI EiceDRIVER™ Compact 1EDI20N12AF Data Sheet 6 Rev. 2.0, 2015-06-01 List of Tables
1EDI EiceDRIVER™ Compact Single Channel MOSFET and GaN HEMT Gate Driver IC 1EDI20N12AF Data Sheet 7 Rev. 2.0, 2015-06-01 1O v e r v i e w Main Features
- Single channel isolated Gate Driver
- Input to output isolation voltage up to 1200 V
- For high voltage power FETs
- 4 A typical peak current at rail-to-rail outputs
- Separate source and sink outputs Product Highlights
- Galvanically isolated Coreless Transformer Driver
- Low input to output capacitive coupling
- Suitable for operation at high ambient temperature
- Wide input voltage operating range
- ideally suited for driving casc oded or normally-off Gallium Nitride HEMTs Typical Application
- AC and Brushless DC Motor Drives
- High Voltage PFC, DC/DC-Co nverter and DC/AC-Inverter
- Induction Heating Re sonant Application
- UPS-Systems
- Welding
- Solar MPPT boost converter
Description
The 1EDI20N12AF is a galvanically isolated single channel FET driver in a PG-DSO-8-51 package that provides output currents of at least 2 A at separated output pins. The input logic pins operate on a wide input voltage range from 3 V to 15 V using CMOS threshold levels to support even 3.3 V microcontroller. Data transfer across the isolation barrier is realized by the Coreless Transformer Technology. The undervoltage lockout (UVLO) functions for both input and output chip and an active shutdown feature are included to always guarantee safe operation. Product Name Gate Drive Current (min) Package 1EDI20N12AF ±2.0 A MOSFET level optimized PG-DSO-8-51
1EDI EiceDRIVER™ Compact 1EDI20N12AF Overview Data Sheet 8 Rev. 2.0, 2015-06-01 Figure 1 Typical Application OUT+ OUT+ Control EiceDRIVERTM 1EDI20N12AF EiceDRIVERTM 1EDI20N12AF IN+ IN+ IN- IN- GND1 VCC1 VCC2,H VCC2,L GND2,L GND2,HGND1 VCC1 OUT- OUT- DC DC
1EDI EiceDRIVER™ Compact 1EDI20N12AF Block Diagram Data Sheet 9 Rev. 2.0, 2015-06-01
2 Block Diagram
Figure 2 Block Diagram 1EDI20N12AF IN+ IN- GND1 VCC1 VCC2 OUT- OUT+ GND2 input filter TX UVLO active filter input filter GND1 VCC1 UVLO RX Shoot through protection VCC2
1EDI EiceDRIVER™ Compact 1EDI20N12AF Pin Configuration and Functionality Data Sheet 10 Rev. 2.0, 2015-06-01
3 Pin Configuration and Functionality
3.1 Pin Configuration
Figure 3 PG-DSO-8-51 (top view)
3.2 Pin Functionality
Logic input supply voltage with wide operating range (3.3 V o 15 V). IN+ Non Inverting Driver Input IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN- = low) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal pull-down-resistor favors off-state. Table 1 Pin Configuration Pin No. Name Function
1 VCC1 Positive Logic Supply
2 IN+ Non-Inverting Driv er Input (active high)
3 IN- Inverting Driver Input (active low)
4 GND1 Logic Ground
5 VCC2 Positive Power Supply Output Side
6 OUT+ Driver Source Output
7 OUT- Driver Sink Output
8 GND2 Power Ground
1EDI EiceDRIVER™ Compact 1EDI20N12AF Pin Configuration and Functionality Data Sheet 11 Rev. 2.0, 2015-06-01 IN- Inverting Driver Input IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN+ = high) Due to internal filtering a mi nimum pulse width is defined to ensure robu stness against noise at IN-. An internal pull-up-resistor favors off-state. GND1 Ground connection of input circuit. VCC2 Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this supply pin. OUT+ Driver Source Output Driver output pin sourcing current to turn on external switch transistor. During on -state the driving output is switched to VCC2. Switching of this ou tput is controlled by IN+ and IN-, resp .. This output will also be turned off at an UVLO event. During turn off the OUT+ terminal is able to sink approx. 100 mA. OUT- Driver Sink Output) Driver output pin sinking current to turn off external switch transistor. During off-state the driving output is switched to GND2. Switching of this output is controlled by IN+ and IN-, resp.. In case of UVLO an active shut down keeps the output low. GND2 Reference Ground Reference ground of the output driving circuit. In case of a bipolar supply (positive and negative voltag e with respect to switch source potential) this pin is connected to the negative supply voltage.
1EDI EiceDRIVER™ Compact 1EDI20N12AF Functional Description Data Sheet 12 Rev. 2.0, 2015-06-01
4 Functional Description
4.1 Introduction
The 1EDI EiceDRIVER™ Compact is a ge neral purpose gate driver. Basic control and protection features support fast and easy design of highly reliable systems. The galvanic isolation between input logic and driver output is achieved by utilizing on-chip Coreless Transformer Technology. The wide input range supports the direct connection of various signal sources like DSPs and microcontrollers. The separated rail-to-rail driver outputs simplify gate resistor selection, save an external high current bypass diode and improve dV/dt control. Figure 4 Application Ex ample Bipolar Supply
4.2 Supply
The driver can operate over a wide supply voltage range, either unipolar or bipolar. With bipolar supply the driver is typically operated with a positive voltage of 12 V at VCC2 and a negative voltage of -8V at GND2 relative to th e source potential as seen in Figure 4. Negative supply can help to prevent a dynamic turn on. For unipolar supply configuration the driver is typically supplied with a posi tive voltage of 12 V at VCC2. In this case, careful evaluation for turn off gate resistor sele ction is recommended to avoid dynamic turn on (see Figure 5). Figure 5 Application Exam ple Unipolar Supply GND1 IN+ IN- VCC1 OUT+ VCC2 GND2 OUT- +5 V SGND IN +12V 10R 1µ100n 3R3 -8V GND1 IN+ IN- VCC1 OUT+ VCC2 GND2 OUT- +5 V SGND IN +12V 10R 1µ100n 3R 3
1EDI EiceDRIVER™ Compact 1EDI20N12AF Functional Description Data Sheet 13 Rev. 2.0, 2015-06-01
4.3 Protection Features
4.3.1 Undervoltage Lockout (UVLO)
To ensure correct switching the device is equip ped with an undervoltage lockout for input and output independently. Operation starts only after both VCC levels have increased beyond the respective V UVLOH levels (see also Figure 8). If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The switch is turned off a nd the signals at IN+ and IN- are ignored until V VCC1 reaches the power-up voltage VUVLOH1 again. If the power supply voltage V VCC2 of the output chip goes down below V UVLOL2 the switch is again turned off and signals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again. Note: VVCC2 is always referred to GND2; the output UVLO function thus depends on the total supply voltage.
4.3.2 Active Shut-Down
The Active Shut-Down feature ensures a safe off-state if the output chip is not connected to the power supply, The gate is clamped at OUT- to GND2.
4.3.3 Short Circuit Clamping
During short circuit the gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connec ted to OUT+ limits this voltage to a value s lightly higher than the supply voltage. A maximum current of 500 mA may be fed back to the supply through this path for 10 μs. If higher currents are expected or tighter clamping is desired external Schottky diodes may be added.
4.4 Non-Inverting and Inverting Inputs
There are two possible input modes to control the switch. In the non-inverting mode IN+ controls the driver output while IN- is set to low. In the inverting mode IN- controls the driver output while IN+ is set to high, see Figure 7. A minimum input pulse width is required to filter occasional glitches.
4.5 Driver Outputs
The output driver section uses MOSFETs to provide a rail-to -rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be mainta ined as long as the driver ’s supply is stable. Due to the low internal voltage drop, switching behaviour is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated in the driver.
1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Data Sheet 14 Rev. 2.0, 2015-06-01
5 Electrical Parameters
5.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as absolute limits, i.e. exceeding them may lead to destruction of the integrated circuit. Table 2 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test ConditionMin. Max. Power supply output side VVCC2 -0.3 40 V 1) 1) With respect to GND2. Gate driver output VOUT VGND2-0.3 VVCC2+0.3 V – Positive power supply input side VVCC1 -0.3 18.0 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 18.0 V – Input to output isolation voltage VISO -1200 1200 V Junction temperature TJ -40 150 °C – Storage temperature TS -55 150 °C – Power dissipation (Input side) PD, IN –2 5 m W 2) @TA = 25°C 2) See Figure 10 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. Power dissipation (Output side) PD, OUT – 400 mW 2) @TA = 25°C Thermal resistance (Input side) RTHJA,IN – 145 K/W 2) @TA = 85°C Thermal resistance (Output side) RTHJA,OUT – 165 K/W 2) @TA = 85°C ESD capability VESD,HBM – 2 kV Human Body Model3) 3) According to EIA/JESD22-A114-C (dischar ging a 100 pF capacitor through a 1.5 kΩ series resistor).
1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Data Sheet 15 Rev. 2.0, 2015-06-01
5.2 Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1.
5.3 Electrical Characteristics
Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 5 to 7).
5.3.1 Voltage Supply
Table 3 Operating Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Max. Power supply output side VVCC2 10 35 V 1) 1) With respect to GND2. Power supply input side VVCC1 3.1 17 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 17 V – Switching frequency fsw –4 . 0 M H z 2) 3) 2) do not exceed max. power dissipation 3) Parameter is not subject to production test - verified by design/characterization Ambient temperature TA -40 125 °C – Thermal coefficient, junction-top Ψth,jt –4 . 8 K / W 3) @TA = 85°C Common mode transient immunity (CMTI) |dVISO/dt| – 100 kV/ μs 3) @ 1000 V Table 4 Voltage Supply Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. UVLO threshold input chip VUVLOH1 –2 . 8 5 3 . 1 V – VUVLOL1 2.55 2.75 – V – UVLO hysteresis input chip (VUVLOH1 - VUVLOL1) VHYS1 90 100 – mV – UVLO threshold output chip (MOSFET Supply) VUVLOH2 – 9.1 10.0 V – VUVLOL2 8.0 8.5 – V – UVLO hysteresis output chip (VUVLOH2 - VUVLOL2) VHYS2 550 600 – mV –
1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Data Sheet 16 Rev. 2.0, 2015-06-01
5.3.2 Logic Input
Note: Unless stated otherwise VCC1 = 5.0V
5.3.3 Gate Driver
IQ1 –0 . 6 5 1 . 0 m A VVCC1 = 5 V IN+ = High, IN- = Low =>OUT = High Quiescent current output chip IQ2 –1 . 2 2 . 0 m A VVCC2 = 15 V IN+ = High, IN- = Low =>OUT = High Table 5 Logic Input Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. IN+,IN- low input voltage VIN+L,VIN-L – – 30 % of VCC1 IN+,IN- high input voltage VIN+H,VIN-H 7 0 ––% o f V C C 1 IN+,IN- low input voltage VIN+L,VIN-L ––1 . 5 V – IN+,IN- high input voltage VIN+H,VIN-H 3 . 5 ––V – IN- input current IIN- –7 0 2 0 0 μA VIN- = GND1 IN+ input current IIN+ –7 0 2 0 0 μA VIN+ = VCC1 Table 6 Gate Driver Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. High level output peak current (source) 1EDI20N12AF IOUT+,PEAK 2.0 4.0 –A 1) IN+ = High, IN- = Low, VVCC2 = 15 V 1) voltage across the device V(VCC2 - OUT+) or V(OUT- - GND2) < VVCC2. Low level output peak current (sink) 1EDI20N12AF IOUT-,PEAK 2.0 3.5 –A 1) IN+ = Low, IN- = Low, VVCC2 = 15 V Table 4 Voltage Supply (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Data Sheet 17 Rev. 2.0, 2015-06-01
5.3.4 Short Circuit Clamping
5.3.5 Dynamic Characteristics
Dynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V. Table 7 Short Circuit Clamping Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Clamping voltage (OUT+) (VOUT - VVCC2) VCLPout – 0.9 1.3 V IN+ = High, IN- = Low, OUT = High IOUT = 500 mA pulse test, tCLPmax = 10 μs) Table 8 Dynamic Characteristics Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input IN to output propa- gation delay ON TPDON 90 115 137 ns CLOAD = 100 pF VIN+ = 50%, VOUT=50% @ 25°CInput IN to output propa- gation delay OFF TPDOFF 100 120 143 ns Input IN to output propa- gation delay distortion (TPDOFF - TPDON) TPDISTO -15 5 25 ns Input pulse suppression IN+, IN- TMININ+, TMININ- 30 40 – ns – IN input to output propagation delay ON variation due to temp TPDONt ––1 0 n s 1)CLOAD = 100 pF VIN+ = 50%, VOUT=50% 1) The parameter is not subject to production test - verified by design/characterization IN input to output propagation delay OFF variation due to temp TPDOFFt ––1 0 n s 1)CLOAD = 100 pF VIN+ = 50%, VOUT=50% IN input to output propagation delay distortion variation due to temp ( TPDOFF-TPDON) TPDISTOt ––4n s 1)CLOAD = 100 pF VIN+ = 50%, VOUT=50% Rise time TRISE 5 1 02 0n s CLOAD = 1 nF VL 20%, VH 80% Fall time TFALL 491 9 n s CLOAD = 1 nF VL 20%, VH 80%
1EDI EiceDRIVER™ Compact 1EDI20N12AF Electrical Parameters Data Sheet 18 Rev. 2.0, 2015-06-01
5.3.6 Active Shut Down
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Active shut down voltage VACTSD 1) Referred to GND2 –2 . 2 2 . 5 V IOUT-/IOUT-,PEAK=0.1, VCC2 open
1EDI EiceDRIVER™ Compact 1EDI20N12AF Package Outlines Data Sheet 20 Rev. 2.0, 2015-06-01
7 Package Outlines
Figure 9 PG-DSO-8-51 (Plastic (Green) Dual Small Outline Package)
1EDI EiceDRIVER™ Compact 1EDI20N12AF Application Notes Data Sheet 21 Rev. 2.0, 2015-06-01
8 Application Notes
8.1 Reference Layout for Thermal Data
The PCB layout shown in Figure 10 represents the reference layout used for the thermal characterisation. Pin 4 (GND1) and pin 8 (GND2) require each a ground plane of 100 mm² for achieving maximum power dissipation. The 1EDI20N12AF is conceived to dissipate most of the heat generated through these pins. The thermal coefficient junction-top ( Ψth,jt) can be used to calculate the juncti on temperature at a given top case temperature and driver power dissipation: Figure 10 Reference Layout for Thermal Data (Copper thickness 35 μm)
8.2 Printed Circuit Board Guidelines
The following factors should be taken into account for an optimum PCB layout.
- Sufficient spacing should be kept between high vo ltage isolated side and low voltage side circuits.
- The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and to reduce parasitic coupling.
- In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible. Tj Ψth jt, PD Ttop+⋅=
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