171021501 WURTH
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we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module 7 - 50V / 2.5A / 2.5 - 15V Output
DESCRIPTION
The VDRM series of the Mag I³C Power Module family provide a fully integrated DC-DC power supply including the buck switching regulator and inductor in a package. The WPMDU1251501 offers high efficiency and delivers up to 2.5A of output current. It operates from 7V input voltage up to 50 V. It is designed for fast transient response. It is available in a standard industrial high power density BQFN-41 (9 x 11 x 2.8mm) package with good thermal performance. The V DRM regulators have an on-board protection circuitry to guard against thermal overstress and electrical damage featuring t hermal shutdown, over-current, short- circuit, overvoltage and undervoltage protections. TYPICAL APPLICATIONS Point-of-Load DC-DC applications from 12V and 24V industrial rails Industrial, Test & Measurement, Medical applications System power supplies DSPs, FPGAs, MCUs and MPUs supply I/O interface power supply
FEATURES
Peak efficiency up to 96% Current capability up to 2.5A Wide input voltage range: 7V to 50V 65V transients capability Output voltage range: 2.5V to 15V Continuous output power: 37.5W Integrated shielded inductor solution for quick time to market and ease of use Adjustable switching frequency (0.3 to 1MHz) Current Mode Control Undervoltage lockout protection (UVLO) Adjustable soft-start and voltage tracking Frequency synchronization with external clock Thermal shutdown and output short circuit protection Cycle by cycle current limit Power Good Operating ambient temperature up to 85°C Operating junction temp. range: -40 to 105°C RoHS & REACH compliant Mold compound UL 94 Class V0 (flammability testing) certified Complies with EN 55022 class B radiated and conducted emissions standard TYPICAL CIRCUIT DIAGRAM CIN EN/UVLO VIN RT/CLK PGND SS/TRK FB VOUT Module RSET COUT AGND VIN VOUT INTSS PG BQFN-41
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module PACKAGE PGND VOUT SW SW AGND VOUT 11 VOUT 10 NC 9 NC 8 SW 7 SW 6 AGND 5 AGND 4 RCCOMP 3 COMP 2 RSET INT 1
18 PGND
17 PGND
16 PGND
15 VOUT
14 VOUT
13 VOUT
12 VOUT
20 PGND
19 PGND
25 BOOT
26 VIN
27 EN/UVLO
28 SS/TRK
29 INTSS
34 AGND
33 AGND
32 AGND
31 RT/CLK
30 INTRRTPGND 18
SYMBOL PIN TYPE PIN DESCRIPTION VIN 26 Power The supply input pin is a terminal for an unregulated input voltage source. It is required to place the input capacitor nearby the VIN pin and PGND. VOUT 10, 11, 12, 13, 14, 15, Power The o utput voltage pins are connected to the internal inductor. Connect external bypass capacitors between these pins and PGND. PGND 16, 17, 18, 19, 20, 40 Power This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with VIN and VOUT. Pad 40 should be connected to PCB ground planes using multiple vias for good thermal performance. AGND 4, 5, 32, 33, 34, 37 Supply These pins are connected to the internal analog ground (AGND) of the device. This node should be treated as the zero volt ground reference for the analog control circuitry. Pad 37 should be connected to PCB ground planes using multiple vias for good thermal performance. Not all pins are connected together internally. All pins must be connected together externally with a copper plane. Connect AGND to PGND at a single point (at the ground terminal of the first output capacitor). See Layout section for recommendations. RSET INT 1 Analog An internal resistor of 10KΩ is connected internally between R SET INT and FB. This is the low side resistor of the feedback voltage divider. Must be connected to AGND. FB 36 Input Connect a resistor from the last output capacitor terminal to FB to set the output voltage.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module PINS FOR OPTIONAL USE SYMBOL PIN TYPE PIN DESCRIPTION EN/UVLO 27 Input Enable and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to disable the device. A resistor divider between this pin, AGND, and VIN sets the UVLO voltage. RT/CLK 31 Input This pin sets the switching frequency. Left open will set the internal oscillator to the default switching frequency. An external resistor from this pin to AGND sets a user defined switching frequency. This pin ca n also be used to synchronize with an external clock. INTRRT 30 Analog Internal Resistor (R RT INT ) which defines the default switching frequency. Must be connected to AGND. SS/TRK 28 Input Soft-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time during start-up. A voltage applied to this pin allows for tracking and sequencing control. INTSS 29 Input Internal soft -start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the tracking feature of pin SS/TRK. PG 35 Output Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately ±6% out of regulation. A pull-up resistor is required if this function is used. AUXILIARY PINS DESCRIPTION SYMBOL PIN TYPE PIN DESCRIPTION COMP 2 Output Output of the error amplifier. Do Not Connect. This pin must be soldered to an isolated pad. RCCOMP 3 Analog Internal R and C of the compensation network. Do Not Connect. This pin must be soldered to an isolated pad. BOOT 25 Supply Internal bootstrap pin for the high -side MOSFET. Do Not Connect. This pin must be soldered to an isolated pad. SW 6, 7, 21, 22, 23, 24, 38, 41 Power Switch node. Do not place any external component on these pins or tie them to a pin of another function. NC 8, 9 Not connect. These pins are not connected to the internal circuitry, and are not connected to each other.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module
ORDERING INFORMATION
ORDER CODE PART DESCRIPTION SPECIFICATIONS PACKAGE PACKING UNIT 171021501 WPMDU1251501NT 2.5A / 37.5W version BQFN-41 Tape and Reel with 250 Units 178021501 Evaluation Board 2.5A / 37.5W version 1 PACKAGE SPECIFICATIONS Weight Molding compound UL class Certificate number 0.54g EME-G770H UL94 V-0 E41429 SALES INFORMATION SALES CONTACTS Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 1
74638 Waldenburg
Tel. +49 (0) 79 42 945 - 0 www.we-online.com powermodules@we-online.com
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the listed absolute maximum ratings may affect the device negatively and may cause permanent damage. SYMBOL PARAMETER LIMITS UNIT MIN MAX VIN Input voltage -0.3 65 V VOUT Output voltage -0.6 VIN V AGND AGND to PGND -0.2 2.3 V SW Switching node pin voltage -0.6 65 V Switching node pin voltage (10ns transient) -2 65 V EN/UVLO Enable/Undervoltage lockout pin voltage -0.3 5 V Enable/Undervoltage lockout pin source current 100 µA FB Output voltage adjust pin voltage -0.3 3 V PG Power good pin voltage -0.3 6 V Power good pin sink current 10 mA SS/TRK Soft-start/Tracking pin voltage -0.3 3 V Soft-start/Tracking pin sink current 200 µA INTSS Internal soft-start or tracking feature select pin voltage -0.3 3 V RT/CLK Timer/Clock pin voltage -0.3 3.6 V Timer/Clock pin source current 100 µA Tstorage Assembled, non operating storage temperature -65 150 °C TSOLR Peak case/leads temperature during reflow soldering, max. 30sec per JEDEC J-STD020. Maximum three cycles! 245 ±5°C °C Mechanical Shock Mil-STD-883D, Method 2002.3, 1msec, ½ sine, mounted 1500 G Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz 20 G OPERATING CONDITIONS Operating conditions are conditions under which operation of the device is intended to be functional. All values are referenced to GND. SYMBOL PARAMETER MIN (1) TYP (2) MAX (1) UNIT VIN Input voltage 7 - 50 V VOUT Regulated output voltage 2.5 15 V fSW Switching frequency 300 - 1000 kHz TA Ambient temperature range -40 - 85 (3) °C TJ Junction temperature range -40 - 105 °C IOUT Nominal output current 2.5 A THERMAL SPECIFICATIONS SYMBOL PARAMETER TYP UNIT θJA Thermal resistance junction to ambient (4) 14 °C/W ψJT Thermal resistance junction to top (5) 3.3 °C/W ψJB Thermal resistance junction to board (6) 6.8 °C/W TSD Thermal shutdown, junction temperature, rising 180 °C Thermal shutdown hysteresis, falling 15 °C
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module ELECTRICAL SPECIFICATIONS MIN and MAX limits are valid for the recommended ambient temperature range of -40°C to 85°C. Typical values represent statistically the utmost probability at following conditions: VIN = 24 V, VOUT = 5.0 V, IOUT = 2.5 A, RT = Open, CIN = 2 x 2.2 μF ceramic, COUT = 2 x 47 μF ceramic, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT Output current IOCP Over current protection - 5.1 - A Accuracy VFB Reference accuracy TA = 25°C; IOUT = 100mA with internal feedback resistor - - ±2.0 (7) % Temperature variation -40°C ≤ TA ≤ +85°C - ±0.5 ±1.0 % VOUT Line regulation Over input voltage range - ±0.1 - % Load regulation Over output current range - ±0.4 - % Total output voltage variation Includes set-point, line, load, and temperature variation - - ±3.0 (7) % Output voltage ripple 0.25A ≤ IOUT ≤ 2.5A, VOUT ≥3.3V - 1 - % of VOUT Switching frequency fSW Free-running oscillator frequency RT/CLK pin open 300 400 500 kHz fCLK Synchronization clock frequency range 300 - 1000 kHz DCLK Synchronization clock duty cycle range 25 50 75 % VCLK-H High-level threshold CLK Relative to AGND - 1.9 2.2 V VCLK-L Low-level threshold CLK Relative to AGND 0.5 0.7 - V Enable and undervoltage lockout VUVLO VIN undervoltage lockout No hysteresis, rising and falling - 2.5 - V VEN EN threshold trip point VEN rising and falling, no hysteresis 1.15 1.25 1.36 (8) V IEN EN input current VEN < 1.15V - -0.9 - µA VEN > 1.36 V - -3.8 - µA IEN to AGND, VEN= 0V - 1.3 4 µA Power Good PG Power good thresholds VOUT rising, VOUT GOOD - 94 - % VOUT rising, VOUT FAULT - 109 - % VOUT falling, VOUT GOOD - 91 - % VOUT rising, VOUT FAULT - 106 - % Power good low voltage I(PG) = 3.5mA - 0.2 - V Efficiency η Efficiency VIN = 24V, IOUT = 1.5 A, VOUT = 5 V, fSW = 500 kHz - 84 - % VIN = 48V IOUT = 1.5A, VOUT = 5V, fSW = 500 kHz - 79 - %
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module SYMBOL PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT Transient Response TTR Transient response Recovery time 1A/µs load step from 50 to 100%, - 400 - µs VTR Transient response VOUT over/undershoot 1A/µs load step from 50 to 100%, - 90 - mV Quiescent current IQ Input quiescent current EN = 0V, TA = 25°C, 3.5V ≤ VIN ≤ 60V 1.3 4 µA Non switching: VFB = 0.83V, TA = 25°C, VIN = 12 V 200 µA RELIABILITY SYMBOL PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT MTBF Mean Time Between Failures Confidence level 60%, TA=55°C, Activation energy 0.7eV, 1000 hrs test duration, 46185 samples, 1 fail 1.79·109 h NOTES (1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. (2) Typical numbers are valid at 25°C ambient temperature and represent statistically the utmost probability assuming the Gaussian distribution. (3) Depending on heat sink design, number of PCB layers, copper thickness and air flow. (4) Measured on a 100 x 100mm four layer board, with 35µm (1 ounce) copper, no air flow (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, T J, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, T J, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. (7) The stated limit of the feedback voltage tolerance includes the tolerance of both the inter nal voltage reference and the internal adjustment resistor RSET INT . The overall output voltage tolerance is affected by the tolerance of the external RSET resistor. (8) Value when no voltage divider is present at the EN/UVLO pin.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module TYPICAL PERFORMANCE CURVES If not otherwise specified, the following conditions apply: VIN = 7-50V; CIN = 2x 2.2µF X7R ceramic; CO = 2x 47µF X7R ceramic, TAMB = 25°C. 11D Ambient Temperature [°C] Thermal Derating: VIN = 12V; VOUT = all voltages Output Current [A] Natural Convection 12D Ambient Temperature [°C] Thermal Derating: VIN = 24V; VOUT = all voltages Output Current [A] Natural Convection 15D Ambient Temperature [°C] Thermal Derating: VIN = 36V; VOUT = all voltages Output Current [A] Natural Convection 16D Ambient Temperature [°C] Thermal Derating: VIN = 48V; VOUT = all voltages Output Current [A] Natural Convection
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module TYPICAL PERFORMANCE CURVES If not otherwise specified, the following conditions apply: VIN = 7-50V; CIN = 2x 2.2µF X7R ceramic; CO = 2x 47µF X7R ceramic, TAMB = 25°C. 30 100 1000 Frequency [MHz] Radiated Emissions [dBµV/m] Radiated Emissions 171021501 Measured on evaluation board without input filter VIN = 24V, VOUT = 5V, fSW = 500kHz, ILOAD = 2A Horizontal Vertical EN55022 Class A limit EN55022 Class B limit 30 100 1000 Frequency [MHz] Radiated Emissions [dBµV/m] Radiated Emissions 171021501 Measured on evaluation board with input filter Cf = 2.2µF and Lf = 22µH VIN = 24V, VOUT = 5V, fSW = 500kHz, ILOAD = 2A Horizontal Vertical EN55022 Class A limit EN55022 Class B limit 0.15 1 10 Frequency [MHz] Conducted Emissions [dBµV/m] Conducted Emissions 171021501 Measured on evaluation board with input filter Cf = 2.2µF and Lf = 22µH VIN = 24V, VOUT = 5V, fSW = 500kHz, ILOAD = 2A Average Quasi peak EN55022 Class B Quasi Peak limit EN55022 Class B Average limit -10 0.5
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module TYPICAL PERFORMANCE CURVES If not otherwise specified, the following conditions apply: VIN = 7-50V; CIN = 2x 2.2µF X7R ceramic; CO = 2x 47µF X7R ceramic, TAMB = 25°C. 01D Efficiency [%] Output Current [A] Efficiency: VIN = 12V @ TAMB = 25°C 100 VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz 05D Power Loss [W] Output Current [A] Power Loss: VIN = 12V @ TAMB = 25°C VOUT = 5.0V, fSW =500 kHz VOUT = 3.3V, fSW =400 kHz VOUT = 2.5V, fSW =400 kHz 02D Efficiency [%] Output Current [A] Efficiency: VIN = 24V @ TAMB = 25°C 100 VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 06D Power Loss [W] Output Current [A] Power Loss: VIN = 24V @ TAMB = 25°C VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 03D Efficiency [%] Output Current [A] Efficiency: VIN = 36V @ TAMB = 25°C 100 VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 07D Power Loss [W] Output Current [A] Power Loss: VIN = 36V @ TAMB = 25°C VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module TYPICAL PERFORMANCE CURVES If not otherwise specified, the following conditions apply: VIN = 7-50V; CIN = 2x 2.2µF X7R ceramic; CO = 2x 47µF X7R ceramic, TAMB = 25°C. 04D Efficiency [%] Efficiency: VIN = 48V @ TAMB = 25°C VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 100 Output Current [A] 08D Power Loss [W] Output Current [A] Power Loss: VIN = 48V @ TAMB = 25°C VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 09D Output Voltage Ripple [mV] Output Voltage Ripple: VIN = 12V @ TAMB = 25°C Output Current [A] VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz 10D Output Voltage Ripple [mV] Output Voltage Ripple: VIN = 24V @ TAMB = 25°C Output Current [A] VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 13D Output Voltage Ripple [mV] Output Voltage Ripple: VIN = 36V @ TAMB = 25°C Output Current [A] VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz 14D Output Voltage Ripple [mV] Output Voltage Ripple: VIN = 48V @ TAMB = 25°C Output Current [A] VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module BLOCK DIAGRAM INTSS RT/CLK PG FB SS/TR SW EN/UVLO VOUT PGND PWM Controller Driver Protection Circuitry BOOT RCCOMP INTRRT AGND COMP 29 2 3 1 COUTRSET VOUT AGND PGND Linear Regulator VIN UVLO CIN VIN PGND RSET INT Cboot 4.9µHVIN26 2 µA VR EF AGND PGND 28 3130 10-15, 39 0.8V Power Module Error Amplifier 10kΩ CIRCUIT DESCRIPTION The MagI³C Power Module WPMDU1251501 is based on a non synchronous step down regulator with integrated MOSFET, schottky diode and a power inductor. The control scheme is based on a Current Mode (CM) regulation loop. The VOUT of the regulator is divided with the feedback resistor network RSET and an internal 10KΩ resistor and fed into the error amplifier which compares this signal with the internal 0.8V reference VREF. The error signal is amplified and controls the on-time of a fixed frequency pulse with generator. This signal drives the power MOSFET. The Current Mode architecture features a constant frequency during load steps. Only the on-time is modulated. It is internally compensated and stable with low ESR output capacitors and requires no external compensation network. This architecture supports fast transient response and very small output ripple values (less than 10mV) are achieved.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module DESIGN FLOW The next 10 simple steps will show how to select the external components to design your power application. Essential Steps 1. Set output voltage 2. Set operating frequency 3. Select input capacitor 4. Select output capacitor Optional Steps 5. Select soft-start capacitor 6. Select undervoltage lockout divider 7. Enable/Disable 8. Voltage tracking 9. Synchronization to an external clock 10. Power Good CIN EN/UVLO VIN RT/CLK PGND SS/TRK FB VOUT Module RSET CSS COUT AGND VIN VOUT INTSS PG RUVLO1 RUVLO2 RRT 10. 1. 3. 4. Step 1 Setting the output voltage (VOUT) The MagI³C Power Module is designed to provide output voltages from 2.5 V to 15 V. The output voltage is determined by the value of RSET, which must be connected between the V OUT node and the FB pin (Pin 36). For output voltages higher than 5 V, improved operating performance can be obtained by increas ing the operating frequency. This adjustment requires the addition of RRT between RT/CLK (Pin 31) and AGND (Pin 30). See the Step 2 Set operating frequency section for more details. Table 1 gives the standard external RSET resistor for a number of common bus voltages and also includes the recommended RRT resistor for output voltages above 5 V. VOUT RSET 2.5V 21.5kΩ 3.3V 31.6kΩ 5V 52.3kΩ 9V 102kΩ 12V 140kΩ 15V 178kΩ Table 1: Recommended standard output voltages
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module For other output voltages the value of RSET can be calculated using the following formula. RSET = 10 ∗ ( VOUT 0.798 − 1) kΩ (1) The MagI³C Power Module operates over the input voltage range of 7 V to 50 V. For reliable start-up and operation at light loads, the minimum input voltage depends on the output voltage (see table below). Output voltage range Condition Input voltage VOUT ≤ 12V 7V ≤ VIN ≤ 50V VINmin ≥ VOUT + 3V VINmax ≤ VOUT *15 VOUT > 12V VINmin ≥ VOUT *1.33 VINmax ≤ VOUT *15 Although the device can safely handle input surge voltages up to 65 V, sustained operation at input voltages above 50 V is not recommended. See the Step 6 (Undervoltage Lockout (UVLO) Threshold section) for more information. VOUT RSET 10kΩ AGND RSET INT FB Step 2 Setting the operating frequency (fSW) Nominal switching frequency of the MagI³C Power Module is set from the factory at 400 kHz. This switching frequency is optimized for output voltages below 5 V. For output voltages of 5 V and above, better oper ating performance can be obtained by raising the operating frequency. This is easily done by adding a resistor, RRT from the RT/CLK pin (Pin 31) to the AGND pin (Pin 30). Raising the operating frequency reduces output voltage ripple, lowers the load curren t threshold where pulse skipping begins, and improves transient response. The recommended switching frequency for typical output voltages is listed in Table 2. For the maximum recommended output voltage value of 15 V, the switching frequency computes to 1 MHz. Operation above 1 MHz is not recommended. VOUT fSW RRT 2.5V 400kHz Open 3.3V 400kHz Open 5V 500kHz 1,1MΩ 9V 700kHz 365kΩ 12V 800kHz 267kΩ 15V 1MHz 178kΩ Table 2: Standard Switching Frequencies
frequencies. The lower boundary of the graph shows the minimum input voltage as a function of the output voltage. Figure 1. Input Voltage vs. Output Voltage Operating Area
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module Step 3 Select input capacitor (CIN) The WPMDU1251501 MagI³C power module contains no internal input capacitors. Therefore an external input capacitance placed directly at the V IN pin is required to handle the input ripple current of the application. The input capacitor can be several capacitors in parallel. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by the equation: ICINRMS ≈ 1 2 ∗ IOUT ∗ √ D 1 − D (2) where D ≈ VOUT VIN (As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 * VOUT). If the system design requires a certain minimum value of peak -to-peak input ripple voltage (ΔVIN) be maintained then the following equation may be used. CIN ≥ IOUT ∗ D ∗ (1– D) fSW ∗ ΔVIN (3) If ΔVIN is 1% of VIN for a 24V input to 5V output application this equals 240 mV and fSW = 500kHz. CIN ≥ 2.5A ∗ 5V 24V ∗ (1– 5V 24V) 500000 ∗ 0.24V CIN ≥ 3.4µF Recommended minimum input capacitance is 4.4µF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. It should be noted that rip ple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module Step 4 Select output capacitor (COUT) L COUT RloadVIN VOUT IL Iout HS Mosfet ESRVES R VCOUT LS Mosfet CIN None of the required output capacitors is integrated within the module. . At a minimum, the output capacitor must meet the worst case RMS current rating of 0.5 ∗ ∆𝐼𝐿 , as calculated in equation (4). ∆IL = VOUT ∗ (VIN − VOUT) fSW ∗ L ∗ VIN (4) Beyond that, additional capacitance will reduce output ripple as long as the ESR is low enough to permit it. There is no limit of the maximum output capacitance. Please consider the derating of the nominal capacitance value due to temperature, aging and applied DC voltage (only for MLCC, e.g. X7R up to -50%). Selection by output voltage ripple requirements The capacitor should be selected in order to minimize the output voltage ripple and provide a stable voltage at the output. Under steady state conditions, the voltage ripple observed at the output can be defined as: VOUT ripple = ∆IL ∗ ESR + ∆IL ∗ 1 8 ∙ fSW ∙ COUT (5) Very low ESR capacitors, like ceramic and polymer electrolytic, are recommended. If a low ESR capacitor is selected, the equation (4) can be simplified and a first condition for the minimum capacitance value can be derived: COUT ≥ ∆IL 8 ∗ VOUT ripple ∗ fSW (6)
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module The use of very low ESR capacitors leads to an output voltage ripple as shown below: When capacitors with slightly higher ESR are utilized, the dominant parameter which influences the output voltage ripple is just the ESR: ESR ≤ VOUT ripple ∆IL (7) Consequently the shape of the output voltage ripple changes, as shown below: -10 0 1 2 3 Output voltage ripple [mV] time [µs] Output voltage ripple with low ESR capacitors -100 -50 100 0 1 2 3 Output voltage ripple [mV] time [µs] Output voltage ripple with high ESR capacitors
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module Selection by load step requirements The output voltage is also affected by load transient (see picture below). By the output current transition from a low to a high value, the voltage at the output capacitor (VOUT) drops. This involves two contributions. One is caused by the voltage drop across the ESR (V ESR) and depends on the slope of the rising edge of the current step (trise). For low ESR values and small load currents, this is often negligible. It can be calculated as follows: VESR = ESR ∗ ∆IOUT (8) Where ∆𝐼𝑂𝑈𝑇 is the load step, as shown in the picture below (simplified: no voltage ripple is shown). 0 t Iout 0 t Vout ∆Iout ∆Vout VESR Vdischarge td treg trise The second component is the voltage drop due to discharge of the output capacitor, which can be estimated as: Vdischarge = ∆IOUT ∙ td 2 ∙ COUT (9) In a current mode architecture the t d is strictly related to the bandwidth of the regulation loop and influenced by the C OUT (increasing COUT, the td increases as well).
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module In order to choose the value of the output capacitor, the following steps should be followed: 1. According to the operating conditions (VIN, VOUT and fSW), select the minimum COUT recommended in table on page 38. 2. Measure td. 3. Calculate the appropriate value of C OUT for the maximum voltage drop V discharge allowed at a defined load step, using the following equation (10), derived from equation (9): COUT ≥ ∆IOUT ∙ td 2 ∙ Vdischarge (10) 4. As above mentioned, changing C OUT affects also t d. Therefore a new measure should be performed and, if necessary, the step 2 and 3 should be repeated (it is an iterative process and few steps could be required). According to the table on page 3 8, two output MLCC of 47µF would be necessary. After mounting these capacitors, the load transient should be performed and the td measured (see picture below). The ΔVOUT = 0.13V and td= 3µs. It is important to remind that the ΔVOUT includes also the voltage drop during trise, mainly due to the ESR (VESR = 60mV, see picture above). In order to achieve the desired maximum ΔVOUT, the Vdischarge should be below 0.025V. Using the equation (9), the minimum required output capacitor is: COUT ≥ 2A ∙ 3µs 2 ∙ 0.025V = 120µF To achieve the calculated value of COUT, an additional MLCC of 47µF is mounted in parallel. -0,3 -0,2 -0,1 0,1 0,2 0,3 0 10 20 30 40 50 60 VOUT (AC coupled) [V] IOUT [A] time [µs] Load transient with COUT = 47µF MLCC ΔVOUT = 0.29V 6µs Vdischarge = 0.2V VOUT IOUT
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module The result with three MLCC of 47µF in parallel is shown below: In order to have a safer margin from the desired ΔVOUT<0.1V, additional capacitance at output would be required. -0,30 -0,20 -0,10 0,00 0,10 0,20 0,30 0 20 40 60 80 100 120 VOUT (AC coupled) [V] IOUT [A] time [µs] Load transient with COUT = 2x47µF MLCC + 220µF electrolytic VOUT IOUT ΔVOUT = 0.16V 24µs Vdischarge = 0.1V
SS capacitor values and timing interval. Figure 4. Soft-Start Capacitor Css and INTSS connection
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module The VON UVLO threshold must be set to at least (V OUT + 3 V) or 6.5 V whichever is higher to insure proper startup and reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set the UVLO threshold to approximately 80% to 85% of the minimum expected input voltage. VOFF should be selected to be at least 500 mV less than VON. Use equation 6 and 7 to calculate the values of RUVLO1 and RUVLO2. RUVLO1 = VON − VOFF 2.9 ∗ 10−3 kΩ (10) RUVLO2 = 1.25 VON − 1.25 RUVLO1 + 0.9 ∗ 10−3 kΩ (11) Table 4 lists standard resistor values for RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages. VON Threshold RUVLO1 RUVLO2 6.5V 174kΩ 40.2kΩ 10V 24.3kΩ 15V 15.8kΩ 20V 11.5kΩ 25V 9.09kΩ 30V 7.5kΩ 35V 6.34kΩ 40V 5.62kΩ 45V 4.99kΩ Table 4: Standard VON Threshold Values
voltage, VOUT2, powers the core. rail to be shorter than the master rail. Therefore place an external soft-start capacitor at the master module1. Figure 10. Voltage tracking configuration
Figure 11. Simultaneous voltage tracking waveforms First select R2TR . A value below 10K is recommended. Use equation 8 to calculate the resistor R1TR.
a duty cycle between 20 % to 80 %. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V. CLK mode are needed, the device can be configured as shown in Figure 12. Before the external clock is present, the device works in RT mode where the switching frequency is set by the RRT resistor. frequency set by the RRT resistor. Figure 12. Synchronization Configuration if the input UVLO or thermal shutdown is asserted, the EN pin is pulled low, or the SS/TRK pin is below 1.4 V.
switching frequency combinations. Figure 13. Pulse Skipping Load Threshold
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module PCB Layout Instructions: PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC- DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC -DC converter resulting in poor regulation or instability. Good layout can be implemented by following five simple design rules. 1: Minimize area of switched current loops CIN VIN PGND VOUT Power Module COUT Loop 1 Loop 2 High di/dt VIN VOUT Target is to identify the paths in the system which have discontinuous current flow. They are the most critical ones because they act as an antenna and cause observable high frequency noise (EMI). The easiest approach to find the critical paths is to draw the high current loops during both switching cycles and identify the sections which do not overlap. They are the ones where no continuous current flows and high di/dt is observed. Loop 1 is the current path during the ON -time of the High-Side MOSFET. Loop 2 is the current path during the OFF-time of the High-Side MOSFET. VIN VIN FB PGND VOUT Module RSET COUT AGND CIN VOUT Based on those considerations, the path of the input capacitor CIN is the most critical one to generate high frequency noise on Vin. Therefore place CIN as close as possible to the MagI³C power module VIN and PGND pins. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the i nput and output capacitor should consist of a localized top side plane that connects to the PGND pins.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module The placement of the input capacitors is highlighted in the following picture of the reference board: CIN1 CIN2 CIN3 COUT1 COUT2 RSET RRT CSS RUVLO2 RUVLO1 VIN VOUT PGND SW AGND FB EN/UVLO RT/CLK SS/TRK INTSS PG 2: Have a single point ground The ground connections for the clock setting, soft-start, and enable components should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Connect the AGND and PGND copper area at one point at the ground terminal of the first output capacitor. CIN1 CIN2 CIN3 COUT1 COUT2 RSET RRT CSS RUVLO2 RUVLO1 VIN VOUT PGND SW AGND FB EN/UVLO RT/CLK SS/TRK INTSS PG
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module 3: Minimize trace length to high impedance pins The feedback resistor , RSET should be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RSET should be routed away from the body of the MagI³C power module to minimize noise pickup. Place RRT, and CSS as close as possible to their respective pins. CIN1 CIN2 CIN3 COUT1 COUT2 RSET RRT CSS RUVLO2 RUVLO1 VIN VOUT PGND SW AGND FB EN/UVLO RT/CLK SS/TRK INTSS PG 4: Make input and output terminal connections as wide as possible This reduces any voltage drops on the input or output of the converter and maximizes efficiency. CIN1 CIN2 CIN3 COUT1 COUT2 RSET RRT CSS RUVLO2 RUVLO1 VIN VOUT PGND SW AGND FB EN/UVLO RT/CLK SS/TRK INTSS PG
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module 5: Provide adequate device heat-sinking Place a dedicated AGND copper area beneath the MagI³C Power Module. CIN1 CIN2 CIN3 COUT1 COUT2 RSET RRT CSS RUVLO2 RUVLO1 VIN VOUT PGND SW AGND FB EN/UVLO RT/CLK SS/TRK INTSS PG Use an array of heat-sinking vias to connect the AGND pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be used to make connection to inner layer heat-spreading ground planes. It is recommended to use a via array as proposed in the picture above with via diameter of 300 μm (hole:100µm) thermal vias spaced 400µm. Ensure enough copper area is used for heat -sinking to keep the junction temperature below 125°C. 6: Isolate high noise areas Place a dedicated AGND copper area beneath the MagI³C Power Module.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module Determine power losses and thermal requirements of the board For example: VIN = 24𝑉, VOUT = 3.3𝑉, IOUT = 1.5𝐴, TAMB(MAX) = 85°C and TJ(MAX) = 125°C TAMB(MAX) is the maximum air temperature surrounding the module. TJ(MAX) is the maximum value of the junction temperature according to the “OPERATING CONDITIONS” limit. The goal of the calculation is to determine the characteristics of the re quired heat sink. In case of a surface mounted module this would be the PCB (number of layers, copper area and thickness). These characteristics are reflected in the value of the thermal resistance case to ambient: θCA. The basic formula for calculating the operating junction temperature TJ of a semiconductor device is as follows: TJ = PIC−Loss ∗ θJA + TAMB (14) PIC-LOSS are the total power losses within the module IC and are related to the operating conditions. θJA is the thermal resistance junction to ambient and calculated as: θJA = θJC + θCA (15) θJC is the thermal resistance junction to case. Combining equation (14) and (15) results in the maximum case-to-ambient thermal resistance: θCA(MAX) < TJ−MAX − TAMB(MAX) PIC−Loss − θJC (16) From section ”THERMAL SPECIFICATIONS“ use as typical thermal resistance from junction to case θJC = θJB = 6.8 °C/W. Use the 25°C power dissipation curves in the “TYPICAL PERFORMANCE CURVES“ section to estimate the P IC- LOSS for the application being designed. Add 20% losses to take into consideration the ambient temperature of 85°C.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module 06D Power Loss [W] Output Current [A] Power Loss: VIN = 24V @ TAMB = 25°C VOUT = 5.0V, fSW = 500 kHz VOUT = 3.3V, fSW = 400 kHz VOUT = 2.5V, fSW = 400 kHz VOUT = 12V, fSW = 800 kHz VOUT = 15V, fSW = 1000 kHz From the graph we read a power loss of 1.5W. Adding 20% results in a loss of 1.8W. En tering the values in formula (16) results in: θCA(MAX) < 125°C − 85°C θJA(MAX) = θJC + θCA(MAX) = 6.8°C/W + 15.42°C/W = 22.2°C/W To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will have a direct effect on the overall junction-to-ambient thermal resistance. For θJA < 22.2°C/W and only natural convection (i.e. no air flow) , the minimum PCB area should be slightly smaller than 60cm2. This corresponds to a square board with 7,6 cm x 7,6 cm copper area, 4 layers, and 35µm copper thickness. Higher copper thickness will further improve the overall thermal performance. Note that thermal vias should be placed under the IC package to easily transfer heat from the top layer of the PCB to the inner layers and the bottom layer.
conversion resumes, otherwise the inhibit cycle repeats. Figure 14. Overcurrent Limiting Figure 15. Over-Current Protection Circuit capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. resumes. Please note that an operation of the junction above 125°C is not recommended.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module
APPLICATIONS
Typical Application Circuit CIN2 EN/UVLO VIN RT/CLK PGND SS/TRK FB VOUT Module RSET CSS COUT1 AGND VIN VOUT SSCHO PG RUVLO1 RUVLO2 RRT CIN1 COUT2 Recommended component values specified at TA = 25°C VOUT 12V 5V 3.3V VIN 15V to 50V 8V to 50V 7V to 36V RSET 140kΩ 52.3kΩ 31.6kΩ RUVLO1 174kΩ 174kΩ 174kΩ RUVLO2 15.4kΩ 31.6kΩ 40.2kΩ RRT 267kΩ 1.1MΩ Open CIN1 min 2.2µF; 100V 2.2µF; 100V 4.7µF; 50V CIN2 2.2µF; 100V 2.2µF; 100V Open COUT1 min 47µF; 16V 47µF; 6.3V 47µF; 6.3V COUT2 47µF; 16V 47µF; 6.3V 47µF; 6.3V CSS 22nF Open Open
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module EVALUATION BOARD SCHEMATIC CIN1 EN/UVLO VIN RT/CLK PGND SS/TRK FB VOUT Module RSET CSS COUT1 AGND VIN VOUT SSCHO PG RRT CIN2 COUT3CIN3 COUT2 IC1 Cf Lf R1 R2 LED1 COUT4 RUVLO1 RUVLO2 RSYNC CSYNC EXT. CLOCK Optional input filter Bill of Material Designator Description Quantity Order Code Manufacturer IC1 MagI3C Power Module 1 171021501 Würth Elektronik CIN1 Aluminium Electrolythic capacitor 27µF/100V 1 860040874001 Würth Elektronik CIN2,CIN3 Ceramic chip capacitor 4,7µF/100V X5R 2 COUT1 Ceramic chip capacitor 100nF/100V X7R 0805 1 COUT2,COUT3 Ceramic chip capacitor 22µF/25V X7R 2 885012109014 Würth Elektronik COUT4 Aluminium Polymer Electrolythic capacitor 33µF/25V 1 875105545004 Würth Elektronik CSS, CSYNC Not mounted Cf (1) Filter ceramic chip capacitor 2.2µF/100V 1 Lf (2) Filter inductor 22µH, PD2 1 744774122 Würth Elektronik RUVLO1,RUVLO2, RSYNC Not mounted R1 12.4kΩ 1 R2 12.4kΩ 1 LED1 LED red 1 150080SS75000 Würth Elektronik RRT Set by jumper Open for fsw = 400kHz 1.1MΩ for fsw = 500kHz 1 549kΩ for fsw = 600kHz 1 365kΩ for fsw = 700kHz 1 267kΩ for fsw = 800kHz 1 215kΩ for fsw = 900kHz 1 178kΩ for fsw = 1MHz 1 RSET Set by jumper 21.5kΩ for VOUT = 2.5V 1 31.6kΩ for VOUT = 3.3V 1 52.3kΩ for VOUT = 5V 1 102kΩ for VOUT = 9V 1 140kΩ for VOUT = 12V 1 178kΩ for VOUT = 15V 1 (1) not mounted on the Evaluation Board (2) not mounted on the Evaluation Board. A shorting wire or 0R resistor is put in its place
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module HANDLING RECOMMENDATIONS 1. f SOLDER PROFILE 1. Only Pb-Free assembly is recommended according to JEDEC J-STD020. 2. Measure the peak reflow temperature of the MagI³C power module in the middle of the top view. 3. Ensure that the peak reflow temperature does not exceed 245°C ±5°C as per JEDEC J-STD020. 4. The reflow time period during peak temperature of 245°C ±5°C must not exceed 30 seconds. 5. Reflow time above liquidus (217°C) must not exceed 90 seconds. 6. Maximum ramp up is rate 3°C per second 7. Maximum ramp down rate is 3°C per second 8. Reflow time from room (25°C) to peak must not exceed 8 minutes as per JEDEC J-STD020. 9. Maximum numbers of reflow cycles is three. 10. For minimum risk, solder the module in the last reflow cycle of the PCB production. 11. For soldering process please consider lead material copper (Cu) and lead finish tin (Sn). 12. For solder paste use a standard SAC Alloy such as SAC 305, type 3 or higher. 13. Below profile is valid for convection reflow only 14. Other soldering methods (e.g.vapor phase) are not verified and have to be validated by the customer on his own risk Temperature [°C] Time [sec] 150 180 217 Max 250 Max 120 sec Min 60 sec Max 90 sec Min 30 sec Max 10 - 30 sec 245°C Ramp Up Rate Max 3°C/sec Ramp Down Rate Max 3°C/sec Max 3 solder cycles ! Preheat Liquidus Peak
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module PHYSICAL DIMENSIONS (mm) Package Type: BQFN-41 (9 x 11 x 2.8mm)
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module recommended soldering pad solder past recommendation 150 µm
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module PACKAGING Reel (mm) 20P
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module Tape (mm) 22P BQFN-41 11,359,35 ±0,1 ±0,1 ±0,05 0,30 ±0,1 3,10 ±0,05 1,55 ±0,10 Marking Marking Marking Marking Marking Marking
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module DOCUMENT HISTORY Revision Date Description Comment
1.0 May 2016 Release of final version
The following conditions apply to all goods within the product series of MagI³C of Würth Elektronik eiSos GmbH & Co. KG: General: All recommendations according to the general technical specifications of the data-sheet have to be complied with. The usage and operation of the product within ambient conditions which probably alloy or harm the component surface has to be avoided. The responsibility for the applicability of customer specific products and use in a particular customer design is always within the authority of the customer. All technical specifications for standard products do also apply for customer specific products. Residual washing varnish agent that is used during the production to clean the application might change the characteristics of the body, pins or termination. The washing varnish agent could have a negative effect on the long term function of the product. Direct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake or in the worst case it could break. As these devices are sensitive to electrostatic discharge customer shall follow proper IC Handling Procedures. Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of Würth Elektronik eiSos GmbH & Co. KG components in its applications, notwithstanding any applications -related information or support that may be provided by Würth Elektronik eiSos GmbH & Co. KG. Customer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Customer will fully indemnify Würth Elektronik eiSos and its representatives against any damages arising out of the use of any Würth Elektronik eiSos GmbH & Co. KG components in safety-critical applications. Product specific: Follow all instructions mentioned in the datasheet, especially: The solder profile has to comply with the technical reflow or wave soldering specification, otherwise this will void the warranty. All products are supposed to be used before the end of the period of 12 months based on the product date-code. Violation of the technical product specifications such as exceeding the absolute maximum ratings will void the warranty. It is also recommended to return the body to the original moisture proof bag and reseal the moisture proof bag again. ESD prevention methods need to be followed for manual handling and processing by machinery.
we-online.com © May 2016 Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0 WPMDU1251501 / 171021501 MagI³C Power Module VDRM - Variable Step Down Regulator Module IMPORTANT NOTES The following conditions apply to all goods within the product range of Würth Elektronik eiSos GmbH & Co. KG: 1. General Customer Responsibility Some goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding general suitability for certain application areas. These statements about sui tability are based on our knowledge and experience of typical requirements concerning the areas, serve as general guidance and cannot be estimated as binding statements about the suitability for a customer application. The responsibility for the applicabil ity and use in a particular customer design is always solely within the authority of the customer. Due to this fact it is up to the customer to evaluate, where appropriate to investigate and decide whether the device with the specific product characteristics described in the product specification is valid and suitable for the respective customer application or not. Accordingly, the customer is cautioned to verify that the datasheet is current before placing orders. 2. Customer Responsibility related to Specific, in particular Safety-Relevant Applications It has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the usual lifetime cannot be completely eliminated in the current state of the a rt, even if the products are operated within the range of the specifications. In certain customer applications requiring a very high level of safety and especially in customer applications in which the malfunction or failure of an electronic component coul d endanger human life or health it must be ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is caused to third parties in the event of malfunction or failure of an electronic component. 3. Best Care and Attention Any product-specific notes, warnings and cautions must be strictly observed. 4. Customer Support for Product Specifications Some products within the product range may contain substances which are subject to restrictions in certain jurisdictions in order to serve specific technical requirements. Necessary information is available on request. In this case the field sales engineer or the internal sales person in charge should be contacted who will be happy to support in this matter. 5. Product R&D Due to constant product improvement product specifications may change from time to time. As a standard reporting procedure of the Product Change Notification (PCN) according to the JEDEC -Standard we inform about minor and major changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge should be contacted. The basic responsibility of the customer as per Section 1 and 2 remains unaffected. 6. Product Life Cycle Due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of products. As a standard reporting procedure of the Product Termination Notification (PTN) according to the JEDEC - Standard we will inform at an early stage about inevitable product discontinuance. According to this we cannot guarantee that all products within our product range will always be available. Therefore it needs to be verified with the field sales engineer or the internal sales person in charge about the current product availability expectancy before or when the product for application design -in disposal is considered. The approach named above does not apply in the case of individual agreements deviating from the foregoing for customer-specific products. 7. Property Rights All the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas, development contracts as well as models or templates that are subject to copyright, patent or commercial protection supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG. Würth Elektronik eiSos GmbH & Co. KG does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright, mask work right, o r other intellectual property right relating to any combination, application, or process in which Würth Elektronik eiSos GmbH & Co. KG components or services are used. 8. General Terms and Conditions Unless otherwise agreed in individual contracts, all or ders are subject to the current version of the “Genera l Terms and Conditions of Würth Elektronik eiSos Group”, last version available at www.we-online.com.