TL16C552 TI
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Technical content
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068IBM PC/AT Compatible /C0068Two TL16C550 ACEs /C0068Enhanced Bidirectional Printer Port /C006816-Byte FIFOs Reduce CPU Interrupts /C0068Independent Control of Transmit, Receive, Line Status, and Data Set Interrupts on Each Channel /C0068Individual Modem Control Signals for Each Channel /C0068Programmable Serial Interface Characteristics for Each Channel: – 5-, 6-, 7-, or 8-bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation /C00683-State TTL Drive for the Data and Control Bus on Each Channel /C0068Hardware and Software Compatible With TL16C452
description
(TOP VIEW) ACK PE 87 6 5493 GND RI1 DSR1 CLK CS1 TRI PEMD IOW IOR CS2 RESET DCD0 RI0 DSR0 CS0 16 8 6 72 35 36 37 38 39 66 65 GND CTS0 BUSY SLCT 64 63 62 61 40 41 42 43 SIN0 TXRDY1 ENIRQ ERR SIN1 RXRDY1 RXRDY0 DCD1 VDD VDD The TL16C552 is an enhanced dual channel version of the popular TL16C550 asynchronous communications element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Instruments Incorporated IBM PC/AT is a trademark of International Business Machines Corporation.
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description (continued) received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the transfer operations being performed and the error conditions. In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports. A programmable baud rate generator is included that can divide the timing reference clock input by a divisor between 1 and (2 16 – 1). The TL16C552 is housed in a 68-pin plastic leaded chip carrier. functional block diagram CTS0 DSR0 DCD0 RI0 SIN0 CS0 DB–DB7 RTS0 DTR0 SOUT0 INT0 RXRDY0 TXRDY0 RTS1 DTR1 SOUT1 INT1 RXRDY1 TXRDY1 BDO 53–46 CTS1 DSR1 DCD1 RI1 SIN1 CS1 14–21 8 A0–A2 IOW IOR RESET CLK ERR SLCT BUSY PE ACK PEMD CS2 ENIRQ
8 PD0–PD7
35–33
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION ACK 68 I Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place. It generates a printer port interrupt during its positive transition. AFD 56 I/O Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal when continuous form paper is to be autofed to the printer. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ . A0, A1, A2 35, 34, 33 I Address lines A0–A2. A0, A1, and A2 select the internal registers during CPU bus operations. See Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port. BDO 44 O Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the parallel port is read. This output can control the system bus driver (74LS245). BUSY 66 I Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready to accept data. CLK 4 I Clock input. CLK is an external clock input to the baud rate divisor of each ACE. CS0 , CS1, CS2 32, 3, 38 I Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port. CTS0 , CTS1 28, 13 I Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change of state in either CTS terminal, since the previous reading of the associated modem status register, causes the setting of delta clear to send (ΔCTS) bit (MSR0) of each modem status register. DB0 – DB7 14 – 21 I/O Data bits DB0 – DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control, and status information between the TL16C552 and the CPU. These lines are normally in a high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the first serial data bit to be received or transmitted. DCD0 , DCD1 29, 8 I Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or ΔDCD) bit of the modem status register indicates whether the DCD input has changed states since the previous reading of the modem status register. DCD has no affect on the receiver. DSR0 , DSR1 31, 5 I Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated modem status register. The MSR1 (delta data set ready or ΔDSR) bit indicates whether the associated DSR terminal has changed states since the previous reading of the modem status register. DTR0 , DTR1 25, 11 O Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0) or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready to receive data. ENIRQ 43 I Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status register. INT2 is latched high on rising edge of ACK. ERR 63 I Line printer error. ERR is an input line from the printer. The printer reports an error by holding this line low during the error condition. GND 7, 27, 54 Ground (0 V). All terminals must be tied to ground for proper operation. INIT 57 I/O Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal, which allows the printer initialization routine to be started. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ . IOR 37 I Input/output read strobe. IOR is an active-low input that enables the selected channel to output data to the data bus (DB0–DB7). The data output depends upon the register selected by the address inputs A0, A1, A2, and chip select. Chip select 0 (CS0 ) selects ACE #1, chip select 1 (CS1) selects ACE #2, and chip select 2 (CS2) selects the printer port. IOW 36 I Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to either ACE or to the parallel port. The destination depends upon the register selected by the address inputs A0, A1, A2, and chip selects CS0 , CS1, and CS2.
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Terminal Functions (continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION INT0, INT1 45, 60 O Serial channel interrupts. INT0 and INT1 are 3-state serial channel interrupt outputs (enabled by bit 3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition and is enabled by the interrupt enable register of its associated channel: receiver error flag, received data available, transmitter holding register empty, and modem status. The interrupt is cleared upon appropriate service. When reset, the interrupt output is in the high-impedance state. INT2 59 O Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK. It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output is in the high-impedance state. Its mode is also controlled by ENIRQ PD0–PD7 53–46 I/O Parallel data bits (0–7). These eight lines (PD0–PD7) provide a byte wide input or output port to the system. PE 67 I Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of paper. PEMD 1 I Printer enhancement mode. When low, PEMD enables the write data register to the PD0–PD7 lines. A high on this signal allows direction control of the PD0–PD7 port by the DIR bit in the control register. PEMD is usually tied low for the printer operation. RESET 39 I Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are suspended. The modem control register along with its associated outputs are cleared. The line status register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain in an idle state until programmed to resume serial data activities. This input has a hysteresis level of typically 400 mV. RTS0 , RTS1 24, 12 O Request to send outputs. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control register. Both RTSx terminals are set by RESET. A low on the RTSx terminal indicates that its ACE has data ready to transmit. In half-duplex operations, RTSx controls the direction of the line. RXRDY0, RXRDY1 9, 61 O Receiver ready. RXRDY0 and RXRDY1 are receiver direct memory access (DMA) signaling terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3) when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450 mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple transfers that are made continuously until the receiver FIFO has been emptied are supported by mode 1. Mode 0. RXRDYx is active (low) when in the FIFO mode (FCR0=1, FCR3=0) or when in the TL16C450 mode (FCR0=0) and the receiver FIFO or receiver holding register contain at least one character. When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx terminal goes inactive (high). Mode 1. RXRDYx goes active (low) in the FIFO mode (FCR0=1) when FCR3=1 and the time-out or trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is empty. RI0, RI1 30, 6 I Ring indicator inputs. RI0 and RI1 are modem control inputs. Their condition is tested by reading MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or MSR2) that indicates whether either input has changed states from high to low since the previous reading of the modem status register. SIN0, SIN1 41, 62 I Serial data inputs. SIN0 and SIN1 are serial data inputs that move information from the communication line or modem to the TL16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is low state. Data on the serial data inputs is disabled when operating in the loop mode. SLCT 65 I Printer selected. SLCT is an input line from the printer that goes high when the printer has been selected. SLIN 58 I/O Line printer select. SLIN is an open-drain input that selects the printer when it is active (low). This terminal has an internal pullup resistor to VDD of approximately 10 kΩ . SOUT0, SOUT1 26, 10 O Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry. A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the transmitter is disabled, when RESET is true (low), when the transmitter register is empty, or when in the loop mode.
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION STB 55 I/O Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the printer. When it is active (low), it provides the printer with a signal to latch the data currently on the parallel port. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ . TRI 2 I 3-state control. TRI controls the 3-state control of all I/O and output terminals. When TRI is asserted, all I/O and outputs become high impedance, allowing board level testers to drive the outputs without overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down with an internal resistor that is approximately 5 kΩ . TXRDY0 , TXRDY1 22, 42 O Transmitter ready. TXRDY0 and TXRDY1 are transmitter ready signals. Two types of DMA signaling are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the transmitter FIFO has been filled are supported by mode 1. Mode 0. When in the FIFO mode (FCR0=1, FCR3=0) or in the TL16C450 mode (FCR0=0) and there are no characters in the transmitter holding register or transmitter FIFO, TXRDY are active (low). Once TXRDY is activated (low), it goes inactive after the first character is loaded into the holding register of transmitter FIFO. Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCR0=1) when FCR3=1 and there are no characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDYx goes inactive (high). VDD 23, 40, 64 Power supply. VDD is the power supply requirement is 5 V ± 5%. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage levels are with respect to ground (VSS ). recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 4.75 5 5.25 V Clock high-level input voltage, VIH(CLK) 2 VDD V Clock low-level input voltage, VIL(CLK) –0.5 0.8 V High-level input voltage, VIH 2 VDD V Low-level input voltage, VIL –0.5 0.8 V Clock frequency, fclock 8 MHz Operating free-air temperature range, TA 0 70 °C
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
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electrical characteristics over recommended ranges of operating free-air temperature and supply voltage PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = –0.4 mA for DB0–DB7, IOH = –2 mA for PD0–PD7, IOH = –0.4 mA for INIT, AFD, STB, and SLIN (see Note 2), IOH = –0.4 mA for all other outputs 2.4 V VOL Low-level output voltage IOL = 4 mA for DB0–DB7, IOL = 12 mA for PD0–PD7, IOL = 10 mA for INIT, AFD, STB, and SLIN (see Note 2), IOL = 2 mA for all other outputs 0.4 V II Input current VDD = 5.25 V, All other terminals are floating ± 10 µA II(CLK) Clock input current VI = 0 to 5.25 V ± 10 µA VDD =52 5V V O = 0 with chip deselected orIOZ High-impedance output current VDD = 5.25 V, VO = 0 with chi deselected, or VO 5 25 V with chip and write mode selected ± 20 µAIOZ High im edance out ut current VO = 5.25 V with chip and write mode selected ± 20 µA VDD = 5.25 V, No loads on outputs, IDD Supply current DD ,, SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1, 50 mAIDD Supply current RI0 and RI1 at 2 V, Other inputs at 0.8 V, 50 mA Baud rate generator fclock = 8 MHz, Baud rate = 56 kbit/s NOTE 2: These four terminals contain an internal pullup resistor to VDD of approximately 10 kΩ . clock timing requirements over recommended ranges of operating free-air temperature and supply voltage MIN MAX UNIT tw1 Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1) 55 ns tw2 Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1) 55 ns tw3 Pulse duration, master (RESET) low (see Figure 16) 1000 ns read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 4) MIN MAX UNIT tw4 Pulse duration, IOR low 80 ns tsu1 Setup time, chip select valid before IOR low (see Note 3) 15 ns tsu2 Setup time, A2–A0 valid before IOR low (see Note 3) 15 ns th1 Hold time, A2–A0 valid after IOR high (see Note 3) 20 ns th2 Hold time, chip select valid after IOR high (see Note 3) 20 ns td1 Delay time, tsu2 + tw4 + td2 (see Note 4) 175 ns td2 Delay time, IOR high to IOR or IOW low 80 ns NOTES: 3. The internal address strobe is always active. 4. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 5) MIN MAX UNIT tw5 Pulse duration, IOW low 80 ns tsu4 Setup time, chip select valid before IOW low (see Note 3) 15 ns tsu5 Setup time, A2–A0 valid before IOW low (see Note 3) 15 ns tsu6 Setup time, D0–D7 valid before IOW high 15 ns th3 Hold time, A2–A0 valid after IOW high (see Note 3) 20 ns th4 Hold time, chip select valid after IOW high (see Note 3) 20 ns th5 Hold time, D0–D7 valid after IOW high 15 ns td3 Delay time, tsu5 + tw5 + td4 175 ns td4 Delay time, IOW high to IOW or IOR low 80 ns NOTE 3: The internal address strobe is always active. read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 4) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 Propagation delay time from IOR high to BDO high or from IOR low to BDO low C L = 100 pF,See Note 5 60 ns ten Enable time from IOR low to D0–D7 valid C L = 100 pF,See Note 5 60 ns tdis Disable time from IOR high to D0–D7 released C L = 100 pF,See Note 5 0 60 ns NOTE 5: V OL and VOH (and the external loading) determine the charge and discharge time. transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, interrupt THRE low to SOUT low at start 8 24 RCLK cycles td6 Delay time, SOUT low at start to interrupt THRE high See Note 6 8 8 RCLK cycles td7 Delay time, IOW (WR THR) high to interrupt THRE high See Note 6 16 32 RCLK cycles td8 Delay time, SOUT low at start to TXRDY low C L = 100 pF 8 RCLK cycles tpd2 Propagation delay time from IOW (WR THR) low to interrupt THRE low C L = 100 pF 140 ns tpd3 Propagation delay time from IOR (RD IIR) high to interrupt THRE low C L = 100 pF 140 ns tpd4 Propagation delay time from IOW (WR THR) high to TXRDY high C L = 100 pF 195 ns NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time.
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receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9, 10, 11, 12 and 13) PARAMETER TEST CONDITIONS MIN MAX UNIT td9 Delay time from stop to INT high See Note 7 1 RCLK cycle tpd5 Propagation delay time from RCLK high to sample CLK high 100 ns tpd6 Propagation delay time from IOR (RD RBR/RD LSR) high to reset interrupt lowC L = 100 pF 150 ns tpd7 Propagation delay time from IOR (RD RBR) low to RXRDY high 150 ns NOTE 7: The receiver data available indication, the overrun error indication, the trigger level interrupts and the active RXRDY indication is delayed three RCLK cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) is delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RCLK cycle delays for trigger change level interrupts. modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 14) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd8 Propagation delay time from IOW (WR MCR) high to RTS (DTR) low/high C L = 100 pF 100 ns tpd9 Propagation delay time from modem input (CTS, DSR) low/high to interrupt highC L = 100 pF 170 ns tpd10 Propagation delay time from IOR (RD MSR) high to interrupt low C L = 100 pF 140 ns tpd11 Propagation delay time from RI high to interrupt high C L = 100 pF 170 ns parallel port timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 15) MIN MAX UNIT tsu7 Setup time, data valid before STB low 1 µs th6 Hold time, data valid after STB high 1 µs tw6 Pulse duration, STB low 1 500 µs td10 Delay time, BUSY high to ACK low Defined by printer td11 Delay time, BUSY low to ACK low Defined by printer tw6 Pulse duration, ACK low Defined by printer tw7 Pulse duration, BUSY high Defined by printer td12 Delay time, BUSY high after STB high Defined by printer
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Figure 4. Read Cycle Timing Waveforms Figure 5. Write Cycle Timing Waveforms
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Figure 9. Receiver Timing Waveforms Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
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NOTES: A. This is the reading of the last byte in the FIFO. Figure 13. Receiver Ready Mode 1 Waveforms
1 INT, 2 INT
Figure 14. Modem Control Timing Waveforms
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Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic abbreviations are shown in the Table 1 for the registers. Table 1. Internal Register Types With Mnemonics (bit 7) to select the register to be written to or read from (see Table 2). Table 2. Register Selection†‡ ‡ The serial channel is accessed when either CS0 or CS1 is low. Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
of these registers follow Table 3. Table 3. Summary of Accessible Registers
0 RBR Data Data Data Data Data Data Data Data
0 THR Data Data Data Data Data Data Data Data
1 IER 0 0 0 0 (EDSSI ) (ERLSI) (ETBEI) (ERBFI )1 IER 0 0 0 0 (EDSSI)
2 FCR Receiver Receiver Reserved Reserved DMA Tranmitter Receiver FIFO
2 IIR FIFOs FIFOs 0 0 Interrupt ID Interrupt ID Interrupt ID 0 If
3 LCR (DLAB) Set Stick (EPS) (PEN) (STB) (WLSB1) (WLSB0)()
4 MCR 0 0 0 Loop Enable
5 LSR Error in (TEMT) (THRE) (BI) (FE) (PE) (OE) (DR)
6 MSR (DCD) (RI) (DSR) (CTS) (ΔDCD) (TERI) (ΔDSR) (ΔCTS)()
7 SCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
‡ These bits are always 0 when FIFOs are disabled.
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the following bulleted list. TL16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCR0=1. /C0068Bit 3: FCR3=1 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCR0=1. /C0068Bits 4 and 5: These two bits are reserved for future use. /C0068Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt as shown in Table 4. Table 4. Receiver FIFO Trigger Level
- LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
- IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt IIR = 04.
- Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
- IIR = 04 (receive data available indication) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. A FIFO timeout interrupt occurs when the following conditions exist: a. Minimum of one character in FIFO b. Last received serial character was longer than four continuous previous character times ago (if two stop bits are programmed, the second one is included in the time delay). c. The last CPU read of the FIFO was more than four continuous character times earlier. At 300 baud and 12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received character to interrupt issued.1 2. By using the RCLK input for a clock signal, the character times can be calculated. (The delay is proportional to the baud rate.) 3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received, when there has been no time-out interrupt. 4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO. Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled (FCRO = 1, IER = 1). 1. When the transmitter FIFO is empty, the THR interrupt (IIR = 02) occurs. The interrupt is cleared as soon as the THR is written to or the IIR is read. One to sixteen characters can be written to the transmit FIFO when servicing this interrupt. 2. The transmitter FIFO empty indications are delayed one character time minus the last stop bit time whenever the following occurs: THRE = 1 and there has not been a minimum of two bytes at the same time in transmitter FIFO, since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is enabled. Receiver FIFO trigger level and character time-out interrupts have the same priority as the received data available interrupt. The THRE interrupt has the same priority as the transmitter FIFO empty interrupt. FIFO polled mode operation Clearing IER0, IER1, IER2, IER3, or all, with FCR0 = 1, puts the ACE into the FIFO polled mode. Receiver and transmitter are controlled separately. Therefore, either or both can be in the polled mode. In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE status. interrupt enable register (IER) The IER independently enables the four serial channel interrupt sources that activate the interrupt (INT0 or INT1) output. All interrupts are disabled by clearing IER0 – IER3. Interrupts are enabled by setting the appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output. All other system functions operate in their normal manner, including the setting of the LSR and MSR. The contents of the IER are described in Table 3 and in the following bulleted list. /C0068Bit 0: IER0, when set, enables the received data available interrupt and the time-out interrupts in the FIFO mode.
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/C0068Bit 1: IER1, when set, enables the THRE interrupt. /C0068Bit 2: IER2, when set, enables the receiver line status interrupt. /C0068Bit 3: IER3, when set, enables the modem status interrupt. /C0068Bits 4 – 7: IER4 – IER7 are always cleared. indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5. Table 5. Interrupt Control Functions /C0068Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending. /C0068Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5. mode and a trigger change level interrupt is pending. /C0068Bits 4 and 5: IIR4 and IIR5 are always cleared. /C0068Bits 6 and 7: IIR6 and IIR7 are set when FCR0=1.
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION line control register (LCR) The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described in the following bulleted list and shown in Figure 17. /C0068Bits 0 and 1: LCR0 and LCR1 are the word length select bits. The number of bits in each serial character is programmed as shown in Figure 17. /C0068Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character as shown in Figure 17. The receiver always checks for one stop bit. /C0068Bit 3: LCR3 is the parity enable bit 3. When LCR3 is high, a parity bit between the last data word bit and stop bit is generated and checked. /C0068Bit 4: LCR4 is the even parity select bit 4. When enabled, setting this bit selects even parity. /C0068Bit 5: LCR5 is the stick parity bit 5. When parity is enabled (LCR3=1), LCR5=1 causes the transmission and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity to a known state and allows the receiver to check the parity bit in a known state. /C0068Bit 6: LCR6 is the break control bit 6. When LCR6 is set, the serial output (SOUT1 and SOUT0) is forced to the spacing state (low). The break control bit acts only on the serial output and does not affect the transmitter logic. When the following sequence is used, no invalid characters are transmitted because of the break: Step 1. Load a zero byte in response to the transmitter holding register empty (THRE) status indication. Step 2. Set the break in response to the next THRE status indication. Step 3. Wait for the transmitter to be idle when transmitter empty status signal is set high (TEMT=1). Then clear the break when the normal transmission has to be restored. /C0068Bit 7: LCR7 is the divisor latch access bit (DLAB) bit 7. Bit 7 must be set to access the divisor latches DLL and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the receiver buffer register, the transmitter holding register or the interrupt enable register.
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2 Stop Bits if 6, 7, 8 Data Bits Selected
Figure 17. Line Control Register Contents enhancement is the addition of a direction control bit, and an interrupt status bit. data direction control bits. port. Write operations immediately output data to the PD0–PD7 terminals. direction bit is cleared to write.
Table 6. Extended Mode and Direction Control Bit Combinations printer being disconnected from the port. Table 7. LPS Register Bit Description
0 Reserved 1
1 Reserved 1
2 PRINT 1
3 ERR †
4 SLCT †
5 PE †
6 ACK †
7 BSY †
† Outputs are dependent upon device inputs. /C0068Bits 0 and 1: These bits are reserved and are always set. /C0068Bit 3: This bit is the error (ERR, active low) status bit corresponds to ERR input. /C0068Bit 4: This bit is the select (SLCT) status bit corresponds to SLCT input. /C0068Bit 5: This bit is the paper empty (PE) status bit corresponds to PE input. /C0068Bit 6: This bit is the acknowledge (ACK, active low) status bit corresponds to ACK input. /C0068Bit 7: This bit is the busy (BSY, active low) status bit corresponds to BUSY input (active high). operations set or clear these bits, while read operations return the state of the last write operation to this register. The bits in this register are described in Table 8. PS/2 is a trademark of International Business Machines Corporation.
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Table 8. LPC Register Bit Description
0 STB
1 AFD
2 INIT
3 SLIN
4 INT2 EN
5 DIR
6 Reserved (0)
7 Reserved (0)
LPT interface. When STB is cleared, the signal is negated. interface. When AFD is cleared, the signal is negated. INIT is cleared, the INIT signal is asserted on the LPT interface. LPT interface. when SLIN is cleared, the signal is negated. buffers in the LPD port are disabled allowing data driven from external sources to be read from the LPD port. When DIR is cleared, the LPD port is in output mode. the following bulleted list. Table 9. Line Status Register Bits † LSR is intended only for factory test. It should be considered as read only by applications software.
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION line status register (LSR) (continued) /C0068Bit 0: LSR0 is the data ready (DR) bit. DR is set high when an incoming character has been received and transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the receiver buffer register or the FIFO. /C0068Bit 1: SR1 is the overrun error (OE) bit. OE indicates that data in the receiver buffer register was not read by the CPU before the next character was transferred into the receiver buffer register overwriting the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An OE occurs in the FIFO mode after the FIFO is full and the next character is completely received. The OE is detected by the CPU on the first LSR read after the overrun happens. The character in the shift register is not transferred to the FIFO but it is overwritten. /C0068Bit 2: LSR2 is the parity error (PE) bit. PE indicates that the received data character does not have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO. /C0068Bit 3: LSR3 is the framing error (FE) bit. FE indicates that the received character did not have a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when the character is at the top of the FIFO. /C0068Bit 4: LSR4 is the break interrupt (BI) bit. BI is set when the received data input is held in the spacing (cleared) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the first LSR read. Only one zero character is loaded into the FIFO when BI occurs. LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting IER2=1 in the interrupt enable register. /C0068Bit 5: LSR5 is the THRE bit. THRE indicates that the ACE is ready to accept a new character for transmission. The THRE bit is set when a character is transferred from the transmitter holding register (THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading of the transmitter holding register by the CPU. LSR5 is not reset by a CPU read of the LSR. In the FIFO mode when the transmitter FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. When THRE is the interrupt source indicated in IIR, INTRPT is cleared by a read of the IIR. /C0068Bit 6: LSR6 is the transmitter empty (TEMT) bit. TEMT is set when the THR and the TSR are both empty. LSR6 is cleared when a character is loaded into the THR and remains low until the character is transferred out of SOUT. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the transmitter FIFO and shift register are empty, this bit is set. /C0068Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in the TL16C450 mode. In FIFO mode, it is set when at least one of the following data errors is in the FIFO: PE, FE, or BI indication. It is cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.
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- It initializes the transmitter and receiver clock counters.
- It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared. All of the discrete
turned off. The LCR, divisor latches, RBR, and transmitter buffer register are not effected. high), the ACE remains in the idle mode until programmed. enabled, an interrupt occurs due to THRE. A summary of the affect of a reset on the ACE is given in Table 10. Table 10. RESET Affects On Registers and Signals
Figure 18. Modem Control Register Contents proper polarity input at the modem or data set. polarity input at the modem or data set. /C0068Bit 2: When MCR2 is set, OUT1 is forced low. /C0068Bit 3: When MCR3 is set, the OUT2 output is forced low. fully operational. However, interrupts are generated by controlling the lower four MCR bits internally. Interrupts are not generated by activity on the external terminals represented by those four bits. /C0068Bits 5 – 7: These three bits(MCR5 – MCR7) are permanently cleared.
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changes state and cleared when the CPU reads the MSR. is set. The MSR is a priority 4 interrupt. The contents of the MSR are described in Table 11. Table 11. Modem Status Register Bits has changed state since it was last read by the CPU. has changed state since the last time it was read by the CPU. transitions on RI do not activate TERI. channel has changed state since the last time it was read by the CPU. is in the loop mode ((MCR4 = 1), MSR4 reflects the value of RTS in the MCR. loop mode (MCR4=1), MSR6 reflects the value of OUT1 in the MCR. input. When the channel is in the loop mode (MCR4=1), MSR7 reflects the value of OUT2 in the MCR.
Reading the MSR register clears the delta modem status indications but has no affect on the other status bits. operation, the status bit is not set until the trailing edge of the read. still be generated by writing to MCR3 – MCR0. Applications software should not write to the MSR. shown. The read data register allows the microprocessor to read the information on the parallel bus. parallel port implementation used in the IBM serial parallel adaptor. Table 12. Parallel Port Registers Table 13. Parallel Port Register Select
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Table 14. Baud Rates Using a 1.8432-MHz Crystal Table 15. Baud Rates Using a 3.072-MHz Crystal
Table 16. Baud Rates Using a 8.192-MHz Crystal The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR. These control words define the character length, number of stop bits, parity, baud rate, and modem interface. time the ACE serial channel is not transmitting or receiving data. receiver from assembling a false data character due to a low-going noise spike on the SIN input. a FE indication is set in LSR3.
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
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The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended to be used by the programmer to temporarily hold data.
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