TL16C550A TI
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Technical content
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Capable of Running With All Existing TL16C450 Software /C0068After Reset, All Registers Are Identical to the TL16C450 Register Set /C0068In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU /C0068In the TL16C450 Mode, Holding and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data /C0068Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 –1) and Generates an Internal 16× Clock /C0068Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream /C0068Independent Receiver Clock Input /C0068Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled /C0068Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s) /C0068False-Start Bit Detection /C0068Complete Status Reporting Capabilities /C00683-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus /C0068Line Break Generation and Detection /C0068Internal Diagnostic Capabilities: – Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, Framing Error Simulation /C0068Fully Prioritized Interrupt System Controls /C0068Modem Control Functions (CTS, RTS, DSR, DTR , RI, and DCD) /C0068Faster Plug-In Replacement for National Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode†), the TL16C550A can be placed in an alternate mode (FIFO) to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers. The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered. The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (2 16 –1) and producing a 16× clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link. † The TL16C550A can also be reset to the TL16C450 mode under software control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Instruments Incorporated
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(TOP VIEW) MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY AS 18 19 RCLK SIN NC SOUT CS0 CS1 CS2 BAUDOUT 20 21 22 23 FN PACKAGE (TOP VIEW) RI DCD DSR CTS 54 3 2164 4 NC V RD2 DDIS TXRDY ADS XIN XOUT WR1 WR2 NC RD1 42 41 4043 24 25 26 27 28 NC–No internal connection CC VSS
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 block diagram Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Modem Status Register Receiver Buffer Register Line Control Register Receiver Timing and Control Line Control Register Transmitter FIFO S e l e c t Line Control Register Modem Control Logic Interrupt Enable Register Interrupt I/O Register FIFO Control Register Select and Control Logic Power Supply Interrupt Control Logic S e l e c t Line Control Register BAUDOUT SIN RCLK SOUT RTS CTS DTR DSR DCD RI OUT1 OUT2 INTRPT CS0 CS1 CS2 ADS MR RD1 RD2 WR1 WR2 DDIS TXRDY XIN XOUT RXRDY D7–D0 8–1 Internal Data Bus VCC VSS NOTE A: Terminal numbers shown are for the N package.
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NAME NO.† I/O DESCRIPTION 28 [31] 27 [30] 26 [29] I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS ) signal description. ADS 25 [28] I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in the state they were in when the low-to-high transition of ADS occurred. BAUDOUT 15 [17] O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input. CS0 CS1 CS2 12 [14] 13 [15] 14 [16] I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description. CTS 36 [40] I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an interrupt is generated. D0 – D7 1 – 8 [2 – 9] I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the ACE and the CPU. DCD 38 [42] I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes state, an interrupt is generated. DDIS 23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable an external transceiver. DSR 37 [41] I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state, an interrupt is generated. DTR 33 [37] O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level. DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing bit 0 (DTR) of the modem control register. INTRPT 30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer to Table 2. OUT1 OUT2 34 [38] 31 [35] O Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the modem control register. RCLK 9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1 RD2 21 [24] 22 [25] I Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1 tied high). † Terminal numbers shown in brackets are for the FN package.
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (continued) TERMINAL I/O DESCRIPTION NAME NO.† I/O DESCRIPTION RI 39 [43] I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RTS 32 [36] O Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register. RXRDY 29 [32] O Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high). SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device. SOUT 11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the marking (high) state as a result of master reset. TXRDY 24 [27] O Transmitter ready output. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. VCC 40 [44] 5-V supply voltage VSS 20 [22] Supply common WR1 WR2 18 [20] 19 [21] I Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1 tied high). XIN XOUT 16 [18] 17 [19] I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal). † Terminal numbers shown in brackets are for the FN package.
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absolute maximum ratings over free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 VCC V Low-level input voltage, VIL –0.5 0.8 V Operating free-air temperature, TA 0 70 °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH ‡ High-level output voltage IOH = –1 mA 2.4 V VOL ‡ Low-level output voltage IOL = 1.6 mA 0.4 V Ilkg Input leakage current VCC = 5.25 V, VSS = 0, ± 10 µAIlkg In ut leakage current CC VI = 0 to 5.25 V, SS All other terminals floating ± 10 µA VCC =52 5V V SS =0 IOZ High-impedance output current VCC = 5.25 V, VSS = 0 VO =0t o52 5V ± 20 µAIOZ High-im edance out ut current VO = 0 to 5.25 V, Chip selected in write mode or chip deselected ± 20 µA Chip selected in write mode or chip deselected VCC =52 5V T A =2 5°CVCC = 5.25 V, TA = 25 C , SIN DSR DCD CTS dR I t2VICC Supply current SIN, DSR , DCD , CTS , and RI at 2 V, 10 mAICC Su ly current ,,,, , All other inputs at 0 8 V XTAL1 at 4 MHz 10 mAAll other in uts at 0.8 V, XTAL1 at 4 MHz , No load on outputs Baud rate 50 kbit/sN o load on outputs, Baud rate = 50 kbit/s C XIN Clock input capacitance V0 V0 15 20 pF C XOUT Clock output capacitance VCC = 0, V SS = 0, All other terminals grounded 20 30 pF C i Input capacitance All other terminals grounded, f = 1 MHz, TA = 25°C 6 10 pF C o Output capacitance f = 1 MHz , TA = 25 C 10 20 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ These parameters apply for all outputs except XOUT.
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system timing requirements over recommended ranges of supply voltage and operating free-air temperature ALT. SYMBOL FIGURE MIN MAX UNIT tcR Cycle time, read (tw7 + td8 + td9) RC 175 ns tcW Cycle time, write (tw6 + td5 + td6) WC 175 ns tw5 Pulse duration, ADS low tADS 2, 3 15 ns tw6 Pulse duration, write strobe tWR 2 80 ns tw7 Pulse duration, read strobe tRD 3 80 ns tw8 Pulse duration, master reset tMR 1 µs tsu1 Setup time, address valid before ADS↑ tAS 2, 3 15 ns tsu2 Setup time, CS before ADS↑ tCS 2, 3 15 ns tsu3 Setup time, data valid before WR1↓ or WR2↑ tDS 2 15 ns th1 Hold time, address low after ADS↑ tAH 2, 3 0 ns th2 Hold time, CS valid after ADS↑ tCH 2, 3 0 ns th3 Hold time, CS valid after WR1↑ or WR2↓ tWCS 2 20 ns th4§ Hold time, address valid after WR1↑ or WR2↓ tWA 2 20 ns th5 Hold time, data valid after WR1↑ or WR2↓ tDH 2 15 ns th6 Hold time, CS valid after RD1↑ /C0111/C0114RD2 ↓ tRCS 3 20 ns th7§ Hold time, address valid after RD1↑ or RD2↓ tRA 3 20 ns td4§ Delay time, CS valid before WR1↓ or WR2↑ tCSW 2 15 ns td5§ Delay time, address valid before WR1↓ or WR2↑ tAW 2 15 ns td6§ Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ tWC 2 80 ns td7§ Delay time, CS valid to RD1↓ /C0111/C0114 /C0082/C0068/C0050↑ tCSR 3 15 ns td8§ Delay time, address valid to RD1↓ or RD2↑ tAR 3 15 ns td9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 80 ns § Applicable only when ADS is tied low. system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw1 Pulse duration, clock high tXH 1 f = 9 MHz maximum 50 ns tw2 Pulse duration, clock low tXL 1 f = 9 MHz maximum 50 ns td10 Delay time, RD1↓ or RD2↑ to data valid tRVD 3 C L = 100 pF 60 ns td11 Delay time, RD1↑ or RD2↓ to floating data tHZ 3 C L = 100 pF 0 60 ns tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ tRDD 3 C L = 100 pF 60 ns NOTE 2: Charge and discharge time is determined by VOL , VOH , and external loading. baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw3 Pulse duration, BAUDOUT low tLW 1 f = 9 MHz, CLK ÷ 2, C L = 100 pF 80 ns tw4 Pulse duration, BAUDOUT high tHW 1 f = 9 MHz, CLK ÷ 2, C L = 100 pF 100 ns td1 Delay time, XIN↑ to BAUDOUT ↑ tBLD 1 C L = 100 pF 125 ns td2 Delay time, XIN↑↓ to BAUDOUT ↓ tBHD 1 C L = 100 pF 125 ns
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receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 3) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td12 Delay time, RCLK to sample clock tSCD 4 100 ns td13 Delay time, stop to set RCV error interrupt or read RBR to LSI interrupt or stop to RXRDY tSINT 4,5,6,7,8 1 RCLK cycles td14 Delay time, read RBR/LSR to reset interrupttRINT 4,5,6,7,8 C L = 100 pF 150 ns NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or line status register). transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td15 Delay time, INTRPT to transmit start tIRS 9 8 24 baudout cycles td16 Delay time, start to interrupt tSTI 9 8 8 baudout cycles td17 Delay time, WR THR to reset interrupt tHR 9 C L = 100 pF 140 ns td18 Delay time, initial write to interrupt (THRE)tSI 9 16 32 baudout cycles td19 Delay time, read IIR to reset interrupt (THRE)tIR 9 C L = 100 pF 140 ns td20 Delay time, write to TXRDY inactive tWXI 10,11 C L = 100 pF 195 ns td21 Delay time, start to TXRDY active tSXA 10,11 C L = 100 pF 8 baudout cycles modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td22 Delay time, WR MCR to output tMDO 12 C L = 100 pF 100 ns td23 Delay time, modem interrupt to set interrupttSIM 12 C L = 100 pF 170 ns td24 Delay time, RD MSR to reset interrupt tRIM 12 C L = 100 pF 140 ns
2 XIN Cycles
Figure 1. Baud Generator Timing Waveforms
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† Applicable only when ADS is tied low. Figure 2. Write Cycle Timing Waveforms
† Applicable only when ADS is tied low. Figure 3. Read Cycle Timing Waveforms
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8 Clocks
Figure 4. Receiver Timing Waveforms
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NOTES: A. This is the reading of the last byte in the FIFO. B. For a timeout interrupt, td13 = 8 RCLKs. Figure 7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0) NOTES: A. This is the reading of the last byte in the FIFO. B. For a timeout interrupt, td13 = 8 RCLKs. Figure 8. Receiver Ready (RXRDY) Waveforms, FCR = 1 or FCR3 = 1 (mode 1)
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Figure 12. Modem Control Timing Waveforms
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APPLICATION INFORMATION
D7–D0 MEMR or I/OR MEMW or I/ON INTR RESET CS L H EIA 232-D Drivers and Receivers XOUT XIN RCLK BAUDOUT RI CTS DCD DSR DTR RTS SOUT SIN INTRPT D7–D0 RD1 WR1 MR ADS WR2 RD2 CS2 CS1 CS0 TL16C550A (ACE)
3.072 MHz
C P U B u s Figure 13. Basic TL16C550A Configuration Figure 14. Typical Interface for a High-Capacity Data Bus
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A16–A23 ADS AD0–AD15 RSI/ABT PHI1 PHI2 PHI1 PHI2 ADS ADS CPU RSTO A16–A23 CS0 CS1 CS2 MR A0–A2 D0–D2 AD0–AD7 RD1 WR1 AD0–AD15 RD2 WR2 XIN XOUT BAUDOUT RCLK DTR RTS OUT1 OUT2 RI DCD DSR CTS SIN SOUT INTRPT TXRDY DDIS RXRDY GND (VSS) 5 V (VCC) 20 40 Alternate XTAL Control TL16C550A † EIA-232-D Connector 2919 TCU RD WR † Terminal numbers for the TL16C550A are for the N package. Figure 15. Typical TL16C550A Connection to a CPU
Table 1. Register Selection
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
is controlled by writing to this bit location (see Table 3). Table 2. ACE Reset Functions
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of these registers follow Table 3. Table 3. Summary of Accessible Registers
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1
0 Data Bit 0† Data Bit 0
1 Data Bit 1 Data Bit 1
2 Data Bit 2 Data Bit 2
3 Data Bit 3 Data Bit 3
4 Data Bit 4 Data Bit 4 0 0 Reserved
5 Data Bit 5 Data Bit 5 0 0 Reserved Stick
6 Data Bit 6 Data Bit 6 0
7 Data Bit 7 Data Bit 7 0
† Bit 0 is the least significant bit. It is the first bit serially transmitted or received. NOTE 4: These bits are always cleared in the TL16C450 mode.
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling. bits are written to or they are not programmed. Changing this bit clears the FIFOs. is not cleared. The 1 that is written to this bit position is self clearing. is not cleared. The 1 that is written to this bit position is self clearing. /C0068Bit 3: When this bit (FCR0) and FCR3 are set, RXRDY and TXRDY change from mode 0 to mode 1. /C0068Bits 4 and 5: These two bits (FCR4 and FCR5) are reserved for future use. /C0068Bits 6 and 7: These two bits (FCR6 and FCR7) set the trigger level for the receiver FIFO interrupt. Table 4 shows the trigger level for the receiver FIFO interrupt. Table 4. Receiver FIFO Trigger Level
- The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared as soon as the FIFO drops below its programmed trigger level.
- The IIR receive data available indication also occurs when the FIFO trigger level is reached, and, like the
interrupt, it is cleared when the FIFO drops below the trigger level.
- The receiver line status interrupt (IIR = 06), as before, has higher priority than the received data
available (IIR = 04) interrupt.
- The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is cleared when the FIFO is empty.
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FIFO interrupt mode operation (continued) 1. FIFO timeout interrupt occurs when the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character received was longer than 4 continuous character times ago (when 2 stop bits are programmed, the second one is included in this time delay). c. The most recent microprocessor read of the FIFO was longer than 4 continuous character times ago. This causes a maximum character received to interrupt issued delay of 160 ms at 300 baud with 12-bit characters. 2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). 3. When a timeout interrupt has occurred, it is cleared and the timer reset when the microprocessor reads one character from the receiver FIFO. 4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or after the microprocessor reads the receiver FIFO. When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows: 1. The THR interrupt (02) occurs when the transmit FIFO is empty. It is cleared as soon as the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read. 2. The transmit FIFO empty indications are delayed 1 character time minus the last stop bit time when the following occurs: THRE = 1 and there have not been at least two bytes at the same time in the transmit FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, if it is enabled. Character timeout interrupt and receiver FIFO trigger level interrupts have the same priority as the current received data available interrupt. The transmit FIFO empty interrupt has the same priority as the current THRE interrupt. FIFO polled mode operation When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user program checks the receiver and transmitter status using the LSR. /C0068LSR0 is set as long as there is one byte in the receiver FIFO. /C0068LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode and the IIR is not affected since IER2 = 0. /C0068LSR5 indicates when the transmit FIFO is empty. /C0068LSR6 indicates that both the transmit FIFO and shift registers are empty. /C0068LSR7 indicates whether there are any errors in the receiver FIFO. There is no trigger level reached or timeout conditions indicated in the FIFO polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters.
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the four types of interrupts (refer to Table 5) and the INTRPT output signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table3 and are described in the following bulleted list. /C0068Bit 0: This bit, when set, enables the received data available interrupt. /C0068Bit 1: This bit, when set, enables the THRE interrupt. /C0068Bit 2: This bit, when set, enables the receiver line status interrupt. /C0068Bit 3: This bit, when set, enables the modem status interrupt. /C0068Bits 4 – 7: These bits in the IER are not used and are always cleared. interrupt identification register (IIR) The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors. The ACE provides four prioritized levels of interrupts: /C0068Priority 1 – Receiver line status (highest priority) /C0068Priority 2 – Receiver data ready or receiver character time out /C0068Priority 3 –Transmitter holding register empty /C0068Priority 4–Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt is defined by the interrupt’s three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 4. Details of each bit are as follows: /C0068Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared, an interrupt is pending. When bit 0 is set, no interrupt is pending. /C0068Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 5. /C0068Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate that a timeout interrupt is pending. /C0068Bits 4 thru 5: These two bits are not used and are always cleared. /C0068Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FCR is set.
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Table 5. Interrupt Control Functions summarized in Table 3 and described in the following bulleted list. /C0068Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 6. Table 6. Serial Character Word Length and bit 2, is shown in Table 7.
Table 7. Number of Stop Bits Generated
0 Any word length 1
between the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked. cleared, odd parity (an odd number of logic 1s) is selected. bit 5 is cleared, stick parity is disabled. disabled. The break condition has no affect on the transmitter logic; it only affects the serial output. buffer, the THR, or the IER. are described in the following bulleted list and summarized in Table 3. data in the RBR or the FIFO. in the shift register is overwritten but is not transferred to the FIFO. ‡ Bits 1 through 4 are the error conditions that produce a receiver line status Interrupt.
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line status register (LSR)† (continued) /C0068Bit 2‡.: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. /C0068Bit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The ACE then samples this start bit twice and then accepts the input data. /C0068Bit 4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs, only the 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state and receives the next valid start bit. /C0068Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. /C0068Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO mode, this bit is set when the transmitter FIFO and shift register are both empty. /C0068Bit 7: In the TL16C550A, this bit is always cleared. In the TL16C450 mode, this bit is cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO. modem control register (MCR) The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in Table 3 and are described in the following bulleted list. /C0068Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to its low state. When bit 0 is cleared, DTR goes high. /C0068Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over the DTR output. /C0068Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner identical to bit 0’s control over the DTR output. † The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment ‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION modem control register (MCR) (continued) /C0068Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner identical to bit 0’s control over the DTR output. /C0068Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the following occurs: 1. The SOUT is set high. 2. The SIN is disconnected. 3. The output of the TSR is looped back into the RSR input. 4. The four modem control inputs (CTS , DSR, DCD, and RI) are disconnected. 5. The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. 6. The four modem control output terminals are forced to their inactive states (high). In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational but the modem control interrupt’s sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER. /C0068Bit 5 – 7: These bits are permanently cleared. modem status register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list. /C0068Bit 0: This bit is the change in clear to send (ΔCTS) indicator. Bit 0 indicates that the CTS input has changed states since the last time it was read by the CPU . When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. /C0068Bit 1: This bit is the change in data set ready (ΔDSR) indicator. Bit 1 indicates that the DSR input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. /C0068Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. /C0068Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. Bit 3 indicates that the DCD input to the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. /C0068Bit 4: This bit is the compliment of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, bit 4 is equivalent to the MCR bit 1 (RTS). /C0068Bit 5: This bit is the compliment of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, bit 5 is equivalent to the MCR bit 1 (DTR).
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is equivalent to the MCR bit 2 (OUT1). bit 7 is equivalent to the MCR bit 3 (OUT2). of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. accuracy of the selected baud rate is dependent on the selected crystal frequency. Refer to Figure 16 for examples of typical clock circuits. Table 8. Baud Rates Using a 1.8432-MHz Crystal
Table 9. Baud Rates Using a 3.072-MHz Crystal Figure 16. Typical Clock Circuits
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receiver buffer register (RBR) The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register. The ACEs RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. in the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. scratch register The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense that it temporarily holds the programmer’s data without affecting any other ACE operation. transmitter holding register (THR) The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Timing is suppled by the baud out (BAUDOUT ) clock signal. Transmitter section control is a function of the ACE line control register. The ACE THR receives data off the internal data bus and, when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, when the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
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