LTC1699 LINER

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, LTC and LT are registered trademarks of Linear Technology Corporation. n Fully Compliant with Intel 5-Bit Mobile (LTC1699-80) and Desktop VRM8.4 (LTC1699-81) and VRM9.0 (LTC1699-82) VID Specifications n Precision –0.35% Programmable Resistor Divider for Use with 0.8V Referenced DC/DC Converters n Two Different Divider Settings Can Be Stored Using a 2-Wire SMBus Serial Interface (Rev 1.1) n Built-In Safeguards Minimize Misprogramming Due to Bus Conflicts n Three Open-Drain Pins (CPU_ON, IO_ON, CLK_ON) and a Global Control Pin (VRON)to Shutdown or Soft-Start 3 DC/DC Converters Simultaneously n PGOOD Pin and 50ms PGOOD Timer n Available in MSOP-8 and SSOP-16 Package AMD Athlon is a trademark of Advanced Micro Devices, Inc. Pentium is a registered trademark of Intel Corporation. Intel SpeedStep is a trademark of Intel Corporation. The LTC 1699-80, LTC1699-81 and LTC1699-82 are pre- cision (–0.35% max), digitally programmed resistor di- viders that comply with Intel 5-bit mobile (LTC1699-80), desktop VRM8.4 (LTC1699-81) and VRM9.0 (LTC1699-82) VID specifications. Each IC can switch the output of a DC/DC converter between two set voltages. A digital input pin, SEL, selects one of two divider settings stored into registers via a 2-wire SMBus interface. The SMBus interface uses Write Word protocol to setup the registers and to turn the DC/DC converters on or off. Read Word protocol is used to verify register contents and to return the On/Off status of the converters. The LTC1699-80, LTC1699-81 and LTC1699-82 incorporate safeguards against errors due to bus conflicts. Three open-drain N-channel outputs (CPU_ON, IO_ON and CLK_ON) are provided to turn DC/DC converter sup- plies on or off via their RUN/SS inputs. A global control pin, VRON is used to turn the converters on or off simulta- neously. An internal timer pulls the PGOOD pin low for 50ms if the divider setting changes or the converters are turned on via the SMBus and the VRON pin. n Intel Desktop Pentium III Power Supply n Intel Mobile Pentium Power Supply with Intel SpeedStep TM Technology n Desktop AMD Athlon TM Power Supply n Software Programmable Remote Power Supply n Power Supplies with Voltage Margining SMBus VID Voltage Programmers CPU_ON IO_ON CLK_ON PGOOD FB VRON SCL SEL SDA VRON SCL SEL SDA SENSE VCC LTC1699-81 L1, 1µH 10µF 25V C1, C2, C3, C4, C9: TAIYO YUDAN C5: SANYO C10, C11: PANASONIC, SPCL. POLY. D1: CMDSH-3 D2: DIODES INC., B340A L1: TOKO, 919AS-1RON M1: Si4884DY M2: Si4874DY 10µF 25V 10µF 25V 22µF 6.3V 10µF 25V 10µF 35V ALUM VIN 5VDC NC NC NC GND GND RUN/SS PGOOD V RNG FCB I TH SGND I ON VFB BOOST TG SW PGND BG INTVCC VIN EXTVCC LTC1778

1699 TA05

1ΩR5 715k, 1% R2, 11k 0.22µF C15 220pF C12 0.1µFC19, 0.01µF 0.01µF C11 180µF GND GND VOUT 2.5V AT 10A+C10 180µF C18 2200pF C14, 0.1µF C8, 0.01µF 39k 100k PGOOD C13 4.7µF 6.3V SMBus Controlled High Efficiency DC/DC Converter APPLICATIO SU

FEATURES

TJMAX = 125°C, qJA = 200°C/W Consult factory for parts specified with wider operating temperature ranges. LTPV LTPW LTTB LTC1699EMS8-80 LTC1699EMS8-81 LTC1699EMS8-82 ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W (Note 1) ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V £ VCC £ 5.5V (Notes 3, 4) unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Operating Supply Voltage Range 2.7 5.5 V ICC Supply Current CPU_ON, IO_ON, CLK_ON, PGOOD Pins Are Open l 350 mA RFB-SENSE Resistance between SENSE and FB LTC1699-80, LTC1699-82 l 71 0 1 3 k W LTC1699-81 l 14 20 26 k W DE Divider Error All Divider Settings l – 0.35 0.35 % VIH SCL, SDA Input High Voltage l 2.1 V VIL SCL, SDA Input Low Voltage l 0.8 V VIH SEL, VRON Input High Voltage 1.3 2.0 V VIL SEL, VRON Input Low Voltage l 0.8 1.3 V VHYST SEL, VRON Hysteresis – 50 mV VOL SDA, CPU_ON, IO_ON, CLK_ON I = 3mA l 0.4 V Output Low Voltage IIN SCL, SDA, SEL, VRON Input Current SDA Not Acknowledging, 0 £ VPIN £ 5.5V, VPIN = 5.5V for VRON only l –10 mA Operating Temperature ORDER PART NUMBER GN PART MARKING 169980 169981 169982 LTC1699EGN-80 LTC1699EGN-81 LTC1699EGN-82 TJMAX = 125°C, qJA = 130°C/W TOP VIEW GN PACKAGE 16-LEAD PLASTIC SSOP SEL NC SDA SCL VRON PGOOD NC CPU_ON V CC GND GND FB SENSE NC CLK_ON IO_ON SEL SDA SCL PGOOD V CC GND FB SENSE TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP

ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V £ VCC £ 5.5V (Notes 3, 4) unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISK1 SDA, PGOOD, CPU_ON, IO_ON, 0 £ VPIN £ 2.7V l 51 9 6 0 m A CLK_ON Sink Current at VCC = 2.7V ISK2 SDA, PGOOD, CPU_ON, IO_ON, 0 £ VPIN £ 5.5V l 35 65 150 mA CLK_ON Sink Current at VCC = 5.5V ILKG PGOOD, CPU_ON, IO_ON, 0 £ VPIN £ 5.5V l –2 mA CLK_ON Leakage Current IPU VRON Pull-Up Current V PIN = 0 l –1 –2.5 –7 mA Timing (Note 5) fSMB SMBus Operating Frequency l 10 100 KHz tBUF Bus Free Time Between Stop/Start l 4.7 ms tHD:STA Hold Time After (Repeated) Start l 4.0 ms tSU:STA Repeated Start Setup Time l 4.7 ms tSU:STO Stop Condition Setup Time l 4.0 ms tHD:DAT Data Hold Time l 300 ns tSU:DAT Data Setup Time l 250 ns tLOW Clock Low Period l 4.7 ms tHIGH Clock High Period l 4.0 ms tf SCL, SDA Fall Time 0.9V CC to 0.65V l 300 ns tr SCL, SDA Rise Time 0.65V to 2.25V l 1000 ns tSSH SEL to SENSE High (Note 6) Toggle SEL to Switch from Min V OUT to Max VOUT, 500 ns VFB = 0.8V tSSL SEL to SENSE Low (Note 6) Toggle SEL to Switch from Max V OUT to Min VOUT, 500 ns VFB = 0.8V tSPL SEL Toggling to PGOOD Low Toggle SEL to Select New Code l 160 500 ns CL = 100pF, 10kW Pull-Up, S2 in Figure 1 tPH Stop Bit to CPU_ON, IO_ON C L = 100pF, 10kW Pull-Up, S2 in Figure 1 l 2 ms or CLK_ON High (Note 7) tPL Stop Bit to CPU_ON, IO_ON C L = 0.1mF, 10kW Pull-Up, S1 in Figure 1 l 20 50 ms or CLK_ON Low (Note 7) tPPL Stop Bit to PGOOD Low (Note 6) C L = 100pF, 10kW Pull-Up, S2 in Figure 1 l 250 ns tVH VRON High to CPU_ON, IO_ON C L = 100pF, 10kW Pull-Up, S2 in Figure 1 l 2 ms or CLK_ON High tVL VRON Low to CPU_ON, IO_ON, C L = 0.1mF, 10kW Pull-Up, S1 in Figure 1 l 50 ms CLK_ON Low tVPL VRON Low to PGOOD Low C L = 100pF, 10kW Pull-Up, S2 in Figure 1 l 130 500 ns tPGL PGOOD Low Duration C L = 100pF, 10kW Pull-Up, S2 in Figure 1 l 30 50 70 ms Note1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1699-80E, LTC1699-81E and LTC1699-82E are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40 °C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 4: All typical numbers are given for V CC = 5V and TA = 25°C. Note 5: These parameters are guaranteed by design and are not tested in production. SMBus timing is referenced to VIL and VIH levels. Note 6: Dominated by the switching regulator. The delay due to the LTC1699-80, LTC1699-81 or LTC1699-82 is typically 500ns. Note 7: Measured from the rising edge of SDA during Data High acknowledgement.

TYPICAL PERFOR A CE CHARACTERISTICSUW Supply Current vs Supply Voltage Supply Current vs Temperature Resistance Between SENSE and FB Pins vs Temperature (LTC1699-81) SCL, SDA, SEL and VRON Input High and Low Voltage vs Temperature SCL, SDA, SEL and VRON Input High and Low Voltage vs Supply Voltage SCL, SDA, SEL and VRON Hysteresis vs Temperature SCL, SDA, SEL and VRON Hysteresis vs Supply Voltage SDA, CPU_ON, IO_ON, CLK_ON Output Low Voltage vs Temperature VCC (V) 1.5 SUPPLY CURRENT (µA)

1699 G01

TA = 25°C TEMPERATURE (°C) SUPPLY CURRENT (µA)

1699 G02

–5 5 –35 –15 5 25 45 65 85 105 125 VCC = 5.5V VCC = 2.7V TEMPERATURE (°C) RSENSE (kΩ )

1699 G03

20.08 20.06 20.04 20.02 20.00 19.98 19.96 19.94 19.92 19.90 19.88 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V TO 5.5V TEMPERATURE (°C) INPUT HIGH AND LOW VOLTAGE (V)

1699 G04

1.40 1.35 1.30 1.25 1.20 1.15 1.10 –5 5 –35 –15 5 25 45 65 85 105 125 INPUT HIGH, VCC = 5.5V INPUT LOW, VCC = 5.5V INPUT HIGH, VCC = 2.7V INPUT LOW, VCC = 2.7V SUPPLY VOLTAGE (V) INPUT HIGH AND LOW VOLTAGE (V)

1699 G05

1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 INPUT HIGH TA = 25°C INPUT LOW TEMPERATURE (°C) HYSTERESIS (V)

1699 G06

0.07 0.06 0.05 0.04 0.03 0.02 0.01 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 5.5V VCC = 2.7V SUPPLY VOLTAGE (V) HYSTERESIS (V)

1699 G07

0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 T = 25°C TEMPERATURE (°C) OUTPUT LOW VOLTAGE (V)

1699 G08

0.25 0.20 0.15 0.10 0.05 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V IPIN = 3mA VCC = 5.5V TEMPERATURE (°C) RSENSE (kΩ )

1699 G18

10.08 10.06 10.04 10.02 10.00 9.98 9.96 9.94 9.92 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V TO 5.5V Resistance Between SENSE and FB Pins vs Temperature (LTC1699-80, LTC1699-82)

TYPICAL PERFOR A CE CHARACTERISTICSUW SCL, SDA and SEL Input Current vs Temperature TEMPERATURE (°C) INPUT CURRENT (nA)

1699 G09

–5 5 –35 –15 5 25 45 65 85 105 125 SCL PIN SEL PIN SDA PIN VCC = 5.5V VPIN = 5.5V SDA, PGOOD, CPU_ON, IO_ON, CLK_ON Sink Current vs Temperature PGOOD, CPU_ON, IO_ON, CLK_ON Leakage Current vs Temperature VRON Pull-Up Current vs Temperature VRON Pull-Up Current vs Supply Voltage Power Good Low Duration vs Temperature LTC1699-80 Divider Error vs Temperature LTC1699-81 Divider Error vs Temperature LTC1699-82 Divider Error vs Temperature TEMPERATURE (°C) SINK CURRENT (mA)

1699 G10

–5 5 –35 –15 5 25 45 65 85 105 125 VCC = 5.5V, ISK2 VCC = 2.7V, ISK1 TEMPERATURE (°C) LEAKAGE CURRENT (nA)

1699 G11

–60 –40 –20 0 20 40 60 80 100 120 VPIN = 5.5V TEMPERATURE (°C) VRON PULL-UP CURRENT (µA)

1699 G12

2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 5.5V VCC = 2.7V SUPPLY VOLTAGE (V) 1.5 ‰VRON PULL-UP CURRENT‰ (µA)

1699 G013

3.0 2.5 2.0 1.5 1.0 0.5 TA = 25°C VRON = 0V TEMPERATURE (°C) DIVIDER ERROR (%)

1699 G15

0.05 –0.05 –0.10 –0.15 –0.20 –55 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V (MINIMUM VCC) CODE 31 CODE 15 CODE 16 CODE 0 TEMPERATURE (°C) DIVIDER ERROR (%)

1699 G16

0.25 0.20 0.15 0.10 0.05 –0.05 –0.10 –0.15 –0.20 –55 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V (MINIMUM VCC) CODE 15 CODE 31 CODE 0 CODE 16 TEMPERATURE (°C) POWER GOOD LOW DURATION (µs)

1699 G14

52.0 51.5 51.0 50.5 50.0 49.5 49.0 –60 –40 –20 0 20 40 60 80 100 120 VCC = 5.5V VCC = 2.7V TEMPERATURE (°C) DIVIDER ERROR (%)

1699 G17

0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 –0.02 –5 5 –35 –15 5 25 45 65 85 105 125 VCC = 2.7V (MINIMUM VCC) CODE 31 CODE 15 CODE 16 CODE 0

Note: Pin numbers apply to 16-lead SSOP packages. SEL (Pin 1): Register Select Input. A TTL compatible logic input pin that is used to select 1 of 2 resistor divider settings. SEL selects the setting in Register 0 if pulled low and the setting in Register 1 if pulled high. NC (Pin 2): Not connected. SDA (Pin 3): SMBus Data Input/Output. SDA is a high impedance input when address, command or data bits are shifted in. It is an open drain, N-channel output when acknowledging or sending data back to the microproces- sor during read-back. It requires a pull-up resistor or current source to V CC. SCL (Pin 4): SMBus Clock Input. Data at the SDA pin is latched into the LTC1699 at the rising edge of the clock and is shifted out of the SDA pin at the falling edge of the clock. SCL is a high impedance input pin. It is driven by the open collector output of a microprocessor and requires a pull- up resistor or current source to V CC. VRON (Pin 5): Global Control Input. This TTL compatible input pin is pulled up internally by a 2.5mA current source. Pulling VRON low forces the open drain output pins (CPU_ON, IO_ON, CLK_ON and PGOOD) to pull to ground. If the LTC1699-80, LTC1699-81 or LTC1699-82 is pro- grammed to turn on DC/DC converters, pulling VRON high three-states the CPU_ON, IO_ON and CLK_ON pins and allows the DC/DC converters to soft-start. PGOOD (Pin 6): Power Good Output. This open drain output is pulled low for 50ms each time the LTC1699-80, LTC1699-81 or LTC1699-82 turns on the DC/DC convert- ers or SEL is toggled to select a new code. PGOOD may be connected to the FCB input of an LTC DC/DC converter to force the converter into continuous mode operation. This reduces the time needed for the converter output to settle to a lower output voltage under light load conditions if the SEL pin is toggled. NC (Pin 7): Not connected. CPU_ON (Pin 8): CPU DC/DC Converter Control. Open drain output, usually connected to the RUN/SS pin of a DC/ DC converter that generates the CPU core supply. It pulls low to shut down the converter or becomes a high imped- ance state to allow the converter to soft-start. IO_ON (Pin 9): I/O DC/DC Converter Control. Open drain output, normally connected to the RUN/SS pin of the DC/ DC converter that generates the I/O supply. It pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. CLK_ON (Pin 10): Clock DC/DC Converter Control. Open drain output, optionally connected to the RUN/SS pin of the DC/DC converter that generates the supply for the clock buffer. It pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. NC (Pin 11): Not connected. SENSE (Pin 12): Sense Input. Upper terminal of the resistor divider that is connected directly to the output voltage being regulated. FB (Pin 13): Feedback Input. Center tap of the divider that is connected to the feedback pin of an LTC 0.8V referenced DC/DC converter. GND (Pin 14): Ground. Connect to regulator signal ground. GND (Pin 15): Divider Ground. Short to Pin 14. V CC (Pin 16): Positive Supply. 2.7V £ VCC £ 5.5V. Bypass this pin to ground with a 0.1mF ceramic capacitor. PI FU CTIO S UU U

1699 FBD

1699 F01

Figure 1. Load for Timing Tests

ADDRESS COMMAND CODE DATA LOW DATA HIGH SCL S D A 11 1 XXXXX XXX XXX R/W ACK VID4 VID3 VID0 VID2 VID1 C5000 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 PS R/W ACK VID4 VID3 VID0 VID2 VID1 ACKVID4 VID3 VID0 VID1 VID2 ACK ACK SLAVE ADDRESS SLAVE ADDRESSCOMMAND CODE DATA LOW DATA HIGH SCL SDA NOTE 1: S = START CONDITION, P = STOP CONDITION NOTE 2: C7, C6, C5 = 001 FOR SETUP , 010 FOR READ-BACK, 000 FOR ON AND 011 FOR OFF 1699 TD01 11 1 XXXXX ACK C5000 1 1 RD11000 0 0 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 SMBus WRITE WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 001X XXXB, DATA LOW = 0100 1XXXB, DATA HIGH = 0101 1XXXB SMBus READ WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 010X XXXB, DATA LOW = 0100 1000B, DATA HIGH = 0101 1000B 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 PS ACK S VID4 VID3 VID0 VID1 VID2 ACK DCON 00 DCON ACK Operating Sequences

tHD:STA tHD:DAT SDA SCL tSU:DAT tSU:STA tSU:STO STOP

1699 TD02

tHD:STA

1699 TD03

90%10% NOTE: TIMING RELATIVE TO THE STOP BIT (P) IS MEASURED FROM THE RISING EDGE OF SDA SEE TABLE 1 FOR VMIN AND VMAX SENSE VOLTAGES tPGL tPGL SCL P STOP 2nd ON PROTOCOL 2nd OFF PROTOCOL SMBON DCON VRON CPU_ON IO_ON CLK_ON VSENSE (VREF = 0.8V) SEL SDA PGOOD P 1.3V 1.3V 1.3V 1.3V 0.7V V MAX VMIN 0V 0V Timing for SMBus Interface CLK_ON, IO_ON, CLK_ON, PGOOD TIMING

(VRM) in both portable and desktop computers. Table 1. DC/DC Converter Output Voltage for VREF = 0.8V

APPLICATIO S I FOR ATIOWU UU output voltage of a DC/DC converter that generates the CPU core supply voltage. Its programmable ratios (see Table 1) are designed for 0.8V-referenced converters such as the LTC1628, LTC1702, LTC1735 and LTC1778 and comply with the Intel 5-bit desktop (VRM8.4 for LTC1699-81 and VRM9.0 for LTC1699-82) and 5-bit mobile VID codes. On power-up, the outputs of both registers are internally set to 11111B. The LTC1699-80, LTC1699-81 and LTC1699-82 provide three pins, CPU_ON, IO_ON, and CLK_ON to (optionally) control three DC/DC converters that generate the CPU, I/O and clock buffer V CC voltages in a VRM. These open drain, N-channel output pins usually connect to the RUN/SS pins of the converters and pull low to shut down the converters or become a high impedance state to allow the converters to soft-start. The PGOOD pin is driven from an internal timer that pulls PGOOD low for 50ms typical whenever the resistor divider setting is changed or the converters are allowed to soft- start. Over the entire temperature and supply voltage range, the timer low period is 70ms max which meets the 100ms max converter output settling time specified by Intel. The PGOOD pin, if tied to the FCB pin of an LTC DC/ DC converter, reduces the time needed for the converter output to decrease to a lower voltage under light load conditions by forcing the converter into continuous mode for 50ms. The TTL compatible VRON input pin and the output of the internal on/off state machine (SMBON) control the state of the CPU_ON, IO_ON, CLK_ON and PGOOD pins. SMBON is accessed using SMBus protocols and must be pro- grammed to a high state before the converters can turn on. The SMBus protocols (see Figure 2) incorporate safe- guards against errors caused by bus conflicts. Resistor Divider The resistor divider is designed specifically for DC/DC converters, such as the LTC1628, LTC1702, LTC1735, LTC1778 and LTC1929 with a reference voltage of 0.8V. It consists of a fixed resistor, R FB1 connected between the SENSE and FB pins and a variable resistor, R FB2, con- nected between the FB and GND pins. The SENSE and FB pins are tied to the output and feedback nodes of the DC/ DC converter respectively. The output of the DC/DC con- verter is given by: VOUT = VREF • (RFB2+RFB1)/RFB2 where VREF is the internal reference voltage of the con- verter. Each resistor has a tolerance of –30% but the ratio, (RFB2+RFB1)/RFB2, is specified to within –0.35% over temperature. The error budget for the DC/DC converter output voltage must include the –0.35% ratio tolerance and the tolerance in V REF. The value of RFB1 is fixed and RFB2 is changed to vary the divider setting. The value of R FB2 for any divider setting can be calculated from the above equation, assuming that RFB1 = 10k W for the LTC1699-80 and LTC1699-82 and 20kW for the LTC1699-81. Table 1 shows the output voltage of a DC/DC converter (V REF = 0.8V) for all 32 settings of the resistor divider. The divider setting is determined by the outputs (VID0-VID4) of the register selected by the SEL pin. SMBus Interface The SMBus interface uses two wires: SDA and SCL. Data to the LTC1699-80, LTC1699-81 or LTC1699-82, is latched at the rising edge of the SCL clock input and shifted out at the falling edge. The V IL and VIH logic threshold voltages of the SDA and SCL pins are 0.8V and 2.1V respectively and comply with Rev 1.1 version of the Intel System Management Bus Specifications. The Write Word and Read Word protocols (Figure 2) share three common features. First, the 7-bit slave address for both protocols is internally hardwired to 1110 001B = E2H. A single R/W bit follows the slave address. This bit is low for data transfer from the microprocessor to the LTC1699- 80, LTC1699-81 or LTC1699-82 and high for transfers in the opposite direction. Second, the LTC1699-80, LTC1699-81 and LTC1699-82 decode only the three most significant bits of the 8-bit command code. Table 2 shows the four valid combina- tions. All other combinations are ignored. Third, the Data Low and Data High bytes correspond to Registers 0 and 1 respectively. In Write Word protocol with C7 = C6 = 0, C5 = 1, the five most significant bits (VID0- VID4) of these bytes specify a resistor divider setting.

Table 2. LTC1699-80, LTC1699-81 and LTC1699-82 and low to high transitions respectively, while SCL is high. converters on or off in conjunction with the VRON pin. Figure 2. Write Word and Read Word Protocols

APPLICATIO S I FOR ATIOWU UU Register 1. After issuing the final acknowledgement bit, the SMBus interface returns to an idle state and waits for the next start bit. Read Word Protocol The Read Word protocol starts off like Write Word proto- col but after the command code acknowledgment, the microprocessor issues a second start bit (called a re- peated start). This is followed by the slave address but with the R/W bit set high to indicate that data direction is now from the LTC1699-80, LTC1699-81 or LTC1699-82 to the microprocessor. The LTC1699-80, LTC1699-81 or LTC1699-82 then acknowledges the slave address and clocks the contents of Register 0 (Data Low byte) to the microprocessor. The Data Low byte is acknowledged by the microprocessor. On detecting the acknowledgment bit, the LTC1699-80, LTC1699-81 or LTC1699-82 clocks out the contents of Register 1 (Data High byte). As defined in the SMBus specifications, the microprocessor does not acknowledge the last data byte. The LTC1699-80, LTC1699-81 or LTC1699-82 enters an idle state to wait for the next start bit after clocking out the Data High byte. The five most significant bits (VID0-VID4) of the Data Low and High bytes are the resistor divider settings previously loaded using the Setup protocol. The next bit below the VID0-VID4 bits is the status of the DCON signal. If this bit is low (high), the DC/DC converters are switched on (off). The two unused, least significant bits of the Data Low and Data High bytes are clocked out as zeros which removes the need to mask out these bits in software. Safeguards The LTC1699-80, LTC1699-81 and LTC1699-82 provide safeguards against incorrect divider codes and the unin- tentional turn-on or turn-off of the DC/DC converters. Incorrect codes due to bus conflicts during Setup proto- cols can cause damage to circuits powered by the DC/DC converters. The safeguards built into the LTC1699-80, LTC1699-81 and LTC1699-82 include Read-Back, re- peated On and Off protocols, ignoring On protocols if the registers have not been setup, locking out registers while the DC/DC converters are operating and latching in VID codes only in Setup protocols. After power-up, the microprocessor must set up the registers before the LTC1699-80, LTC1699-81 and LTC1699-82 recognizes On protocols. This requirement ensures that the correct DC/DC converter output is pro- grammed before the converters are turned on. After setup, Read-Back allows the contents of Registers 0 and 1 to be verified in case the VID codes were corrupted by noise or bus conflicts. In order to turn on the DC/DC converter, two On protocols must be sent to slave address E2H without any other (E2H) protocols in between. Protocols to other slave addresses are still allowed and are ignored. Similarly, two Off proto- cols must be sent to slave address E2H to turn the converters off. The On and Off protocols are monitored by an internal state machine. The output of the state machine, SMBON, is high after two On commands and low after two Off commands. Repeated On and Off protocols reduce the chances of bus conflicts and noise turning the converter on or off accidentally. In both On and Off protocols, the LTC1699-80, LTC1699-81 and LTC1699-82, do not latch in the Data Low and Data High bytes. This protects the settings that have already been loaded into the registers and verified by read-back. Once the converters are turned on (both SMBON and VRON are high) the contents of Registers 0 and 1 are protected and can only be altered with Setup protocols if VRON is pulled low or two Off protocols are sent to the LTC1699-80, LTC1699-81 or LTC1699-82 (to force SMBON low). DC/DC Converter Control The LTC1699-80, LTC1699-81 and LTC1699-82 provide six pins for DC/DC converter control: SEL, VRON, CPU_ON, IO_ON, CLK_ON and PGOOD. These pins (except SEL) and the output of the internal on/off state machine (SMBON) determine if the DC/DC converters are operating or in shutdown. The SEL and VRON pins are TTL compatible, high imped- ance inputs with a logic threshold of 1.3V over the entire 2.7V to 5.5V supply range. They are compatible with 3.3V logic and have –50mV of hysterisis for noise rejection. When pulled high or low, the SEL pin selects Register 1 and 0 respectively as the active divider setting. The VRON

VRON pin has an internal 2.5uA current source pull-up. CC supplies of the CPU, I/O circuits and the clock buffer. and CLK_ON pins from the corresponding RUN/SS pins. which allows time for the converters to enter regulation. operation and into continuous mode. and is the status bit that is returned during Read-back. Table 3. DC/DC Converter Control Pins Note 1: Also triggered by SEL pin toggling. are pulled to ground, shutting down the converters. to shut down the DC/DC converters. Burst Mode is a trademark of Linear Technology Corporation.

APPLICATIO S I FOR ATIOWU UU Operating Sequence A typical control sequence for the LTC1699-80, LTC1699-81 and LTC1699-82 is as follows:

  • On power up, the DCON bit is preset to a high state by the power-on reset (POR) circuit. The CPU_ON, IO_ON and CLK_ON pins are pulled low to shut down the DC/ DC converters. PGOOD pulls low to indicate that the converters are not in regulation.
  • Pull VRON low as a precaution. Take SEL high or low to select the divider setting; e.g., one that suits the existing power source (battery or wall-pack).
  • Use the Setup protocol to load the appropriate divider settings in Registers 0 and 1 and enable the on/off state machine.
  • Use the Read-Back protocol to verify the contents of Registers 0 and 1.
  • Repeat the setup and read-back if the codes are incor- rect (due to bus conflicts).
  • Send two On protocols in succession to clear the DCON bit.
  • Use the Read-Back protocol to verify that the DCON is low. A high state will indicate that an On command code was corrupted by bus conflicts.
  • Pull VRON high. Since DCON = 0, the CPU_ON, IO_ON and CLK_ON pins enter a high impedance state, allow- ing the DC/DC converters to soft-start. PGOOD stays low for 50ms.
  • To shut down the supply, send two Off protocols to set the DCON bit high or pull VRON low if immediate shutdown is required. The VRON signal in the 8-pin MSOP versions of the LTC1699-80, LTC1699-81 and LTC1699-82 are pulled high internally by a 2.5 mA current source. For these versions, the converters are turned on or off only through the SMBus interface. Overvoltage Protection Faults Toggling the SEL pin, i.e. changing the ladder setting “on the fly” can trigger some converters with over-voltage fault protection (OVP) into a fault state if the new setting calls for a lower output voltage. For some converters such as the LTC1702, cycling the power supply is the only way to clear the fault and restore normal operation. For the LTC1702, an OVP fault is triggered if the difference between the programmed and prevailing output voltages is greater than 15%, and persists for more than 25ms. To prevent the OVP fault from disabling the LTC1702, tie the FAULT pin of the LTC1702 low. Tying FAULT low does not disable the OVP circuit but blocks its effects.

I MAX1 PGOOD1 FCB RUN/SS1 COMP1 SGND FB1 I MAX2 BOOST2 BG2 TG2 SW2 PGND PGOOD2 FAULT RUN/SS2 COMP2 FB2 VCC 1µF 10Ω 1µF1µF 18.7k 20k 100k

1699 TA02

180µF 15pF 220pF 220pF 100k 1µF VOUT1 0.9V TO 2V AT 15A 0.22µF Q3Q2D3 COUT1, COUT2: PANASONIC EEFUE0G181R CIN: KEMET TS10X157M010AS D1, D2: MOTOROLA MBR0520LT1 D3: MOTOROLA MBRS320T3 L1: MURATA LQT12535C1R5N12 L2: COILTRONICS UP2B-2R2 Q1, Q2, Q3: INTERNATIONAL RECTIFIER IRF7811 Q4, Q5: 1/2 FAIRCHILD NDS8926 PWRGD1 1µH 10µF 1µF VIN = 5V –10% 0.22µF CIN 150µF 10V 2200pF 15pF 220pF 10.2k 0.1% 11.5k 0.1% 10k 2.2µH COUT2 180µF 1µF VOUT2 1.5V/3A PWRGD2 VIN 10k TO µP FB CLK_ON IO_ON PGOOD VRON SDA SEL SCL VCC SENSE GND LTC1699-80 CPU_ON 0.1µF SMBus Programmed Dual Output Mobile Pentium Processor Supply

0.47µF C3, C4: OS-CON PS680M C18–C21: T510E108M004 L1, L2: SUMIDA CEP149-1R0MC Q1–Q8: FDS6670A OR FDS7760A C17 1000pF NC TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 SW2 TG2 AMPMD RUN/SS SENSE1+ SENSE1– EAIN PLLFLTR PLLIN NC I TH SGND V DIFFOUT VOS– VOS+ SENSE2– SENSE2+ LTC1929 Q8Q7 Q6Q5 1µH 0.002Ω Q2Q1 C12 1µF C13 2.2µF 0.47µF BAT54A VIN+ VIN– 5VC22 1µF C23 1µF 1µF C1, 1000pF C14 10µF 2µH R8 0.002Ω 10Ω VIN+

1699 TA06

50Ω C19 C20 C21 C24 10µF VOUT+ VOUT– VOSENSE+ VOSENSE– 1.6V/40A REMOTE SENSE R10 50Ω 10k 0.1µF 2.7kC9, 0.01µF C10, 100pF C11, 1nF C15 180pF R5, 10k LTC1699-81 SEL NC SDA SCL VRON PGOOD NC CPU_ON SEL SDA SCL VRON PGOOD V CC GND GND FB SENSE NC CLK_ON IO_ON R6, 100k C25 0.1µF SMBus Controlled 5V Input, 1.6V/40A CPU Power Supply

C OSC RUN/SS ITH PGOOD SENSE SENSE+ VOSENSE SGND TG BOOST SW VIN INTVCC BG PGND EXTVCC LTC1735-1 CSS 0.1µF CB 0.22µF CC2 220pF 47pF 100k 470k INTVCC CC 220pFRC 20k 100k* *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF RSENSE 0.004Ω VOUT 1.6V 12A 1000pF COSC 39pF 4.7µF 1µF + COUT 180µF

  • 3 C O 47µF 10V CIN 150µF 6.3V
  • 2 FDS6680A Q2, Q3 FDS6680A
  • 2 C OUT: PANASONIC EEFUEOG181R CIN: PANASONIC EEFUEOJ151R CO: TAIYO YUDEN LMK550BJ476MM-B L1: COILCRAFT 1705022P-781HC Q4, Q5: 2N2222 R SENSE: IRC LRF 2512-01-R004-J

1699 TA03

0.78µH VIN SGND POWER GOOD 10k FB PGOOD CLK_ON IO_ON CPU_ON VRON SDA SEL SCL VCC SENSE TO µP GND SGND LTC1699-81 180pF 0.1µF SMBus Programmed CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) with Burst Mode Operation Disabled

Dimensions in inches (millimeters) unless otherwise noted. 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF MSOP (MS8) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.021 – 0.006 (0.53 – 0.015) 0° – 6° TYP SEATING PLANE 0.007 (0.18) 0.043 (1.10) MAX 0.009 – 0.015 (0.22 – 0.38) 0.005 – 0.002 (0.13 – 0.05) 0.034 (0.86) REF 0.0256 (0.65) BSC 12 3 4 0.193 – 0.006 (4.90 – 0.15) 8 7 6 5 0.118 – 0.004* (3.00 – 0.102) 0.118 – 0.004** (3.00 – 0.102) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 2001 sn1699 1699fs LT/TP 0201 4K • PRINTED IN USA RELATED PARTS TYPICAL APPLICATIO U PART NUMBER DESCRIPTION COMMENTS LTC1628/ High Efficiency, 2-phase, Synchronous Step Down Switching Regulators Dual Controller, 0.8V Reference, Wide Input Voltage Range LTC1628-PG LTC1694/ SMBus/I 2C Accelerators in SOT-23 Improves SMBus/I 2C Data Integrity LTC1694-1 LTC1702 Dual 1 MHz Synchronous 5V to 2.xV/1.xV Switching Regulator Controller Low Input Voltages, High Efficiency LTC1735/ High Efficiency Synchronous Step Down Switching Regulators 0.8V Reference, Wide Input Voltage Range, Synchronizable/ LTC1735-1 Programmable Fixed Frequency LTC1878 Monolithic Synchronous Step Down Switching Regulator 0.8V Reference, Internal Synchronous Switch, 2.65V £ VIN £ 6V LTC1706-19 VID Voltage Programmer Parallel Interface, Designed for 1.19V Referenced Switching Regulators LTC1706-81 5-Bit Desktop VID Programmer Parallel Interface, 0.8V Reference Intel Desktop VID Codes (VRM8.4) LTC1706-82 VID Programmer for Intel VRM9.0 Parallel Interface, 0.8V Reference Intel Desktop VID codes (VRM9.0) LTC1778 Wide Operating Range, No R SENSE TM Step-Down Controller 2% to 90% Duty Cycle at 200kHz, t ON(MIN) £ 100ns, Stable with Ceramic COUT LTC1929/ 2-Phase High Efficiency Synchronous Step-Down Switching Regulators 2-Phase Single Output Controller, Wide V IN Range: 4V to 36V LTC1929-PG Operation No RSENSE is a trademark of Linear Technology Corporation. VCC FB GND SENSE SCL SEL PGOOD SDA 2µP LTC1699 SMBus1 SMBus2 VCC GND LTC1694 0.1µF VCC TO DC/DC CONVERTER SMBus

1699 TA04

0.1µF Enhanced Data Transmission Speed