1664

LTC1664_1 LINER

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

FEATURES

1664 integrates four accurate, serially addres- sable 10-bit digital-to-analog converters (DACs) in a tiny 16-pin Narrow SSOP package. Each buffered DAC draws just 59mA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads of up to 1000pF. Sleep mode further reduces total supply current to 1mA. Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent lin- earity while allowing for an exceptionally small external form factor. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1664 ideal for battery-powered applications, while its ease of use, high performance and wide supply range make it an excellent choice as a general-purpose converter. n Tiny: 4 DACs in the Board Space of an SO-8 n Micropower: 59mA per DAC Plus 1mA Sleep Mode for Extended Battery Life n Wide 2.7V to 5.5V Supply Range n Rail-to-Rail Voltage Outputs Drive 1000pF n Reference Range Includes Supply for Ratiometric 0V-to-VCC Output n Reference Input Impedance is Code-Independent —Eliminates External Reference Buffer n Individually Addressable DACs n Differential Nonlinearity: £ –0.75LSB Max n Pin-Compatible Octal Version Available (LTC1660) n Mobile Communications n Remote Industrial Devices n Automatic Calibration for Manufacturing n Portable Battery-Powered Instruments n Trim/Adjust Applications 2 5 1GND VOUT A VOUT B REF CS/LD SCK VCC VOUT D VOUT C CLR DOUT DIN 1664 BD 10-BIT DAC A 10-BIT DAC D 3 410-BIT DAC B 10-BIT DAC C ADDRESS DECODER CONTROL LOGIC SHIFT REGISTER CODE 0 256 512 768 1023 LSB

1664 G08

1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 VCC = 5V VREF = 4.096V Differential Nonlinearity (DNL) , LTC and LT are registered trademarks of Linear Technology Corporation. BLOCK DIAGRA W

A UGWA WU WARBSOLUTEX I T I S ORDER PART NUMBER WU UPACKAGE/ORDER I FOR ATIO TJMAX = 125°C, qJA = 150°C/W (GN) TJMAX = 125°C, qJA = 100°C/W (N) Consult factory for Military grade parts. (Note 1) VOUT A, VOUT B…V OUT D, Operating Temperature Range LTC1664CGN LTC1664CN LTC1664IGN LTC1664IN GN PART MARKING 1664 1664I TOP VIEW GN PACKAGE 16-LEAD PLASTIC SSOP N PACKAGE 16-LEAD PDIP GND V OUT A VOUT B VOUT C VOUT D REF CS/LD SCK VCC NC NC NC NC CLR D OUT DIN ELECTRICAL C CHARA TERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF £ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITONS MIN TYP MAX UNITS Accuracy Resolution l 10 Bits Monotonicity (Notes 2, 4) l 10 Bits DNL Differential Nonlinearity (Notes 2, 4) l – 0.2 – 0.75 LSB INL Integral Nonlinearity (Notes 2, 4) l – 0.6 – 2.5 LSB VOS Offset Error (Note 7) l – 10 – 30 mV VOS Temperature Coefficient l – 15 mV/°C FSE Full-Scale Error V CC = 5V, VREF = 4.096V (Note 4) l –3 – 15 LSB Full-Scale Error Temperature Coefficient l – 30 mV/°C PSR Power Supply Rejection V REF = 2.5V 0.18 LSB/V Reference Input Input Voltage Range l 0V CC V Resistance Not in Sleep Mode l 70 130 k W Capacitance 12 pF IREF Reference Current Sleep Mode l 0.001 1 mA Power Supply VCC Positive Supply Voltage l 2.7 5.5 V ICC Supply Current V CC = 5V (Note 3) l 236 380 mA VCC = 3V (Note 3) l 186 290 mA Sleep Mode (Note 3) l 13 mA

ELECTRICAL C CHARA TERISTICS TI I G CHARACTERISTICSUW The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF £ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 4.5V to 5.5V t1 DIN Valid to SCK Setup l 40 15 ns t2 DIN Valid to SCK Hold l 0 –11 ns t3 SCK High Time (Note 6) l 30 5 ns t4 SCK Low Time (Note 6) l 30 7 ns t5 CS/LD Pulse Width (Note 6) l 80 30 ns t6 LSB SCK High to CS/LD High (Note 6) l 30 4 ns t7 CS/LD Low to SCK High (Note 6) l 80 26 ns t8 DOUT Propagation Delay C LOAD = 15pF (Note 6) l 52 6 8 0n s t9 SCK Low to CS/LD Low (Note 6) l 20 0 ns t10 CLR Pulse Width (Note 6) l 100 37 ns t11 CS/LD High to SCK Positive Edge (Note 6) l 30 0 ns SCK Frequency (Notes 6 and 8) l 16.7 MHz VCC = 2.7V to 5.5V t1 DIN Valid to SCK Setup (Note 6) l 60 20 ns t2 DIN Valid to SCK Hold (Note 6) l 0 –14 ns t3 SCK High Time (Note 6) l 50 8 ns t4 SCK Low Time (Note 6) l 50 12 ns DC Performance Short-Circuit Current Low V OUT = 0V, VCC = 5.5V, VREF = 5.1V, l 10 30 100 mA Code = 1023 (Note 9) Short-Circuit Current High V OUT = VCC = 5.5V, VREF = 5.1V, Code = 0 (Note 9) l 10 27 120 mA AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) 0.60 V/ ms Falling (Notes 4, 5) 0.25 V/ ms Voltage Output Settling Time Rising 0.1V FS to 0.9VFS – 0.5LSB (Notes 4, 5) 6 ms Falling 0.9VFS to 0.1VFS – 0.5LSB (Notes 4, 5) 19 ms Capacitive Load Driving 1000 pF Digital I/O VIH Digital Input High Voltage V CC = 2.7V to 5.5V l 2.4 V VCC = 2.7V to 3.6V l 2.0 V VIL Digital Input Low Voltage V CC = 4.5V to 5.5V l 0.8 V VCC = 2.7V to 5.5V l 0.6 V VOH Digital Output High Voltage I OUT = –1mA, D OUT Only l VCC – 1 V VOL Digital Output Low Voltage I OUT = 1mA, DOUT Only l 0.4 V ILK Digital Input Leakage V IN = GND to VCC l 0.05 – 10 mA CIN Digital Input Capacitance 2p F

Supply Current vs Temperature SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t5 CS/LD Pulse Width (Note 6) l 100 30 ns t6 LSB SCK High to CS/LD High (Note 6) l 50 5 ns t7 CS/LD Low to SCK High (Note 6) l 100 27 ns t8 DOUT Propagation Delay C LOAD = 15pF (Note 6) l 5 47 150 ns t9 SCK Low to CS/LD Low (Note 6) l 30 0 ns t10 CLR Pulse Width (Note 6) l 120 41 ns t11 CS/LD High to SCK Positive Edge (Note 6) l 30 0 ns SCK Frequency (Notes 6 and 8) l 10 MHz TYPICAL PERFOR A CE CHARACTERISTICS UW TI I G CHARACTERISTICSUW The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See Rail-to-Rail output considerations. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kW in parallel with 100pF. Note 5: VCC = VREF = 5V. Note 6: Guaranteed by design and not subject to test. Note 7: Measured at code 20. Note 8: If a continuous clock is used, CS/LD timing (t7 and t9) will limit the maximum clock frequency to 5MHz at 4.5V to 5.5V(3.85MHz at 2.7V to 5.5V). Note 9: Any output shorted. Differential Nonlinearity (DNL)Integral Nonlinearity (INL) CODE 0 256 512 768 1023 LSB

1664 G07

2.5 2.0 1.5 1.0 0.5 – 0.5 –1.0 –1.5 – 2.0 – 2.5 VCC = 5V VREF = 4.096V CODE 0 256 512 768 1023 LSB 1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 VCC = 5V VREF = 4.096V TEMPERATURE (°C) –55 –35 –15 5 45 85 SUPPLY CURENT (mA) 300 280 260 240 220 200 180 160

1664 G11

VCC = 5.5V VREF = VCC CODE = 1023 VCC = 4.5V VCC = 3.6V VCC = 2.7V

TYPICAL PERFOR A CE CHARACTERISTICS UW Large-Signal Step Response TIME (ms) 0 2 04 06 08 0 1 0 0 VOUT (V)

1664 G05

10% TO 90% STEP VCC = VREF = 5V 02468 1 0 VCC – VOUT (mV)

1664 G03

–55°C 25°C 125°C VREF = 4.096V DVOUT < 1LSB CODE = 1023 |IOUT| (mA) (Sourcing) Minimum VOUT vs Load Current (Output Sinking) |IOUT| (mA) (Sinking) 02468 1 0 VOUT (mV)

1664 G04

–55°C 25°C 125°C VCC = 5V CODE = 0 IOUT (mA) –30 –20 –10 0 10 20 30 VOUT (V)

1664 G01

2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 VCC = 4.5V VCC = 5V VCC = 5.5V VREF = VCC CODE = 512 SINKSOURCE IOUT (mA) –15 – 4 –8–12 0 4 8 12 15 VOUT (V)

1664 G02

1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 VCC = 2.7V VCC = 3V VCC = 3.6V VREF = VCC CODE = 512 SINKSOURCE Load Regulation vs Output Current Load Regulation vs Output Current IOUT (mA) –2 –1 0 1 2 DVOUT (LSB) 1.5 0.5 –0.5 –1.5

1664 G09

VCC = VREF = 5V CODE = 512 SINKSOURCE IOUT (µA) –500 0 500 DVOUT (LSB) 1.5 0.5 –0.5 –1.5

1664 G10

VCC = VREF = 3V CODE = 512 Minimum Supply Headroom vs Load Current (Output Sourcing) Midscale Output Voltage vs Load Current Midscale Output Voltage vs Load Current LOGIC INPUT VOLTAGE (V) SUPPLY CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 0.2 1234

1664 G12

Supply Current vs Logic Input Voltage

GND (Pin 1): System Ground. VOUT A to VOUT D (Pins 2–5): DAC Analog Voltage Outputs. The output range is 0 1023 1024to V REF æ Łç ö REF (Pin 6): Reference Voltage Input. 0V £ VREF £ VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. D IN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. DOUT (Pin 10): Serial Interface Data Output. Data appears on DOUT 16 positive SCK edges after being applied to DIN. May be tied to DIN of another serial device for daisy-chain operaton. CMOS and TTL compatible. CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. NC (Pins 12–15): Make no electrical connection to these pins. V CC (Pin 16): Supply Voltage Input. 2.7V £ VCC £ 5.5V.

1664 F01

Table 1. LTC1664 Input Word code and VREF is the voltage at REF (Pin 6). diode from REF (anode) to VCC (cathode). SCK must be low before CS/LD is pulled low. b (the DAC input word D9-D0 is ignored).

Table 2. DAC Address/Control Functions

0000 N o C hange Wake

0001 Load DAC A Wake

0010 Load DAC B Wake

0011 Load DAC C Wake

0100 Load DAC D Wake

0101 R eserved

0110 R eserved

0111 R eserved

1000 R eserved

1001 R eserved

1010 R eserved

1011 R eserved

1100 R eserved

1101 R eserved

1110 N o C hange Sleep

1111 Load ALL DACs Wake

1664 F02

Figure 2. LTC1664 Register Loading Sequence

Each of the four rail-to-rail output amplifiers contained in the LTC1664 can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85W when driving a load to the rails. The output amplifiers are stable driving capacitive loads of up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1 mF load can be successfully driven by inserting a 20W resis- tor; a 2.2mF load needs only a 10W resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given. Rail-to-Rail Output Considerations In any rail-to-rail voltage output DAC, the output is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to V CC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. OPERATIOU

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative

A Low Power Dual Trim Circuit with Coarse/Fine Adjustment TYPICAL APPLICATIONSU VOUT2VOUT1 110Ω COARSE 0.1µF 0.1µF 110Ω 3.3V 3.3VR2 11k 11k FINE 110Ω COARSE 11k FINE

1664 TA01

0.1µF3.3V LTC1664– U2A LT®1490 LTC1258-2.5 0.1µF 0.1µF 110Ω 11k U2B LT1490 CODE A 1024VOUT 1 = VREF + = 2.5V + = 2.5V + CODE B 1024 CODE A 1024 )) 100 CODE B 1024 CODE D 1024 )) CODE C 1024 CODE D 1024 )) 100 CODE C 1024 VOUT 2 = VREF +

A 4-Channel Bipolar Output Voltage Circuit Configuration

1664 TA02

VOUT B¢ – 5V R R U2B LT1491 VOUT A¢ – 5V R 0.1µF 0.1µF VS+ VS– R U2A LT1491 0.1µF VOUT C¢ – 5V U2C LT1491 VOUT D¢ – 5V RR RR U2D LT1491 CODE 512 1023 VOUT X –5 V +4.99V

Dimensions in inches (millimeters) unless otherwise noted. 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF

Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) N16 1098 0.255 – 0.015* (6.477 – 0.381) 0.770* (19.558) MAX 1 2 3 4 5 6 7 8 9101112131415 0.020 (0.508) MIN 0.125 (3.175) MIN 0.130 – 0.005 (3.302 – 0.127) 0.065 (1.651) TYP 0.045 – 0.065 (1.143 – 1.651) 0.018 – 0.003 (0.457 – 0.076) 0.100 (2.54) BSC 0.009 – 0.015 (0.229 – 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.325 +0.035 –0.015 +0.889 –0.3818.255() *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear-tech.com RELATED PARTS An 11-Bit Pin Driver VH and VL Adjustment Circuit for ATE Applications 61611 DAC A CLR V CC REF U1 LTC1664 0.1µF 0.1µF 0.1µF VA 3 VH¢ = VH + ∆VH VL¢ = VL + ∆VL VL¢ VH (FROM MAIN DAC) VL (FROM MAIN DAC) 10V –5 V RG 50k RF VB VC VD GND

1664 TA03

0.1µF RG 50k RG 50k RG 50k U2A LT1368 0.1µF RF RF RF LOGIC DRIVE PIN DRIVER DAC C DAC D CS/LD SCK DIN U2B LT1368 VL VOUT VH CODE A 1023 1023 1023 512 512 512 CODE B 1023 512 1023 512 1023 512 ∆VH, ∆VL + 250mV +500mV – 250mV + 250mV –500mV –250mV VA = VC = 2.5V For Resistor Values Shown: Adjustment Range = –500mV Adjustment Step Size = 500µV VH¢ = VH + (VA – VB)RF RG VL¢ = VL + (VC – VD)RF RG VH¢ PART NUMBER DESCRIPTION COMMENTS LTC1665/LTC1660 Octal 8/10-Bit V OUT DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, 60mA per DAC, Rail-to-Rail Output LTC1661 Dual 10-Bit V OUT DAC in 8-Pin MSOP Package V CC = 2.7V to 5.5V, 60mA per DAC, Rail-to-Rail Output LTC1662 Ultra Low Power Dual 10-Bit V OUT DAC in 8-Pin MSOP Package V CC = 2.7V to 5.5V, 1.5mA per DAC, Rail-to-Rail Output LTC1663 Single 10-Bit V OUT DAC with 2-Wire Interface in SOT-23 Package V CC = 2.7V to 5.5V, Internal Reference, 60mA LTC1446/LTC1446L Dual 12-Bit V OUT DACs in SO-8 Package with Internal Reference LTC1446: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 Dual 12-Bit V OUT DAC in SO-8 Package V CC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454/LTC1454L Dual 12-Bit V OUT DACs in SO-16 Package with Added Functionality LTC1454: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LT1460 Micropower Precision Series Reference, 2.5V, 5V, 10V Versions 0.075% Max, 10ppm/ °C Max, Only 130mA Supply Current LTC1590 Dual 12-Bit I OUT DAC in SO-16 Package V CC = 4.5V to 5.5V, 4-Quadrant Multiplication LTC1654 Dual 14-Bit DAC in SO-8 Footprint 1LBS DNL, Selectable Speed/Power LTC1659 Single Rail-to-Rail 12-Bit V OUT DAC in 8-Lead MSOP Package Low Power Multiplying V OUT DAC. Output Swings from VCC: 2.7V to 5.5V GND to REF. REF Input Can Be Tied to V CC ª LINEAR TECHNOLOGY CORPORATION 2000 1664f LT/TP 0700 4K • PRINTED IN THE USA