1654

LTC1654_1 LINER

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package ■ 14-Bit Monotonic Over Temperature ■ Individually Programmable Speed/Power: 3µs Settling Time at 930µA 8.5µs Settling Time at 540µA ■ 3V to 5V Single Supply Operation ■ Maximum Update Rate: 0.9MHz ■ Buffered True Rail-to-Rail Voltage Outputs ■ User Selectable Gain ■ Power-On Reset and Clear Function ■ Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface ■ Smallest Dual 14-Bit DAC: 16-Lead Narrow The LTC 1654 is a dual, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC). It is available in a 16-lead narrow SSOP package, making it the smallest dual 14-bit DAC available. It includes output buffer amplifiers and a flexible serial interface. The LTC1654 has REFHI pins for each DAC that can be driven up to V CC. The output will swing from 0V to VCC in a gain of 1 configuration or VCC/2 in a gain of 1/2 configu- ration. It operates from a single 2.7V to 5.5V supply. The LTC1654 has two programmable speeds: a FAST and SLOW mode with ±1LSB settling times of 3 µs or 8.5µs respectively and supply currents of 930µA and 540µA in the two modes. The LTC1654 also has shutdown capabil- ity, power-on reset and a clear function to 0V. ■ Digital Calibration ■ Industrial Process Control ■ Automatic Test Equipment ■ Offset/Gain Adjustment ■ Multiplying DAC DAC B 1654 BD VOUT B REFHI B VOUT A X1/X1/2 B REFHI A POWER-ON RESET DAC A REFLO AREFLO B X1/X1/2 A INPUT LATCH CONTROL LOGIC CS/LD SCK SDO CLR SDI INPUT LATCH DAC REGISTER 32-BIT SHIFT REGISTER DAC REGISTER FEATURES DESCRIPTIO U APPLICATIO SU BLOCK DIAGRA W , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245.

(Note 1) TTL Input Voltage, REFHI, Operating Temperature Range ORDER PART NUMBER TJMAX = 125°C, θJA = 110°C/W LTC1654CGN LTC1654IGN GN PACKAGE 16-LEAD PLASTIC SSOP TOP VIEW X 1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A V OUT A GN PART MARKING 1654 1654I ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.

ELECTRICAL CHARACTERISTICS

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC n Resolution ● 14 Bits Monotonicity ● 14 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ● ± 0.3 ± 1 LSB INL Integral Nonlinearity Integral Nonlinearity (Note 2) ● ± 1.2 ± 4 LSB ZSE Zero Scale Error 0 °C ≤ TA ≤ 70°C ● 0 6.5 mV VOS Offset Error 0 °C ≤ TA ≤ 70°C (Note 3) ● ± 6.5 mV –40 °C ≤ TA ≤ 85°C (Note 3) ● ± 9.0 mV VOSTC Offset Error Tempco ± 15 µV/°C Gain Error ● ±24 LSB Gain Error Drift 5 ppm/ °C Power Supply VCC Positive Supply Voltage For Specified Performance ● 2.7 5.5 V ICC Supply Current (SLOW/FAST) 2.7V ≤ VCC ≤ 5.5V (Note 5) SLOW ● 540 850 µA 2.7V ≤ VCC ≤ 5.5V (Note 5) FAST ● 930 1400 µA 2.7V ≤ VCC ≤ 3.3V (Note 5) SLOW ● 350 500 µA 2.7V ≤ VCC ≤ 3.3V (Note 5) FAST ● 680 1000 µA In Shutdown (Note 5) ● 31 0 µA Op Amp DC Performance Short-Circuit Current Low V OUT Shorted to GND ● 70 120 mA Short-Circuit Current High V OUT Shorted to VCC ● 80 120 mA Output Impedance to GND Input Code = 0 ● 40 200 Ω PSR Power Supply Rejection REFHIA, REFHIB = 4.096V (V CC = 5V ±10%) ● 2.5 mV/V REFHIA, REFHIB = 2.048V (VCC = 3V ±10%) Input Code = 16383

The ● denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance Voltage Output Slew Rate (Note 8) SLOW ● 0.20 0.9 V/ µs (Note 8) FAST ● 1.25 3.8 V/ µs Voltage Output Settling Time (Note 4) to ±1LSB, SLOW 8.5 µs (Note 4) to ±1LSB, FAST 3.0 µs Digital Feedthrough (Note 7) 1 nV•s Midscale Glitch Impulse DAC Switch Between 8000 and 7FFF 20 nV•s Output Noise Voltage Density at 10kHz, SLOW 170 nV/ √Hz at 10kHz, FAST 150 nV/ √Hz Digital I/O VIH Digital Input High Voltage V CC = 5V ● 2.4 V VIL Digital Input Low Voltage V CC = 5V ● 0.8 V VOH Digital Output High Voltage V CC = 5V, IOUT = –1mA, D OUT Only ● VCC – 0.4 V VOL Digital Output Low Voltage V CC = 5V, IOUT = 1mA, DOUT Only ● 0.4 V VIH Digital Input High Voltage V CC = 3V ● 2.4 V VIL Digital Input Low Voltage V CC = 3V ● 0.8 V VOH Digital Output High Voltage V CC = 3V, IOUT = –1mA, D OUT Only ● VCC – 0.4 V VOL Digital Output Low Voltage V CC = 3V, IOUT = 1mA, DOUT Only ● 0.4 V ILEAK Digital Input Leakage V IN = GND to VCC ● ± 10 µA CIN Digital Input Capacitance (Note 6) 10 pF Reference Input Reference Input Resistance REFHI to REFLO ● 30 60 k Ω Reference Input Range (Note 6) ● 0V CC V Reference Input Current In Shutdown ● 1 µA Switching Characteristics (VCC = 4.5V to 5.5V) t1 SDI Valid to SCK Setup ● 30 ns t2 SDI Valid to SCK Hold (Note 6) ● 0n s t3 SCK High Time (Note 6) ● 15 ns t4 SCK Low Time (Note 6) ● 15 ns t5 CS/LD Pulse Width (Note 6) ● 15 ns t6 LSB SCK to CS/LD (Note 6) ● 10 ns t7 CS/LD Low to SCK (Note 6) ● 10 ns t8 SD0 Output Delay C LOAD = 100pF ● 5 100 ns t9 SCK Low to CS/LD Low (Note 6) ● 10 ns t10 CLR Pulse Width (Note 6) ● 30 ns Switching Characteristics (VCC = 2.7V to 5.5V) t1 SDI Valid to SCK Setup ● 45 ns t2 SDI Valid to SCK Hold (Note 6) ● 0n s t3 SCK High Time (Note 6) ● 20 ns t4 SCK Low Time (Note 6) ● 20 ns t5 CS/LD Pulse Width (Note 6) ● 20 ns t6 LSB SCK to CS/LD (Note 6) ● 15 ns t7 CS/LD Low to SCK (Note 6) ● 15 ns

Note 4: DAC switched between code 2 kL and code 16383. See Applications Information (page 11) for definition of low code kL. Note 5: Digital inputs at 0V or VCC. Note 6: Guaranteed by design. Note 7: CS/LD = 0, VOUT = 4.096V and data is being clocked in. Note 8: 100pF load capacitor. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from low code kL to code 16383. See Applications Information (page 11). Note 3: Offset error is measured at low code k L. See Applications Information (page 11). TYPICAL PERFOR A CE CHARACTERISTICS UW Integral Nonlinearity (INL) vs Input Code INPUT CODE INL (LSB) 0.5 1.0 16383

1654 G01

–0.5 –1.0 –2.0 8192 –1.5 2.0 1.5 INPUT CODE DNL (LSB) 0.5 1.0 16383

1654 G02

–0.5 –1.0 –2.0 8192 –1.5 2.0 1.5 TEMPERATURE (°C) –55 OFFSET ERROR (mV) –1.25 1.25 125

1654 G03

–2.50 –25 53 5 65 95 2.50 Differential Nonlinearity (DNL) vs Input Code Offset vs Temperature Gain Error vs Temperature Minimum Output Voltage vs Load Current (Output Sinking) Minimum Supply Headroom vs Load Current (Output Sourcing) TEMPERATURE (°C) –55 GAIN ERROR (LSB) –2.5 2.5 125

1654 G04

–5.0 –25 53 5 65 95 5.0 OUTPUT SINK CURRENT (mA) OUTPUT PULL-DOWN VOLTAGE (V) 0.6 0.8 1.0

1645 G05

0.4 0.2 0.5 0.7 0.9 0.3 0.1 CODE: ALL ZEROS TA = 125°C TA = 25°C TA = –55 °C LOAD CURRENT (mA) VCC – VOUT (V)0.6 0.8 1.0

1645 G06

0.4 0.2 0.5 0.7 0.9 0.3 0.1 TA = 125°C CODE: ALL 1s VREFHI = 4.096V TA = 25°C TA = –55 °C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Characteristics (VCC = 2.7V to 5.5V) t8 SDO Output Delay C LOAD = 100pF ● 5 150 ns t9 SCK Low to CS/LD Low (Note 6) ● 15 ns t10 CLR Pulse Width (Note 6) ● 45 ns The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.

TYPICAL PERFOR A CE CHARACTERISTICS UW Supply Current vs Logic Input Voltage Large-Signal Settling—Fast Mode LOGIC INPUT VOLTAGE (V) SUPPLY CURRENT (mA) 1.5 3.0

1654 G07

Large-Signal Settling—Slow Mode Midscale Glitch—Fast Mode Midscale Glitch—Slow Mode V OUT Glitch at Power-Up VOUT 10mV/DIV CS/LD 2V/DIV TIME (1µs/DIV) 1654 G10 VOUT 10mV/DIV CS/LD 2V/DIV TIME (1µs/DIV) 1654 G11 VCC 0.5V/DIV TIME (50ms/DIV) 1654 G12 VOUT 50mV/DIV VOUT 1V/DIV CS/LD 2V/DIV TIME (2µs/DIV) 1654 G08 VOUT 1V/DIV CS/LD 2V/DIV TIME (2µs/DIV) 1654 G09

CS/LD (Pin 5): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the SCK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, the control/address bits are decoded. DGND/AGND (Pins 6, 12): Digital and Analog Grounds. SDO (Pin 7): The output of the shift register that becomes valid on the rising edge of the serial clock. V OUT A/B (Pins 9, 15): The Buffered DAC Outputs. REFHI A/B (Pins 10, 14): The Reference High Inputs of the LTC1654. There is a gain of 1 from this pin to the output in a gain of 1 configuration. In a gain of 1/2 configuration, there is a gain of 1/2 from this pin to VOUT. REFLO A/B (Pins 11, 13): The Reference Low Inputs of the LTC1654. These inputs can swing up to VCC – 1.5V. VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V. Requires a 0.1µF bypass capacitor to ground. X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of 1/2 Pin. When this pin is tied to VOUT, the output range will be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when REFLO = 0V). When this pin is tied to REFLO, the output range will be REFLO to REFHI (0V to REFHI when REFLO = 0V). These pins should not be left floating. CLR (Pin 2): The Asynchronous Clear Input. SCK (Pin 3): The TTL Level Input for the Serial Interface Clock. SDI (Pin 4): The TTL Level Input for the Serial Interface Data. Data on the SDI pin is latched into the shift register on the rising edge of the serial clock. The LTC1654 allows either a 24-bit or 32-bit word. When a 24-bit word is used, the first 8 bits are control and address followed by 16 data bits. The last two of the 16 data bits are don’t cares. When a 32-bit word (required for daisy-chain operation) is used, the first 8-bits are don’t cares and the following 24-bits are as above.

1654 TD01

(PREVIOUS WORD) TI I G DIAGRA SUW W UUUPI FU CTIO S

CONTROL BITS ADDRESS BITS DATA WORD 24-BIT DATA STREAM 1654TD02a B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X 24 25 26 27 28 29 30 31 32 C2 C1 C0 A3 A2 A1 A0 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 XX X X X X X X X X CS/LD SCK SDI CONTROL BITS ADDRESS BITS DATA WORD 32-BIT DATA STREAM DON’T CARE C2 C1 C0 A3 A2 A1 A0 XX X X X X X X X X SDO CURRENTSTREAM

1654 TD02b

Figure 1a. 24-Bit Load Sequence (for Non-Daisy-Chained Applications) Figure 1b. 32-Bit Load Sequence (for Single and Daisy-Chained LTC1654s)

The data on the SDI input is loaded into the shift register on the rising edge of SCK. The MSB is loaded first. The Clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. If no daisy-chaining is required, the input word can be 24-bit wide, as shown in the timing diagrams. The 8 MSBs, which are loaded first, are the control and address bits followed by a 16-bit data word. The last two LSBs in the data word are don’t cares. The input word can be a stream of three 8-bit wide segments as shown in the “24-Bit Update” timing diagram. If daisy-chaining is required or if the input needs to be written in two 16-bit wide segments, then the input word can be 32 bits wide and the top 8 bits (MSBs) are don’t cares. The remaining 24 bits are control/address and data. This is also shown in the timing diagrams. The buffered output of the internal 32-bit shift register is available on the SDO pin, which swings from GND to V CC. Multiple LTC1654s may be daisy-chained together by connecting the SDO pin to the SDI pin of the next IC. The SCK and CS/LD signals remain common to all ICs in the daisy-chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all DACs simultaneously. Table 1 shows the truth table for the control/address bits. When the supplies are first applied, the LTC1654 uses SLOW mode, the outputs are set at 0V, and zeros are loaded into the 32-bit input shift register. About 300ns after power-up, the outputs are released from 0V (AGND) and will go to the voltage on the REFLO pin. When CLR goes active, zeros are loaded into the input and DAC latch and the outputs are forced to AGND. After CLR is forced high, the ouputs will go to the voltage on the REFLO pin. Three examples are given to illustrate the DAC’s opera- tion: 1. Load and update DAC A in FAST mode. Leave DAC B unchanged. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in FAST mode CS/LD clock in 0101 0000 XXXXXXXX XXXXXXXX; CS/LD Step 2: Load and update DAC A with DATA CS/LD clock in 0011 0000 + DATA; CS/LD 2. Load and update DAC A in SLOW mode. Power down DAC B. Perform the following sequence for the con- trol, address and DATA bits: Step 1: Set DAC A in SLOW mode CS/LD clock in 0110 0000 XXXXXXXX XXXXXXXX; CS/LD Step 2: Load and update DAC A with DATA CS/LD clock in 0011 0000 + DATA; CS/LD Step 3: Power down DAC B CS/LD clock in 0100 0001 XXXXXXXX XXXXXXXX; CS/LD 3. Power down both DACs at the same time. Perform the following sequence for the control, address and DATA bits: Step 1: Power down both DACs simultaneously CS/LD clock in 0100 1111 XXXXXXXX XXXXXXXX; CS/LD OPERATIOU

The LTC1654 comes complete with rail-to-rail voltage output buffer amplifiers. These amplifiers will swing to within a few millivolts of either supply rail when unloaded and to within a 450mV of either supply rail when sinking or sourcing 5mA. There are two GAIN configuration modes for the LTC1654: a) GAIN of 1: (X 1/X1/2 tied to REFLO) VOUT = (VREFHI – VREFLO)(CODE/16384) + VREFLO b) GAIN of 1/2: (X 1/X1/2 tied to VOUT) VOUT = (1/2)(VREFHI – VREFLO)(CODE/16384) + VREFLO The LTC 1654 has two SPEED modes: A FAST mode and a SLOW mode. When operating in the FAST mode, the output amplifiers will settle in 3µs (typ) to 14 bits on a 4V output swing. In the SLOW mode, they will settle in 8.5µs. The total supply current is 930µA in the FAST mode and 540µA in the SLOW mode. The output noise voltage density at 10kHz is 170nV/ √Hz in SLOW mode and 150nV/√Hz in FAST mode. Power Down Each DAC can also be independently powered down to less than 5µA/DAC of supply current. The reference pin also goes into a high impedance state when the DAC is powered down and the reference current will drop to below 0.1µA. The amplifiers’ output stage is also three-stated but the V OUT pins still have the internal gain-setting resistors connected to them resulting in an effective resistance from VOUT to REFLO. This resistance is typically 90k when the X1/X1/2 pin is tied to VOUT and 36k when X1/X1/2 is tied to REFLO. Because of this resistance, VOUT will go to VREFLO when the DAC is powered down and VOUT is unloaded. OPERATIOU

Table 1. CONTROL C3 C2 C1 C0

0000 Load Input Register n

0001 U pdate (Power-Up) DAC Register n

0010 Load Input Register n, Update (Power-Up) All

0011 Load and Update n

0100 P o w e r D o w n n

0101 Fast n (Speed States are Maintained Even If DAC is

Put in Power-Down Mode)

0110 S l o w n ( D efault State is Slow When Supplies are

Powered Up)

0111 R eserved (Do Not Use)

1000 R eserved (Do Not Use)

1001 R eserved (Do Not Use)

1010 R eserved (Do Not Use)

1011 R eserved (Do Not Use)

1100 R eserved (Do Not Use)

1101 R eserved (Do Not Use)

1110 R eserved (Do Not Use)

1111 N o O peration

ADDRESS (n) A3 A2 A1 A0

0000 D A C A

0001 D A C B

0010 R eserved (Do Not Use)

0011 R eserved (Do Not Use)

0100 R eserved (Do Not Use)

0101 R eserved (Do Not Use)

0110 R eserved (Do Not Use)

1111 B oth DACs

CONTROL ADDRESS DATA (14 + 2 DON'T CARE LSBs) C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

1654 TABLE

CC or below ground. See Figure 2a. defined and tested in output ranges that avoid limiting. Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative

1654 F02

Table 2. Low Code kL

Figure 3. Effect of Negative Offset difference between two successive codes. part, this value cannot be less than 0V. voltage at the output when the DAC is loaded with all zeros. near 0V resulting in the transfer curve shown in Figure 3.

1654 F01

This circuit shows how to use an LTC1654 and an LT 1077 to make a wide bipolar output swing 14-bit DAC with an offset that can be digitally programmed. VOUTA, which can be set by loading the appropriate code for DAC A, sets the offset. As this value changes, the transfer curve for the output moves up and down as illustrated in the graph below. X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X 1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A LTC1654 0.1µF 49.9k

1654 TA02

µP 100k 49.9k V OUT 2 (VOUTB – VOUTA) 15V –15V 100k LT1077 VOUT0 VOUTA ≅ 0V VOUTA ≅ 2.5V VOUTA ≅ 5V CODE

1654 TA03

–10 16383 A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset TYPICAL APPLICATIO SU

X 1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A LTC1654 0.1µF 2.7V TO 5.5V OUTPUT B: 0V TO VCC OUTPUT A: 0V TO VCC

1654 TA01

µP Dual 14-Bit Voltage Output DAC TYPICAL APPLICATIO SU

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTIONU GN16 (SSOP) 0502 12 3 4 5 6 7 8 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 16 15 14 13 .189 – .196* (4.801 – 4.978) 12 11 10 9 .016 – .050 (0.406 – 1.270) .015 ± .004 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) .008 – .012 (0.203 – 0.305) .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .009 (0.229) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 TYP.0165 ± .0015 .045 ±.005 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641)

© LINEAR TECHNOLOGY CORPORATION 2000 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT/LT 0705 REV B • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit V OUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, 5V to 15V Single Supply, Complete V OUT DAC in Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V SO-8 Package LTC1446/LTC1446L Dual 12-Bit V OUT DACs in SO-8 Package LTC1446: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 Dual 12-Bit V OUT DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450/LTC1450L Single 12-Bit V OUT DACs with Parallel Interface LTC1450: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V CC: 4.5V to 5.5V, 5V, Low Power Complete V OUT DAC in SO-8 Package Internal 2.048V Reference Brought Out to Pin LTC1452 Single Rail-to-Rail 12-Bit V OUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying V OUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit V OUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete V OUT DAC in SO-8 Package LTC1454/LTC1454L Dual 12-Bit V OUT DACs in SO-16 Package with Added Functionality LTC1454: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Low Power, Complete V OUT DAC in SO-8 Full Scale: 4.095V, VCC: 4.5V to 5.5V Package with Clear Pin LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP, V CC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1659 Single Rail-to-Rail 12-Bit V OUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V Low Power, Multiplying V OUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC References LT1460 Micropower Precision Reference Low Cost, 10ppm Drift LT1461 Precision Voltage Reference Ultralow Drift 3ppm/ °C, Initial Accuracy: 0.04% LT1634 Micropower Precision Reference Low Drift 10ppm/ °C, Initial Accuracy: 0.05% X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X 1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A LTC1654 0.1µF 49.9k µP 100k 49.9k V OUT 2 (VOUTB – VOUTA) 15V –15V 100k LT1077 A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset TYPICAL APPLICATIO U