LTC1402_1 LINER
Document overview
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Technical content
Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown n Sample Rate: 2.2Msps n 72dB S/(N + D) and –89dB THD at Nyquist n Power Dissipation: 90mW (Typ) n 80MHz Full Power Bandwidth Sampling n No Missing Codes over Temperature n Available in 16-Pin Narrow SSOP Package n Single Supply 5V or –5V Operation n Nap Mode with Instant Wake-Up: 15mW n Sleep Mode: 10mW n True Differential Inputs Reject Common Mode Noise n Input Range (1mV/LSB): 0V to 4.096V or –2.048V n Internal Reference Can Be Overdriven Externally n 3-Wire Interface to DSPs and Processors (SPI and MICROWIRE TM Compatible) The LTC 1402 is a 12-bit, 2.2Msps sampling A/D con- verter. This high performance device includes a high dy- namic range sample-and-hold and a precision reference. It operates from a single 5V supply or dual –5V supplies and draws only 90mW from 5V. The versatile differential input offers a unipolar range of 4.096V and a bipolar range of –2.048V for dual supply systems where high performance op amps perform best, eliminating the need for special translation circuitry. The high common mode rejection allows users to elimi- nate ground loops and common mode noise by measuring signals differentially from the source. Outstanding AC performance includes 72dB S/(N + D) and –93dB SFDR at the Nyquist input frequency of 1.1MHz with dual –5V supplies and –84dB SFDR with a single 5V supply. The LTC1402 has two power saving modes: Nap and Sleep. Nap mode consumes only 15mW of power and can wake up and convert immediately. In Sleep mode, it typically consumes 10mW of power. Upon power-up from Sleep mode, a reference ready (REFRDY) signal is avail- able in the serial data word to indicate that the reference has settled and the chip is ready to convert. The 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcon- trollers and DSPs. A digital output driver power supply pin allows direct connection to 3V or lower logic. SAMPLE- AND-HOLD DOUT BIP/UNI CONV SCK OVDD DVDDAVDD11 2 1 1 GAIN 7 –5V OR 0V 10µF 10µF VREF 4.096V 10µF 64k OUTPUT BUFFER
1402 TA01
2.048 REFERENCE TIMING LOGIC AIN+ LTC1402 OGND962 DGND AIN– 5V 3V OR 5V AGND114 13 AGND2 64k 12-BIT ADC VSS MICROWIRE is a trademark of National Semiconductor Corp. , LTC and LT are registered trademarks of Linear Technology Corporation. n Telecommunications n High Speed Data and Signal Acquisition n Digitally Multiplexed Data Acquisition Systems n Digital Radio Receivers n Spectrum Analysis n Low Power and Battery-Operated Systems n Handheld or Portable Instruments n Imaging Systems
5 Harmonic THD, 2nd, 3rd and SFDR
vs Input Frequency (Unipolar) INPUT FREQUENCY (Hz) 104 105 106 107 –80THD, SFDR, 2ND 3RD (dB) –60 –40
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–100 –120 –20 –90 –70 –50 –110 –10 –30 THD SFDR 2ND 3RD fSAMPLE = 2.22MHz APPLICATIO SU DESCRIPTIO UFEATURES BLOCK DIAGRA W
16-LEAD NARROW PLASTIC SSOP AVDD AGND1 AIN+ AIN– VREF AGND2 GAIN BIP/UNI CONV SCK VSS DGND DV DD 0VDD DOUT OGND PACKAGE/ORDER INFORMATIONW UUABSOLUTE MAXIMUM RATINGSW WW U AVDD = DVDD = OVDD = VDD (Notes 1, 2) Analog Input Voltage Digital Input Voltage Operation Temperature Range ORDER PART NUMBER GN PART MARKING 1402 1402I Consult factory for Military grade parts. LTC1402CGN LTC1402IGN TJMAX = 125°C, qJA = 150°C/ W CONVERTER CHARACTERISTICSU The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference (Note 5). PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 Bits Integral Linearity Error (Note 6) l –0.35 –1L S B Differential Linearity (Note 6) l –0.25 –1L S B Offset Error (Note 6) l –2 – 10 LSB Full-Scale Error (Note 6) l –10 –15 LSB Full-Scale Tempco Internal Reference (Note 6) –15 ppm/ °C External Reference –1 ppm/ °C The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Differential Input Range (Notes 3, 11) Bipolar Mode with BIP/UNI High l – 2.048 V 4.75V £ VDD £ 5.25V Unipolar Mode with BIP/UNI Low l 0 to 4.096 V 4.75V £ VDD £ 5.25V – 5.25V £ VSS £ 0V VCM Analog Common Mode + Differential Dual –5V Supply –2.5 to 5 V Input Range (Note 12) Single 5V Supply 0 to 5 V IIN Analog Input Leakage Current l 1 mA CIN Analog Input Capacitance 10 pF tACQ Sample-and-Hold Acquisition Time (Note 9) l 57 ns tAP Sample-and-Hold Aperture Delay Time 2.6 ns tJITTER Sample-and-Hold Aperture Delay Time Jitter 1 ps CMRR Analog Input Common Mode Rejection Ratio f IN = 1MHz, VIN = 2V to – 2V – 62 dB fIN = 100MHz, VIN = 2V to –2V – 24 dB A ALOG I PUTU U
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Bipolar mode with – 5V supplies and unipolar mode with 5V supply. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N + D) Signal-to-Noise Plus 100kHz Input Signal 72.5 dB Distortion Ratio 1.1MHz Input Signal l 69 72.0 dB THD Total Harmonic 100kHz First 5 Harmonics, Bipolar Mode –89 dB Distortion 1.1MHz First 5 Harmonics, Bipolar Mode l –89 –74.5 dB 100kHz First 5 Harmonics, Unipolar Mode –87 dB 1.1MHz First 5 Harmonics, Unipolar Mode –82 dB SFDR Spurious Free 100kHz Input Signal, Bipolar Mode –93 dB Dynamic Range 1.1MHz Input Signal, Bipolar Mode –93 dB 100kHz Input Signal, Unipolar Mode –93 dB 1.1MHz Input Signal, Unipolar Mode –84 dB IMD Intermodulation –1V 1.25MHz into AIN+, 1.2MHz into AIN– Bipolar Mode –84 dB Distortion 1.5V to 3.5V 1.25MHz into A IN+, 1.2MHz into AIN– Unipolar Mode –84 dB Code-to-Code V REF = 4.096V, 1LSB = 1mV 0.18 LSB RMS Transition Noise Full Power Bandwidth V IN = 4VP-P, DOUT = 2828LSBP-P (Note 18) 82 MHz Full Linear Bandwidth S/(N + D) ‡ 68dB Bipolar Mode 5.0 MHz Unipolar Mode 3.5 MHz DYNAMIC ACCURACYU W The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) INTERNAL REFERENCE CHARACTERISTICSUU U PARAMETER CONDITIONS MIN TYP MAX UNITS VREF Output Voltage I OUT = 0 4.096 V VREF Output Tempco 15 ppm/ °C VREF Line Regulation AV DD = 4.75V to 5.25V, VREF = 4.096V 1 LSB/V VREF Output Resistance Load Current = 0.5mA 2 W VREF Settling Time 2m s The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage V DD = 5.25V l 2.4 V VIL Low Level Input Voltage V DD = 4.75V l 0.8 V IIN Digital Input Current V IN = 0V to VDD l – 10 mA CIN Digital Input Capacitance 5p F VOH High Level Output Voltage OV DD = 4.75V, IOUT = –10 mA 4.7 V OVDD = 4.75V, IOUT = – 200mA l 4V OVDD = 3V, IOUT = –200 mA l 2.5 2.9 V VOL Low Level Output Voltage V DD = 4.75V, IOUT = 160mA 0.05 V VDD = 4.75V, IOUT = 1.6mA l 0.10 0.4 V IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l – 10 mA COZ Hi-Z Output Capacitance DOUT 15 pF ISOURCE Output Short-Circuit Source Current V OUT = 0V, OVDD = 5V – 40 mA VOUT = 0V, OVDD = 3V – 15 mA ISINK Output Short-Circuit Sink Current V OUT = OVDD = 5V 40 mA DIGITAL I PUTS A D DIGITAL OUTPUTSU U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSAMPLE(MAX) Maximum Sampling Frequency (Conversion Rate) l 2.2 MHz tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) l 455 ns tSCK Minimum Clock Period l 28 10000 ns tCONV Conversion Time (Note 9) 14 SCK cycles t0 14th SCLK› to CONV› Interval (Notes 9, 10, 16) l 57 ns t1 Minimum Positive or Negative SCK Pulse Width (Note 9) l 3.8 6 ns t2 CONV to SCK Setup Time (Notes 9, 13) l 7.3 12 ns t3 SCK After CONV (Note 9) l 0n s t4 Minimum Positive or Negative CONV Pulse Width (Note 9) l 3.5 5 ns t5 SCK to Sample Mode (Note 9) l 91 4 n s t6 CONV to Hold Mode (Notes 9, 14) l 3.4 5 ns t7 Minimum Delay Between Conversions (Note 9) l 48 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 9, 15) l 91 2 n s t8a Minimum Delay from SCK to Valid REFREADY (Notes 9, 15) l 15 20 ns t9 SCK to Hi-Z at DOUT (Notes 9, 15) l 11.4 16 ns t10 Previous DOUT Bit Remains Valid After SCK (Notes 9, 15) l 47 n s t11 REFREADY Bit Delay After Sleep-to-Wake Transition (Notes 9, 17) l 10 ms t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 9, 17) l 2m s The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Positive Supply Voltage 4.75 5.25 V VSS Negative Supply Voltage –5.25 0 V IDD Positive Supply Current Active Mode l 18 30 mA Nap Mode l 35 m A Sleep Mode 2 10 mA ISS Negative Supply Current Active, Sleep or Nap Modes with SCK Off l 2 mA PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 90 150 mW POWER REQUIRE E TSW U Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together. Note 3: When these pins are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below V SS or greater than VDD without latchup. Note 4: When these pins are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or greater than VDD. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 2.2MHz, VSS = 0V for unipolar mode specifications and VSS = – 5V for bipolar specifications. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) Note 6: Linearity, offset and full-scale specifications apply for a single- ended AIN+ input with AIN– grounded and using the internal reference in bipolar mode with – 5V supplies. Note 7: Integral linearity is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 8: Bipolar offset is the offset measured from –0.5LSB when the input flickers between 1000 0000 0000 and 0111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The analog input range is defined as the voltage difference between AIN+ and AIN–. The bipolar –2.048V input range could be used with a single 5V supply if the absolute voltages of the inputs remain within the single 5V supply voltage. TI I G CHARACTERISTICSUW
Note 12: The absolute voltage at AIN+ and AIN– must be within this range. Note 13: If less than 7.3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns) because the 0.8ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 15: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch.
ELECTRICAL CHARACTERISTICS
Note 16: The time period for acquiring the input signal is started by the 14th rising clock and it is ended by the rising edge of convert. Note 17: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10mF capacitive load. The Sleep mode resets the REFREADY bit in the DOUT sequence. The REFREADY bit goes high again 10ms after the VREF has stopped slewing in wake up. This ensures valid REFREADY bit operation even with higher load capacitances at V REF. Note 18: The full power bandwidth is the frequency where the output code swing drops to 2828LSBs with a 4VP-P input sine wave. TYPICAL PERFOR A CE CHARACTERISTICS UW ENOBs and SINAD vs Input Frequency (Bipolar) SNR vs Input Frequency (Bipolar) ENOBs and SINAD vs Input Frequency (Unipolar) SNR vs Input Frequency (Unipolar) (Bipolar Mode Plots Run with Dual –5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. INPUT FREQUENCY (Hz) 104 105 106 107 EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE + DISTORTION (dB)
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fSAMPLE = 2.22MHz INPUT FREQUENCY (Hz) 104 105 106 107 –80THD, SFDR, 2ND 3RD (dB) –60 –40
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–100 –120 –20 –90 –70 –50 –110 –10 –30 THD SFDR 2ND 3RD fSAMPLE = 2.22MHz INPUT FREQUENCY (Hz) 104 105 106 107 –50 SNR (dB) –38 –26
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–62 –74 –14 –56 –44 –32 –68 –20 fSAMPLE = 2.22MHz INPUT FREQUENCY (Hz) 104 105 106 107 EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE + DISTORTION (dB)
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fSAMPLE = 2.22MHz INPUT FREQUENCY (Hz) 104 105 106 107 –80THD, SFDR, 2ND 3RD (dB) –60 –40 –100 –120 –20 –90 –70 –50 –110 –10 –30 THD SFDR 2ND 3RD fSAMPLE = 2.22MHz INPUT FREQUENCY (Hz) 104 105 106 107 –50 SNR (dB) –38 –26
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–62 –74 –14 –56 –44 –32 –68 –20 fSAMPLE = 2.22MHz
5 Harmonic THD, 2nd, 3rd and
(Bipolar) (Unipolar)
IMD Spectrum Plot (Bipolar) Sine Wave Spectrum Plot (Unipolar) 5V Supply FREQUENCY (MHz) –15 –20 AMPLITUDE (dB) –10 0.1 10 100 1000
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–25 100mVP-P 4VP-P Sine Wave Spectrum Plot (Bipolar) Dual –5V Supply IMD Spectrum Plot (Unipolar) FREQUENCY (MHz) AMPLITUDE (dB) –70 2ND 3RD 4TH 6TH–80 –90 –100 –110 –120 –10
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–30 –50 –20 –40 –60 0.55 1.11 5TH fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz
2048 SAMPLES
FREQUENCY (MHz) AMPLITUDE (dB) –70 2ND–80 –90 –100 –110 –120 –10
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–30 –50 –20 –40 –60 0.55 1.11 4TH 3RD 5TH 6TH fSAMPLE = 2222222.22Hz fSINE = 109592.01Hz (Bipolar) –5V Supply FREQUENCY (MHz) AMPLITUDE (dB) 0.59 1.18
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–10 –20 –30 –40 –50 –60 f A – fB fA – 2fB 2fA – fB 2fA + fB fA + 2fB 3fB fA – fB 2fB 2fA 3fA –70 –80 –90 –100 –110 –120 fSAMPLE = 2352941.18Hz fSINEA = 1250000Hz –1V INTO AIN+ fSINEB = 1199449Hz –1V INTO AIN– IMD = 83.9dB FREQUENCY (MHz) AMPLITUDE (dB) –70 2ND –80 –90 –100 –110 –120 –10
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–30 –50 –20 –40 –60 0.55 1.11 4TH 6TH 3RD 5TH fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz (Unipolar) 5V Supply FREQUENCY (MHz) AMPLITUDE (dB) –70 2ND –80 –90 –100 –110 –120 –10
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–30 –50 –20 –40 –60 0.55 1.11 4TH 6TH 3RD 5TH fSAMPLE = 2222222.22Hz fSINE = 109592.01Hz FREQUENCY (MHz) AMPLITUDE (dB) 0.59 1.18
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–10 –20 –30 –40 –50 –60 f A – fB 2fA – fB, fA + 2fB fA – 2fB 2fA + fBfA + fB 2fB 2fA 3fA –70 –80 –90 –100 –110 –120 fSAMPLE = 2352941.18Hz fSINEA = 1250000Hz INTO AIN+, 1.5V TO 3.5V f SINEB = 1199449Hz INTO AIN–, 1.5V TO 3.5V IMD = – 84.1dB
2048 SAMPLES 3f
B PSRR vs Frequency FREQUENCY (MHz) –60 REJECTION (dB) –40 –30 –10 0.1 10 100 1000
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–80 –20 –50 –70 VCC VSS VDD DGND Load Regulation for VREF LOAD CURRENT (mA) 4.040INTERNAL REFERENCE VOLTAGE (V)4.050 .4.060 4070 4.080 4.090 4.100 0.4 0.8 1.2 1.6
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2.0 TYPICAL PERFOR A CE CHARACTERISTICS UW (Bipolar Mode Plots Run with Dual –5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
AVDD (Pin 1): 5V Analog Power Supply. Bypass to AGND1 and solid analog ground plane with 10mF ceramic (or 10mF tantalum in parallel with 0.1mF ceramic). AGND1 (Pin 2): Analog Ground. Tie to solid analog ground plane. The analog ground plane should be solid and have no cuts near the LTC1402. AIN+ (Pin 3): Positive Analog Signal Input. 0V to 4.096V in unipolar mode and –2.048V in bipolar mode when AIN– is grounded. Both of these ranges operate fully differentially with respect to A IN– . (Note 3) AIN– (Pin 4): Negative Analog Signal Input. Can be grounded or driven differentially with AIN+. Identical to AIN+, except that it inverts the input signal. (Note 3) VREF (Pin 5): 4.096V Reference Voltage Output. Bypass to AGND1 and solid analog ground plane with 10mF ceramic (or 10mF tantalum in parallel with 0.1mF ceramic). AGND2 (Pin 6): Analog Ground Return for the Reference and Internal CDAC. AGND2 could be overdriven externally above ground. Tie to solid analog ground plane. Differential Nonlinearity vs Output Code (Unipolar) Integral Nonlinearity vs Output Code (Unipolar) Negative Power Supply Rejection for VREF Positive Power Supply Rejection for VREF CODE INL (LSB) 0.50 4096
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–0.50 –1.00 1024 2048 3072512 1536 2560 3584 1.00 –0.25 0.25 –0.75 0.75 fSAMPLE = 2.2MHz CODE DNL (LSB) 0.50 4096
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–0.50 –1.00 1024 2048 3072512 1536 2560 3584 1.00 –0.25 0.25 –0.75 0.75 fSAMPLE = 2.2MHz VSS (V) 4.065INTERNAL REFERENCE VOLTAGE (mV) 4.070 4.075 4.080 4.085 4.090 4.095 –4 –3 –2 –1
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VDD (V) 4.5 4.065INTERNAL REFERENCE VOLTAGE (mV) 4.070 4.075 4.080 4.085 4.090 4.095
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6.0 Differential Nonlinearity vs Output Code (Bipolar) Integral Nonlinearity vs Output Code (Bipolar) CODE INL (LSB) 0.50 4096
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–0.50 –1.00 1024 2048 3072512 1536 2560 3584 1.00 –0.25 0.25 –0.75 0.75 fSAMPLE = 2.2MHz CODE DNL (LSB) 0.50 4096
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–0.50 –1.00 1024 2048 3072512 1536 2560 3584 1.00 –0.25 0.25 –0.75 0.75 fSAMPLE = 2.2MHz TYPICAL PERFOR A CE CHARACTERISTICS UW (Bipolar Mode Plots Run with Dual –5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to 4.096V or tie to VREF to set the reference voltage to 2.048V. (Note 4) BIP/UNI (Pin 8): Tie to logic low to set the input range to unipolar mode or tie to logic high to set the input range to bipolar mode. (Note 4) OGND (Pin 9): Output Ground for the Output Driver. This pin can be tied to the digital ground of the system. All other ground pins should be tied to the analog ground plane. DOUT (Pin 10): Three-State Data Output. (Note 3) Each output data word represents the analog input at the start of the previous conversion. OVDD (Pin 11): Output Data Driver Power. Tie to VDD when driving 5V logic. Tie to 3V when driving 3V logic. DVDD (Pin 12): Digital Power for Internal Logic. Bypass to DGND with 10mF ceramic (or 10mF tantalum in parallel with 0.1mF ceramic). PIN FUNCTIONSUU U DGND (Pin 13): Digital Ground for Internal Logic. Tie to solid analog ground plane. VSS (Pin 14): Negative Supply Voltage. Bypass to solid analog ground plane with 10mF ceramic (or 10mF tantalum in parallel with 0.1mF ceramic) or tie directly to the solid analog ground plane for single supply use. Must be set more negative than either AIN+ or AIN – . Set to 0V or – 5V. SCK (Pin 15): External Clock. Advances the conversion process and sequences the output data at D OUT on the rising edge. Responds to 5V or 3V CMOS and to TTL levels. (Note 4). One or more pulses wake from Nap or Sleep. CONV (Pin 16): Holds the input analog signal and starts the conversion on the rising edge. Responds to 5V or 3V CMOS and to TTL levels. (Note 4). Two pulses with SCK in fixed high or fixed low state start Nap Mode. Four pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRA W 12-BIT CAPACITIVE DAC COMPREF AMP 2.048V REF 64k GAIN CSAMPLE CSAMPLE CONTROL LOGIC SCKCONV 16 15 INTERNAL CLOCK OUTPUT DRIVER ZEROING SWITCHES AVDD
12 DVDD
AIN– AGND1 AGND2 VREF DGND 1402 BD SUCCESSIVE APPROXIMATION REGISTER 64k
Nap Mode and Sleep Mode Waveforms SCK to DOUT Delay SCK CONV NAP SLEEP VREF t12 t11 REFRDY NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD. 1402 TD02 t10 SCK DOUT
1402 TD03
90% 10% SCK CONV INTERNAL S/H STATUS DOUT t7t3 123 45678 9 1 0 1 1 1 2 1 3 14 15 16 1 2 t8a t4 t5 SAMPLE SAMPLEHOLD HOLD Hi-Z Hi-Z tCONV REFRDY BIT + 12-BIT DATA WORD DOUT REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION tTHROUGHPUT 1402 TD01 REF D11 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10 REF
Figure 1. Acquisition Time vs Source Resistance LinearView is a trademark of Linear Technology Corporation. down Pin (Amplifier Draws 200mA While in Shutdown). AC specifications, 6mA supply current each amplifier. specifications. 70ns settling to 0.5LSB.
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common mode rejection of the sample-and-hold circuit. be 50ns for full throughput rate).
elliptic continuous-time 1MHz filter.
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Figure 2. RC Input Filter
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Figure 3. 1MHz Fifth Order Elliptic Lowpass Filter LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. mance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. applications where rail-to-rail performance is desired. Quad version is available as LT1633. type dielectric capacitors have excellent linearity.
5ms should be allowed after a reference adjustment. tion holds up at extremely high frequencies, see Figure 7. use of bipolar mode with single 5V supply.
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Figure 6. Driving VREF with a 12 Bit, VOUT DAC
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a 0.1mF ceramic is recommended. positive supply to disable the internal reference buffer. Figure 6. This is useful in applications where the peak Figure 4. LTC1402 Reference Circuit
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between VREF (Pin 5) and AGND2 (Pin 6). 4.096V to 0V-2.048V, for the same reference cut in half. range pivots around 0V with changing reference voltage. AIN– inputs, as shown in Figure 10b. Figure 8. Several LTC1402 ADCs Can Share a Single Figure 7. CMRR vs Input Frequency
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- For full-scale adjustment in Figures 10a and 10b,
enough output drive current for the 2kW load at each ADC. set and full-scale adjustment. Figure 9. LTC1402 Transfer Characteristic tant, offset and full-scale errors can be adjusted to zero.
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1402 F010b
1402 F010a
ground should be established under and around the ADC. grounds should be connected to this analog ground plane. side to cancel noise coupling. capacitors should be used at the V DD and V REF pins. tors in parallel with 0.1mF ceramic capacitors can be used. waveforms show the power-down modes for the LTC1402. Figure 11. Power Supply Grounding Practice
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scription of the three serial port signals follows. reference for the processor clock multiplier. used for substantial reductions in power consumption. Figure 12. Power Consumption vs Sample Rate
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by the next rising edge of SCK. the same jitter of the DSP’s master clock. CONV rising edge, and the CONV pulse is one clock wide. Figure 13. Serial to Parallel Interface
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Figure 14. DSP Serial Interface to TMS320C54x example of this interface using a TMS320C54X. time, at the full 2.2Msps conversion rate of the LTC1402. driven directly from the DSP.
1402 F14
APPLICATIONS INFORMATIONWU UU ; Files: BSP2KB.ASM -> ; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402 ; first element at 1024, last element at 1023, two middle elements at 2047 and 0000 ; bipolar mode .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.text”, 0x500,0 ;Set address of executable .setsect “vectors”, 0x180,0 ;Set address of incoming 1402 data .setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing .setsect “result”, 0x1800,0 ;Set address of result for clearing .text ;.text marks start of code start: ;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc tim=#0fh prd=#0fh tcr = #10h ; stop timer tspc = #0h ; stop TDM serial port to AC01 pmst = #01a0h ; set up iptr. Processor Mode STatus register sp = #0700h ; init stack pointer. dp = #0 ; data page ar2 = #1800h ; pointer to computed receive buffer. ar3 = #0800h ; pointer to Buffered Serial Port receive buffer ar4 = #0h ; reset record counter call sineinit ; Double clutch the initialization to insure a proper sinepeek: ; insert debugger break here to view results call sineinit ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. wait goto wait breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h) ; turn on halt for second half (bspce(bit15)) return_enable ; ———————mask and shift input data after 2k buffer is full——- bufull: b = *ar3+ << -2 ; load acc b with BSP buffer and shift right 2 b = #00FFFh & b ; mask out the REF bit and the 3 other tristate bits b = #00800h ^ b ; invert BIPOLAR MSB. Comment this line in UNIPOLAR mode *ar2+ = data(#0bh) ; store B to out buffer and advance AR2 pointer TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h if (TC) goto start ; restart if out buffer is at 1fffh goto bufull bsend return_enable ;this is a dummy return to define bsend ;in vector table below ;initialize buffered serial port * BSP initialization code for the ‘C54x DSKplus * * for use with 1402 in standard mode * * BSPC and SPC are the same in the ‘C542 * ON .set 1 OFF .set !ON YES .set 1 NO .set !YES BIT_8 .set 2 BIT_10 .set 1 BIT_12 .set 3 BIT_16 .set 0 GO .set 0x80
APPLICATIONS INFORMATIONWU UU * This is an example of how to initialize the Buffered Serial Port (BSP). * The BSP is initialized to require an external CLK and FSX for * operation. The data format is 16-bits, burst mode, with autobuffering * enabled. *Timing at BSP pins in DSKPLUS TMS320c542 board with inverters at BCLKR and BFSR. * *BDR Pin JP1-26 -_—_—<REF-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—_—<REF-B11- * * * *A 2 place right shift is needed to right justify the input data. * *The REF bit is also be masked in this example * Loopback .set NO ;(digital looback mode?) DLB bit Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit IntSync .set NO ;(internal Frame syncs generated?) TXM bit IntCLK .set NO ;(internal clks generated?) MCM bit BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT) PCM_Mode .set NO ;(Turn on PCM mode?) CLK_polarity .set YES ;(change polarity)for BCLKR YES=_/^, NO=~\\_ Frame_ignore .set !YES ;(inverted !YES -ignores frame) XMTautobuf .set NO ;(transmit autobuffering) RCVautobuf .set YES ;(receive autobuffering) XMThalt .set NO ;(transmit buff halt if XMT buff is full) RCVhalt .set NO ;(receive buff halt if RCV buff is full) XMTbufAddr .set 0x800 ;(address of transmit buffer) XMTbufSize .set 0x000 ;(length of transmit buffer) RCVbufAddr .set 0x800 ;(address of receive buffer) RCVbufSize .set 0x800 ;(length of receive buffer)works up to 800 .eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval .eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format & 1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval .eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval sineinit: bspc = #SPCval ; places buffered serial port in reset ifr = #10h ; clear interrupt flags imr = #210h ; Enable HPINT,enable BRINT0 intm = 0 ; all unmasked interrupts are enabled. bspce = #SPCEval ; programs BSPCE and ABU axr = #XMTbufAddr ; initializes transmit buffer start address bkx = #XMTbufSize ; initializes transmit buffer size arr = #RCVbufAddr ; initializes receive buffer start address bkr = #RCVbufSize ; initializes receive buffer size bspc = #(SPCval | GO) ; bring buffered serial port out of reset return ;for transmit and receive because GO=0xC0 .space 16*32 ;clear a chunk at the end to mark the end ; VECTORS .sect “vectors” ;The vectors start here ;get BSP vectors ; Vector Table for the ‘C54x DSKplus ; BSP vectors and Debugger vectors ; TDM vectors just return
; The vectors in this table can be configured for processing external and ; internal software interrupts. The DSKplus debugger uses four interrupt ; vectors. These are RESET, TRAP2, INT2, and HPIINT. ; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * ; All other vector locations are free to use. When programming always be sure ; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and ; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the ; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally. .mmregs reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER * nop nop nmi return_enable ;04; non-maskable external interrupt nop nop nop trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER * nop nop .space 52*16 ;0C-3F: vectors for software interrupts 18-30 int0 return_enable ;40; external interrupt int0 nop nop nop int1 return_enable ;44; external interrupt int1 nop nop nop int2 return_enable ;48; external interrupt int2 nop nop nop tint return_enable ;4C; internal timer interrupt nop nop nop brint goto breceive ;50; BSP receive interrupt nop nop nop bxint goto bsend ;54; BSP transmit interrupt nop nop nop trint return_enable ;58; TDM receive interrupt nop nop nop txint return_enable ;5C; TDM transmit interrupt nop nop int3 return_enable ;60; external interrupt int3 nop nop nop hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER * nop nop .space 24*16 ;68-7F; reserved area .sect “buffer” ;Set address of BSP buffer for clearing .space 16*0x800 .sect “result” ;Set address of result for clearing .space 16*0x800 .end APPLICATIONS INFORMATIONWU UU
Figure 15. The LTC1402 3-Wire Serial Port Sends Data Over 100 Feet of Category-5
16 VDD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF PACKAGE DESCRIPTIONU Dimensions in inches (millimeters) unless otherwise noted. 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641)
1402f LT/TP 0800 4K • PRINTED IN USA ª LINEAR TECHNOLOGY CORPORA TION 1 999 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear-tech.com RELATED PARTS PART NUMBER RESOLUTION SPEED COMMENTS 16-Bit LTC1604 16 333ksps –2.5V Input Range, –5V Supply LTC1605 16 100ksps –10V Input Range, Single 5V Supply LTC1606 16 250ksps –10V Input Range, Pin-Compatible with LTC1605 LTC1608 16 500ksps –2.5V Input Range, Pin-Compatible with LTC1604 14-Bit LTC1414 14 2.2Msps 175mW, 80dB SINAD and 95dB SFDR LTC1419 14 800ksps 150mW, 81.5dB SINAD and 95dB SFDR LTC1416 14 400ksps 75mW, Low Power with Excellent AC Specs LTC1418 14 200ksps 15mW, Single 5V, Serial/Parallel I/O 12-Bit LTC1412 12 3Msps 150mW, 72dB SINAD and 82dB SFDR LTC1410 12 1.25Msps 150mW, 71.5dB SINAD and 84dB THD LTC1415 12 1.25Msps 55mW, Single 5V Supply LTC1409 12 800ksps 80mW, 71.5dB SINAD and 84dB THD LTC1404 12 600ksps High Speed Serial I/O in SO-8 Package LTC1400 12 400ksps High Speed Serial I/O in SO-8 Package PART NUMBER DESCRIPTION COMMENTS References LT1019-2.5 Precision Band Gap Voltage Reference 3ppm/ °C Drift, 0.5% Max Initial Accuracy LT1460-2.5 Micropower Series Voltage Reference 0.075% Initial Accuracy, 10ppm/ °C Max Drift LT1461-2.5 Precision Voltage Reference 3ppm/ °C Drift, 0.05% Max Initial Accuracy DACs LTC1451 12-Bit V OUT DAC SO-8 Package, 12-Bit Monotonic Overtemperature LTC1452 12-Bit V OUT Multiplying DAC SO-8 Package, 2.7V to 5.5V Operation LTC1456 12-Bit V OUT DAC 0.5LSB DNL, SO-8 Package, Internal Reference