1338-18DCGI8

1338_V01 RENESAS

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 24

Technical content

Features

• Real-Time Clock (RTC) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100
• 56-byte battery-backed Non-Volatile RAM for data storage
• Fast mode I2C serial interface
• Automatic power-fail detect and switch circuitry
• Programmable square-wave output
• Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC (surface-mount package with an integrated crystal)
• Industrial temperature range (-40°C to +85°C) Block Diagram VCC GND VBAT SCL SDA Crystal inside package for 16-pin SOIC ONLY 1Hz / 4.096kHz / 8.192kHz / 32.768kHz SQW/OUT Power Control I2C Interface 32.768kHz Oscillator and Divider Control Logic MUX/ Buffer Clock, Calendar Counter

56 Byte

1 Byte

7 Bytes

Real-Time Clock with Battery Backed Non-Volatile RAM 1338 Datasheet

2©2008–2023 Renesas Electronics Corporation December 14, 2023

1338 Datasheet

Pin Assignment (8-pin MSOP/8-pin SOIC) Pin Assignment (16-pin SOIC) Pin Descriptions SCL SQW/OUT GND VCC1

5 SDA

V BAT IDT 1338 161 152 143 134 8 9 SCL VCC NC NC NC NC NC NC NC NC NC NC SDA GNDSQW/OUT V BAT IDT 1338C Pin Number Pin Name Pin Description/Function 8MSOP, 8SOIC 16SOIC 1 - X1 Connections for standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. An external 32.768kHz oscillator can also drive the IDT1338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left floating. 2 - X2 3 14 VBAT Backup Supply Input for Lithium Coin Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes placed in series between the backup source and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be connected to ground. 4 15 GND Connect to ground. 5 16 SDA Serial data input/output. SDA is the input/output pin for the I2C serial interface. It is an open-drain output and requires an external pull-up resistor (2kOhm typical). 6 1 SCL Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an open-drain output and requires an external pull-up resistor (2kOhm typical) 7 2 SQW/OUT Square-Wave/Output driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is an open drain output and requires an external pull-up resistor (10K ohm typical). Operates when the device is powered with VCC or VBAT. 8 3 VCC Device power supply. When voltage is applied within specified limits, the device is fully accessible by I2C and data can be written and read. - 4 – 13 NC No connect. These pins are unused and must be connected to ground for proper operation.

3©2008–2023 Renesas Electronics Corporation December 14, 2023 The following sections discuss in detail the Oscillator block, Power Control block, Clock/Calendar Register Block and Serial I 2C block. Oscillator Block Selection of the right crystal, correct load capacitance and careful PCB layout are important for a stable crystal oscillator. Due to the optimization for the lowest possible current in the design for these oscillators, losses caused by parasitic currents can have a significant impact on the overall oscillator performance. Extra care needs to be taken to maintain a certain quality and cleanliness of the PCB. Crystal Selection The key parameters when selecting a 32 kHz crystal to work with 1338 RTC are:

• Recommended Load Capacitance
• Crystal Effective Series Resistance (ESR)
• Frequency Tolerance Effective Load Capacitance Please see diagram below for effective load capacitance calculation. The effective load capacitance (CL) should match the recommended load capacitance of the crystal in order for the crystal to oscillate at its specified parallel resonant frequency with 0ppm frequency error. In the above figure, X1 and X2 are the crystal pins of our device. Cin1 and Cin2 are the internal capacitors which include the X1 and X2 pin capacitance. Cex1 and Cex2 are the external capacitors that are needed to tune the crystal frequency. Ct1 and Ct2 are the PCB trace capacitances between the crystal and the device pins. CS is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). Cex1 and Cex2 are not needed if the crystal circuit uses the recommended crystal with specified load capacitance (CL) of 12.5pF. Note: 1338CSRI integrates a standard 32.768 kHz crystal in the package and contributes an additional frequency error of 10ppm at nominal VCC (+3.3 V) and TA=+25°C. CPU X1 X2 VCC SQW/OUT VBAT GND SDA SCL CRYSTAL IDT1338 VCC 2k2k VCCVCC 10k

4©2008–2023 Renesas Electronics Corporation December 14, 2023 ESR (Effective Series Resistance) Choose the crystal with lower ESR. A low ESR helps the crystal to start up and stabilize to the correct output frequency faster compared to high ESR crystals. Frequency Tolerance The frequency tolerance for 32kHz crystals should be specified at nominal temperature (+25°C) on the crystal manufacturer datasheet. The crystals used with 1338 typically have a frequency tolerance of ±20ppm at +25°C. Specifications for a typical 32kHz crystal used with our device are shown in the table below. PCB Design Consideration

• Signal traces between the device pins and the crystal must be kept as short as possible. This minimizes parasitic capacitance and sensitivity to crosstalk and EMI. Note that the trace capacitances play a role in the effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. Crosstalk from these signals may disturb the oscillator signal.
• Reduce the parasitic capacitance between X1 and X2 signals by routing them as far apart as possible.
• The oscillation loop current flows between the crystal and the load capacitors. This signal path (crystal to CL1 to CL2 to crystal) should be kept as short as possible and ideally be symmetric. The ground connections for both capacitors should be as close together as possible. Never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and EMI.
• To reduce the radiation / coupling from oscillator circuit, an isolated ground island on the GND layer could be made. This ground island can be connected at one point to the GND layer. This helps to keep noise generated by the oscillator circuit locally on this separated island. The ground connections for the load capacitors and the oscillator should be connected to this island. PCB Layout PCB Assembly, Soldering and Cleaning Board-assembly production process and assembly quality can affect the performance of the 32kHz oscillator. Depending on the flux material used, the soldering process can leave critical residues on the PCB surface. High humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. These process residuals cause the insulation of the sensitive oscillator signal lines towards each other and neighboring signals on the PCB to decrease. High humidity can lead to moisture condensation on the surface of the PCB and, together with process residuals, reduce the surface resistivity of the board. Flux residuals on the board can cause leakage current paths, especially in humid environments. Thorough PCB cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. In general, reduction of losses in the oscillator circuit leads to better safety margin and reliability. Parameter Symbol Min Typ Max Units Nominal Freq. fO 32.768 kHz Series Resistance ESR 110 k Load Capacitance CL 12.5 pF

“Power-Up/Down Timing” diagram). Table 1. Power Control Table 2. Power-up/down Characteristics Note 2: Measured at typical VBAT level.

main registers during a read. Table 3. RTC and RAM Address Map Note: Bits listed as “0” should always be written and read as 0. BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. required, which decreases V BAT current. result in undefined operation. address pointer rolls over to zero. provided the oscillator is already running. re-initialized to the new format.

case of an update of the main registers during a read. Table 4. Control Register (07H) The control register controls the operation of the SQW/OUT pin and provides oscillator status. = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0. 1) The first time power is applied. 2) The voltage present on VCC and VBAT are insufficient to support oscillation. 3) The CH bit is set to 1, disabling the oscillator. 4) External influences on the crystal (i.e., noise, leakage, etc.). VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits. Table 5. Square Wave Output

0 X X 0 0

1 X X 1 0

8©2008–2023 Renesas Electronics Corporation December 14, 2023 The 1338 supports the I 2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The 1338 operates as a slave on the I 2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The 1338 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see the “Data Transfer on I 2C Serial Bus” figure):

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Timeout: Timeout is where a slave device resets its interface whenever Clock goes low for longer than the timeout, which is typically 35msec. This added logic deals with slave errors and recovering from those errors. When timeout occurs, the slave interface should re-initialize itself and be ready to receive a communication from the master, but it will expect a Start prior to any new communication.

9©2008–2023 Renesas Electronics Corporation December 14, 2023 Data Transfer on I2C Serial Bus Depending upon the state of the R/ W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The 1338 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see the “Data Write–Slave Receiver Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit 1338 address, which is 1101000, followed by the direction bit (R/ W), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the 1338 acknowledges the slave address + write bit, the master transmits a register address to the 1338. This sets the register pointer on the 1338, with the 1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the 1338 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the 1338 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see the “Data Read–Slave Transmitter Mode” figure). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit 1338 address, which is 1101000, followed by the direction bit (R/ W), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The 1338 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The 1338 must receive a “not acknowledge” to end a read.

10©2008–2023 Renesas Electronics Corporation December 14, 2023 Data Write – Slave Receiver Mode Data Read (from current Pointer location) – Slave Transmitter Mode Data Read (Write Pointer, then Read) – Slave Receive and Transmit

11©2008–2023 Renesas Electronics Corporation December 14, 2023 Handling, PCB Layout, and Assembly The IDT1338 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning equipment should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All NC (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during re-flow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 1338. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended DC Operating Conditions (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) Item Rating Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V Storage Temperature -55 to +125C Soldering Temperature 260C Parameter Symbol Min. Typ. Max. Unit Ambient Operating Temperature TA -40 - +85 C VBAT Input Voltage, Note 2 VBAT 1.3 3.0 3.7 - Pull-up Resistor Voltage (SQW/OUT), Note 2 VPU - - 5.5 V Logic 1, Note 2 VIH 0.8VCC - VCC + 0.3 V Logic 0, Note 2 VIL -0.3 - +0.2VCC V Supply Voltage 1338-18 VCC VPF 1.8 5.5 V1338-31 VPF 3.3 5.5 Power Fail Voltage 1338-18 VPF

12©2008–2023 Renesas Electronics Corporation December 14, 2023 (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) (VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0V, TA = +25°C, unless otherwise noted.) (Note 1) Parameter Symbol Conditions Min. Typ. Max. Unit Input Leakage ILI Note 3 - - 1 µA I/O Leakage ILO Note 4 - - 1 µA SDA Logic 0 Output IOLSDA VCC > 2V; VOL = 0.4V - - 3.0 mA VCC < 2V; VOL = 0.2VCC - - 3.0 SQW/OUT Logic 0 Output IOLSQW VCC > 2V; VOL = 0.4V - - 3.0 mA 1.71V < VCC < 2V; VOL = 0.2VCC - - 3.0 mA 1.3V < VCC < 1.71V; VOL = 0.2VCC - - 250 µA Active Supply Current (Note 5) ICCA 1338-18 - 7.5 15 µA 1338-31; VCC < 3.63V - 12 20 1338-31; 3.63V < VCC < 5.5V - 14 25 Standby Current (Note 6) ICCS 1338-18 - 1 2 µA 1338-31; VCC < 3.63 V - 1 2 1338-31; 3.63V < VCC < 5.5V - 2 5 VBAT Leakage Current (VCC Active) IBATLKG - - 25 100 nA Parameter Symbol Conditions Min. Typ. Max. Unit VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT OFF IBATOSC1 Note 7 - 800 1200 nA VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT ON IBATOSC2 Note 7 - 1025 1400 nA VBAT Data-Retention Current (OSC OFF); VBAT = 3.7V IBATDAT Note 7 - 120 300 nA

13©2008–2023 Renesas Electronics Corporation December 14, 2023 (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C) (Note 1) WARNING: Negative undershoots below -0.3V while the device is in battery-backed mode may cause loss of data. Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: All voltages referenced to ground. Note 3: SCL only. Note 4: SDA and SQW/OUT. Note 5: ICCA—SCL clocking at max frequency = 400kHz. Note 6: Specified with the I2C bus inactive. Note 7: Measured with a 32.768kHz crystal on X1 and X2. Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Parameter Symbol Conditions Min. Typ. Max. Unit SCL Clock Frequency fSCL Fast Mode 100 - 400 kHz Standard Mode 0 - 100 Bus Free Time Between a STOP and START Condition tBUF Fast Mode 1.3 - - µs Standard Mode 4.7 - - Hold Time (Repeated) START Condition, Note 8 tHD:STA Fast Mode 0.6 - - µs Standard Mode 4.0 - - Low Period of SCL Clock tLOW Fast Mode 1.3 - - µs Standard Mode 4.7 - - High Period of SCL Clock tHIGH Fast Mode 0.6 - - µs Standard Mode 4.0 - - Setup Time for a Repeated START Condition tSU:STA Fast Mode 0.6 - - µs Standard Mode 4.7 - - Data Hold Time (Notes 9, 10) tHD:DAT Fast Mode 0 - 0.9 µs Standard Mode 0 - - Data Setup Time (Note 11) tSU:DAT Fast Mode 100 - - ns Standard Mode 250 - - Rise Time of Both SDA and SCL Signals (Note 12) tR Fast Mode 20 + 0.1CB - 300 ns Standard Mode - - 1000 Fall Time of Both SDA and SCL Signals (Note 12) tF Fast Mode 20 + 0.1CB - 300 ns Standard Mode - - 300 Setup Time for STOP Condition tSU:STO Fast Mode 0.6 - - µs Standard Mode 4.0 - - Capacitive Load for Each Bus Line (Note 12) CB - - - 400 pF I/O Capacitance (SDA, SCL) CI/O Note 13 - - 10 pF Oscillator Stop Flag (OSF) Delay tOSF Note 14 - 100 - ms

14©2008–2023 Renesas Electronics Corporation December 14, 2023 Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released. Note 12: CB—total capacitance of one bus line in pF. Note 13: Guaranteed by design. Not production tested. Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V < VCC < VCCMAX and 1.3V < VBACKUP < 3.7V. Timing Diagram

15©2008–2023 Renesas Electronics Corporation December 14, 2023 Typical Operating Characteristics IBAT vs VBAT (IDT1338-31) 494 534 574 614 654 694 734 VBat (V) Supply current (nA) SQWE=1 SQWE=0 Icc vs Vcc (IDT1338-31) Vcc (V) Supply Current (uA) SCL=400kHz SCL=0Hz IBAT vs Temperature 400 500 600 700 800 -40 -20 0 20 40 60 80 Temperature (C) IBAT (nA) SQWE=1 SQWE=0 Oscillator Frequency vs Supply Voltage 32767.750000 32767.800000 32767.850000 32767.900000 32767.950000 Os cillator Supply Voltage (V) Frequency (Hz) Freq

16©2008–2023 Renesas Electronics Corporation December 14, 2023 Thermal Characteristics for 8MSOP Thermal Characteristics for 8SOIC Thermal Characteristics for 16SOIC Parameter Symbol Conditions Min. Typ. Max. Unit Thermal Resistance Junction to Ambient JA Still air - 95 - C/W Thermal Resistance Junction to Case JC - - 48 - C/W Parameter Symbol Conditions Min. Typ. Max. Unit Thermal Resistance Junction to Ambient JA Still air - 150 - C/W JA 1 m/s air flow - 140 - C/W JA 3 m/s air flow - 120 - C/W Thermal Resistance Junction to Case JC - - 40 - C/W Parameter Symbol Conditions Min. Typ. Max. Unit Thermal Resistance Junction to Ambient JA Still air - 120 - C/W JA 1 m/s air flow - 115 - C/W JA 3 m/s air flow - 105 - C/W Thermal Resistance Junction to Case JC - - 58 - C/W

17©2008–2023 Renesas Electronics Corporation December 14, 2023 Marking Diagram (8MSOP) Marking Diagram (8SOIC) Notes: 1. ‘$’ is the assembly mark code. 2. ‘’ is the lot sequence. 3. ‘YYWW’ is the last two digits of the year and week that the part was assembled. 4. “G” denotes RoHS compliant package. 5. “I” denotes industrial grade. 6. Bottom marking: Lot number. Marking Diagram (16SOIC) 38GI YYWW$ IDT1338-31DVGI IDT1338 -31DCGI YYWW$ IDT1338-31DCGI IDT1338 -18DCGI YYWW$ IDT1338-18DCGI 1 8 916 IDT 1338AC-31 SRGI YYWW$ IDT1338AC-31SRGI 1 8 916 IDT 1338AC-18 SRGI YYWW**$ IDT1338AC-18SRGI

18©2008–2023 Renesas Electronics Corporation December 14, 2023 The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document.

Ordering Information

The 1338 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS requirements. The lead finish is JESD91 category e3. “A” is the device revision designator and will not correlate to the datasheet revision. Part / Order Number Carrier Type Package Temperature Range 1338-18DCGI Tubes 8-pin SOIC -40 to +85 C 1338-18DCGI8 Tape and Reel 8-pin SOIC -40 to +85 C 1338AC-18SRGI Tubes 16-pin SOIC -40 to +85 C 1338AC-18SRGI8 Tape and Reel 16-pin SOIC -40 to +85 C 1338-31DVGI Tubes 8-pin MSOP -40 to +85 C 1338-31DVGI8 Tape and Reel 8-pin MSOP -40 to +85 C 1338-31DCGI Tubes 8-pin SOIC -40 to +85 C 1338-31DCGI8 Tape and Reel 8-pin SOIC -40 to +85 C 1338AC-31SRGI Tubes 16-pin SOIC -40 to +85 C 1338AC-31SRGI8 Tape and Reel 16-pin SOIC -40 to +85 C

19©2008–2023 Renesas Electronics Corporation December 14, 2023

Revision History

Date Description of Change December 14, 2023 Updated AC Electrical Characteristics Rise/Fall Time parameters; removed Standard Mode minimum value. February 3, 2023 Updated POD links in Package Outline Drawings.

• Rebranded/reformatted datasheet to Renesas. November 12, 2014 Updated device markings. March 10, 2014 Changed tVCCF min value from 300µs to 3ms. Added associated note. February 07, 2013 1. Changed the Vih Min value to 0.8Vcc and the Vil Max value to +0.2Vcc on page 11. This is based on new data taken on TSMC samples (old data was from Fab 4). 2. The IBATDAT current on page 12 should change from 10nA to 120nA (Typ) and from 100nA to 300nA (Max) per latest Characterization data from TSMC. December 10, 2012 Updated orderable parts - added “G” to 16-pin SOIC parts with SRI/SRI8. New part numbers for 16-pin SOIC will read as SRGI and SRGI8. September 20, 2012 1. Moved all from Fab4 to TSMC. QA requested change in the marking of only the 16-pin SOIC device with internal crystal to add “A” due to the fact that TSMC uses a different crystal than Fab4. Notification of a change in orderables was initiated with PCN A1208-06. 2. Updated 16-pin SOIC marking diagram and ordering information to include “A”. October 17, 2011 Added separate item for tVCCF in “Power-up/Down Conditions” table for 1338-31; 300µs min. September 22, 2011 Changed “VCC Fall Time; VPF(MAX) to VPF(MIN)” spec from 300µs Min. to 1ms Min. (Table 2, “Power-Up/Down Characteristics). April 13, 2011 Updated Supply Current specifications. March 29, 2010 Added “Timeout” paragraph on page 8. November 10, 2009 Added “Handling, PCB Layout, and Assembly” section. December 02, 2008 Updated Typical Operating Characteristics graphs; added marking diagrams. November 13, 2008 Updated graphs in “Typical Operating Characteristics; added “Typical Operating Circuit” diagram. November 10, 2008 Updated Block Diagram; Typical Operating Characteristics charts. May 9, 2008 The part number for 16pin RoHS complaint part has now changed from 1338C-31SOGI to 1338C-31SRI and the 1338C-18SOGI changed to 1338C-18SRI. April 03, 2004 Combined -3 and -33 parts to -31. March 28, 2008 Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices. January 29, 2008 New device. Preliminary release.

RECOMMENDED LAND PATTERN(PCB Top View, SMD Design) 1Index Area Seating PlanecccC See Detail A Side View Gage PlaneDetail A(Rotated 90° CW) D EHE AA2A1 eb h θ°0° Min0.25LLP Section A-A AA h R0.07 MIN θ1° θ1° With PlatingBase Metalbcb1c1 3.810.610.38 3.813.617.166.96 1.27 © Renesas Electronics Corporation

© Renesas Electronics Corporation Feb 25, 2016Rev 00Initial ReleaseNov 4, 2021Rev 01Added Land PatternDate CreatedRev no.DescriptionPackage Revision History

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