10XS3412

MC10XS3412 NXP

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Features

• Four protected 10 mΩ and 12 mΩ high-side switches (at 25 °C)
• Operating voltage ra nge of 6.0 to 20 V with sleep current < 5.0 μA, extended mode from 4.0 to 28 V
• 8 . 0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy chain capability
• PWM module using external clock or calibratable internal oscillator with programmable outputs delay management
• Smart overcurrent shutdown, sev ere short-circuit, overtemperature protection with time limited autoretry, and Fail-safe mode in case of MCU damage
• Output OFF or ON ope nload detection compliant to bulbs or LEDs and short to battery detection
• Analog current feedback with selectable ratio and board temper ature feedback

Figure 1. 10XS3412 simplified application diagram

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1 Orderable parts

2 Device variations

Table 1. Orderable part variations

1. To order parts in tape and reel, add the R2 suffix to the par t number.

Table 2. Device variations

• 10XS3412CHFK
• 10XS3412JHFK VCL(WAKE) 19 V Fault detection blanking time
• 10XS3412CHFK
• 10XS3412JHFK tFAULT - 5.0 5.0 μs Output shutdown delay time
• 10XS3412CHFK
• 10XS3412JHFK tDETECT - 7.0 7.0 μs Peak Package Reflow Temperature During Reflow, (2),(3)
• 10XS3412CHFK
• 10XS3412JHFK TPPRT Note 3 °C Notes 2. Pin soldering temperature li mit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics.

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3 Internal block diagram

Figure 2. 10XS3412 simplified internal block diagram

4 Pin connections

Figure 3. 10XS3412 pin connections Table 3. 10XS3412 pin definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

1 CSNS Output Output current

temperature feedback is SPI programmable. to directly control HS0 : HS3 high-side output pins.

7 FS Output Fault status

8 WAKE Input Wake This input pin controls the device mode. as place the device in a low-current Sleep mode.

10 CS Input Chip select

(active low) This input pin is connected to a chip select output of a master microcontroller (MCU). MCU or to the SO pin of the previous device of a daisy-chain of devices. device. These ground pins must be also shorted in the board.

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pin of the next device of a daisy-chain of devices. 4, 20 NC N/A No connect These pins may not be connected. 24 FSI Input Fail-safe input This input enables the watchdog timeout feature. Table 3. 10XS3412 pin definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

5 Electrical characteristics

5.1 Maximum ratings

Table 4. Maximum ratings

• Load dump at 25 °C (400 ms)
• Maximum operating voltage
• Reverse battery at 25 °C (2.0 min.) VPWR(SS) -18 V VDD supply voltage range VDD -0.3 to 5.5 V Input / output voltage (7) -0.3 to VDD + 0.3 V WAKE input clamp current ICL(WAKE) 2.5 mA CSNS input clamp current ICL(CSNS) 2.5 mA HS [0:3] voltage
• Positive
• Negative VHS[0:3] 41 -16 V Output current(4) IHS[0:3] 6 A Output clamp energy using Single-pulse method(5) ECL [0:3] 100 mJ ESD Voltage(6)
• Human Body Model (HBM) for HS[0:3], VPWR and GND
• Human Body Model (HBM) for other pins
• Charge Device Model (CDM) Corner pins (1, 13, 19, 21) All other pins (2-12, 14-18, 20, 22-24) VESD1 VESD2 VESD3 VESD4 ± 8000 ± 2000 ± 750 ± 500 V THERMAL RATINGS Operating temperature
• Ambient
• Junction TA TJ - 40 to 125 - 40 to 150 Storage temperature TSTG - 55 to 150 °C Notes 4. Continuous high-side output cur rent rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 5. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150°C initial). 6. ESD testing is performed in accordance with the Human Body Mo del (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 7. Input / Output pins are: IN[0:3], RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB

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• Junction to Case
• Junction to Ambient RθJC RθJA <1.0 °C/ W Peak Package Reflow Temperature During Reflow(9), (10)
• 10XS3412CHFK
• 10XS3412JHFK TPPRT Note 9 Notes 8. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of RθJA can be reached in a real application case (4 layers board). 9. Pin soldering temperature li mit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 10. NXP’s Package Reflow capability meets Pb-free requirements f or JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics.

Table 4. Maximum ratings (continued)

5.2 Static electrical characteristics

Table 5. Static electrical characteristics noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• Fully operational
• Extended mode(11) VPWR 6.0 4.0 V Battery clamp voltage(12) VPWR(CLAMP) 41 47 53 V VPWR operating supply current
• Outputs commanded ON, HS[0 : 3] open, IN[0:3] > VIH IPWR(ON) – 6.5 20 mA VPWR supply current
• Outputs commanded OFF, OFF openload detection disabled, HS[0 : 3] shorted to the ground with VDD= 5.5 V WAKE > VIH or RST > VIH and IN[0:3] < VIL IPWR(SBY) – 6.5 8.0 mA Sleep state supply current VPWR = 12 V, RST = WAKE = IN[0:3] < VIL, HS[0 : 3] shorted to the ground
• TA = 25 °C
• TA = 85 °C IPWR(SLEEP) – 1.0 5.0 μA VDD supply voltage VDD(ON) 3.0 – 5.5 V VDD supply current at VDD = 5.5 V
• No SPI communication
• 8.0 MHz SPI communication(13) IDD(ON) – 1.6 5.0 2.2 mA VDD sleep state current at VDD = 5.5 V IDD(SLEEP) – – 5.0 μA Overvoltage shutdown threshold VPWR(OV) 28 32 36 V Overvoltage shutdown hysteresis VPWR(OVHYS) 0.2 0.8 1.5 V Undervoltage shutdown threshold(14) VPWR(UV) 3.3 3.9 4.3 V VPWR and VDD power-on reset threshold VSUPPLY(POR) 0.5 - 0.9 VPWR(UV) Recovery undervoltage threshold Vpwr(UV)_UP 3.4 4.1 4.5 V VDD supply failure threshold (for VPWR > VPWR(UV)) VDD(FAIL) 2.2 2.5 2.8 V Notes 11. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 V to 6.0 V voltage range, the device is only protected with the thermal shutdown detection. 12. Measured with the outputs open. 13. Typical value guaranteed per design. 14. Output will automatically recov er with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the VPWR degradation level did not go below the undervoltage power-on reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification.

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• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V RDS_01(ON) mΩ HS[0,1] output Drain-to-Source ON resistance (IHS = 5.0 A, TA = 150 °C)
• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V RDS_01(ON) mΩ HS[0,1] output Source-to-Drain ON resistance (IHS = -5.0 A, VPWR = 18 V)(15)
• TA = 25 °C
• TA = 150 °C RSD_01(ON) – mΩ HS[2,3] output Drain-to-Source ON resistance (IHS = 5.0 A, TA = 25 °C)
• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V RDS_23(ON) mΩ HS[2,3] output Drain-to-Source ON resistance (IHS = 5.0 A, TA = 150 °C)
• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V RDS_23(ON) mΩ HS[2,3] output Source-to-Drain ON resistance (IHS = -5.0 A, VPWR = -18 V)(15)
• TA = 25 °C
• TA = 150 °C RSD_23(ON) – mΩ Maximum severe short-circuit impedance detection(16) RSHORT 28 64 100 mΩ Notes 15. Source-Drain ON resistance (re verse Drain-to-Source ON resistance) with negative polarity VPWR. 16. Short-circuit impedance calcul ated from HS[0:3] to GND pins. Value guaranteed per design.

Table 5. Static electrical characteristics (continued) noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

28 W bit = 0

28 W bit = 1

• 28 W bit = 0
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
• 28 W bit = 1
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1 CSR0_0 CSR1_0 CSR0_1 CSR1_1 Current sense ratio (CSR0) accuracy (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0
• Output current 12.5 A 5.0 A 3.0 A 1.5 A CSR0_0_ACC -12 -13 -16 -20 Notes 17. Current sense ratio = I CSNS / IHS[0:3]

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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• Output current 3.0 A 1.5 A CSR0_1_ACC -16 -20 CSR0 current recopy accuracy with one calibration point (6.0 V < VHS[0:3] < 20 V)(18)
• Output current 5.0 A CSR0_0_ACC(C AL) -5.0 – 5.0 % CSR0 current recopy temperature drift (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0(19)
• Output current 5.0 A Δ(CSR0_0)/ Δ(T) 0.04 %/°C Current sense ratio (CSR1) accuracy (6.0 V < VHS[0:3] < 20 V) with 28 W bit=0
• Output current 12.5 A 75 A CSR1_0_ACC -17 -12 +17 +12 Current sense clamp voltage
• CSNS Open; IHS[0:3] = 5.0 A with CSR0 ratio VCL(CSNS) VDD+0.25 VDD+1.0 V OFF openload detection source current(20) IOLD(OFF) 30 – 100 μA OFF openload fault detection voltage threshold VOLD(THRES) 2.0 3.0 4.0 V ON openload fault detection current threshold IOLD(ON) 100 300 600 mA ON openload fault detection current threshold with LED VHS[0:3] = VPWR - 0.75 V IOLD(ON_LED) 2.5 5.0 10 mA Output short to VPWR detection voltage threshold Output programmed OFF VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V Output negative clamp voltage
• 0.5 A < IHS[0:3] < 5.0 A, output programmed OFF VCL - 22 – -16 V Output overtemperature shutdown for 4.5 V < VPWR < 28 V TSD 155 175 195 °C Notes 18. Based on statistical analys is. It is not production tested. 19. Based on statistical data: delta(C SR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production tested. 20. Output OFF openload detection current is the current require d to flow through the load for the purpose of detecting the existence of an openload condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES)

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• 10XS3412CHFK
• 10XS3412JHFK VCL(WAKE) 19 V Wake input forward voltage
• ICL(WAKE) = -2.5 mA VF(WAKE) - 2.0 – - 0.3 V SO high state output voltage
• IOH = 1.0 mA VSOH VDD-0.4 – – V SO and FS low state output voltage
• IOL = -1.0 mA VSOL – – 0.4 V SO, CSNS and FS tri-state leakage current
• CS = VIH and 0 V < VSO < VDD, or FS = 5.5 V, or CSNS=0.0 V ISO(LEAK) - 2.0 0 2.0 μA FSI external pull-down resistance(26)
• Watchdog disabled
• Watchdog enabled RFS – Infinite 1.0 kΩ Notes 21. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 22. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 23. The current must be limited by a series resistance when usin g voltages > 7.0 V. 24. Pull-down current is with V SI > 1.0 V and VSCLK > 1.0 V. 25. Pull-up current is with V CS < 2.0 V. CS has an active internal pull-up to VDD. 26. In Fail-safe HS[0:3] depends r espectively on ON[0:3]. FSI has an active internal pull-up to VREG ~ 3.0 V.

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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5.3 Dynamic electrical characteristics

Table 6. Dynamic electrical characteristics noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

• VPWR = 14 V SRR_00 0.15 0.3 0.6 V/μs Output rising slow slew rate (low speed slew rate / SR[1:0]=01)(27)
• VPWR = 14 V SRR_01 0.07 0.15 0.3 V/μs Output falling fast slew rate (high speed slew rate / SR[1:0]=10)(27)
• VPWR = 14 V SRR_10 0.3 0.6 1.2 V/μs Output falling medium slew rate (medium speed slew rate / SR[1:0]=00)(27)
• VPWR = 14 V SRF_00 0.15 0.3 0.6 V/μs Output falling slow slew rate (low speed slew rate / SR[1:0]=01)(27)
• VPWR = 14 V SRF_01 0.07 0.15 0.3 V/μs Output rising fast slew rate (high speed slew rate / SR[1:0]=10)(27)
• VPWR = 14 V SRF_10 0.3 0.6 1.2 V/μs HS[0,1] output turn-on and turn-off delay time(28)
• VPWR = 14 V t DLY_01 45 70 95 μs HS[2,3] output turn-on and turn-off delay time(28)
• VPWR = 14 V t DLY_23 40 65 90 μs Driver output matching slew rate (SRR /SRF) VPWR = 14 V @ 25 °C and for medium speed slew rate (SR[1:0]=00) Δ SR 0.8 1.0 1.2 Driver output matching time (t DLY(ON) - t DLY(OFF)) VPWR = 14 V, f PWM = 240 Hz, PWM duty cycle = 50%, @ 25 °C for medium speed slew rate (SR[1:0]=00) Δ t RF -25 -5.0 15 μs Notes 27. Rise and fall slew rates measured across a 5.0 Ω resistive load at high-side output = 30% to 70% (see Figure 4, page 21). 28. Turn-on delay time measured from rising edge of any signal (IN[0 : 3] and CS) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with RL = 5.0 Ω resistive load. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3] and CS) that would turn the output OFF to VHS[0 : 3] =VPWR / 2 with RL = 5.0 Ω resistive load.

• 10XS3412CHFK
• 10XS3412JHFK tFAULT - 5.0 5.0 μs Output shutdown delay time(30)
• 10XS3412CHFK
• 10XS3412JHFK tDETECT - 7.0 7.0 μs CSNS valid time(31) t CNSVAL – 70 100 μs Watchdog timeout(32) t WDTO 217 310 400 ms ON openload fault cyclic detection period with LED
• Internal clock (PWM_en bit = 1 & CLOCK_Set = 1)
• External clock (PWM_en bit = 1 & CLOCK_Set = 0) TOLLED 6.4 8.3 PWM period ms Notes 29. Time necessary to report the fault to FS pin. 30. Time necessary to switch off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage = 50% of VPWR 31. Time necessary for CSNS to be within ±5% of the targeted val ue (from HS voltage = 50% of VPWR to ±5% of the targeted CSNS value). 32. For FSI open, the Watchdog timeout delay measured from the r ising edge of RST, to HS[0,2] output state depend on the corresponding input command.

Table 6. Dynamic electrical characteristics (continued) noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. Clock fail detector availabl e for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
2. The PWM ratio is measured at V HS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle 100%)

the output with RL = 5.0 Ω resistive load.

1. Typical value guaranteed per design.
2. Value guaranteed per s tatistical analysis.

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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• CL = 80 pF t RSO – – 13 ns SO fall time
• CL = 80 pF t FSO – – 13 ns SI, CS, SCLK, incoming signal rise time(40) t RSI – – 13 ns SI, CS, SCLK, incoming signal fall time(40) t FSI – – 13 ns Time from rising edge of SCLK to SO low-impedance(41) t SO(EN) – – 60 ns Time from rising edge of SCLK to SO high-impedance(42) t SO(DIS) – – 60 ns Notes 37. Parameters guaranteed by design. 38. RST low duration measured with outputs enabled and going to OFF or disabled condition. 39. Maximum setup time required for the 10XS3412 is the minimum guaranteed time needed from the microcontroller. 40. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 41. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS. 42. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.

noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

5.4 Timing diagrams

Figure 4. Output slew rate and time delays Figure 5. Overcurrent shutdown protection

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Figure 6. Bulb cooling management Figure 7. Input timing switching characteristics

0.7 VDD

0.2 VDD

Figure 8. SCLK waveform and valid SO data delay time

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6 Functional description

6.1 Introduction

The 10XS3412 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(on) MOSFETs (dual 10 mΩ, dual 12 mΩ) can control four separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 1 6-bit SPI interface. Its output w ith selectable slew-rate impro ves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XS3412 allows the user to progr am via the SPI the fault current trip levels and duration of ac ceptable lamp inrush. The device has Fail-safe mode to provide functionality of the outputs in case of MCU damage.

6.2 Functional pin description

6.2.1 Output current monitoring (CSNS)

The Current Sense pin provides a current proportional to the designated HS0 : HS3 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resi stor (4.7 kΩ typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI.

6.2.2 Direct inputs (IN0, IN1, IN2, IN3)

Each IN input wakes the device. The IN0 : IN3 high-side input pins are also used to directly control HS0 : HS3 high-side output pins. In case of the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, RDWN.

6.2.3 Fault status ( FS)

This pin is an open drain confi gured output requiring an extern al pull-up resistor to V DD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.

6.2.4 Wake

The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 kΩ typ). This input has a passive internal pull-down, RDWN.

6.2.5 Reset ( RST)

The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low- current Sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN.

6.2.6 Chip select ( CS)

The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 10XS3412 latches in data from the Input Shift regist ers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pull-up from VDD, IUP.

6.2.7 Serial clock (SCLK)

The SCLK pin clocks the internal shift registers of the 10XS3412 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull- down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 10, page 27). SCLK input has an active internal pull-down, IDWN.

6.2.8 Serial input (SI)

This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of se rial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XS3412 are configured and controlled using a 5-bit addressing scheme described in Table 11. Register addressing and configuration are described in Table 12. The SI input has an active internal pull-down, IDWN.

6.2.9 Digital drain voltage (VDD)

This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe mode.

6.2.10 Ground (GND)

These pins are the ground for the device.

6.2.11 Positive power supply (VPWR)

This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package.

6.2.12 Serial output (SO)

The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out o n the falling edge of SCLK. SO reporting descriptions are provi ded in Table 24.

6.2.13 High-side outputs (HS3, HS1, HS0, HS2)

Protected 10 mΩ and 12 mΩ high-side power outputs to the load.

6.2.14 Fail-safe input (FSI)

This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature. When the FSI pin is opened, the watchdog circuit is enabled. After a Watchdog timeout occurs, the output states depends on IN[0:3]. When the FSI pin is connected to GND, the watchdog circuit is d isabled. The output states depends on IN[0:3] in case of V DD Failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).

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6.3 Functional internal block description

Figure 9. Functional block diagram

6.3.1 Power supply

The 10XS3412 is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device. (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep mode. on the SPI or/and on VDD voltage.

6.3.2 High-side switches: HS0 – HS3

maintain the device in its Safe Operating Area.

6.3.3 MCU interface and output control

and configurable overcurrent detection circuitry and wire-harness optimization, the vehicle is lighter. In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.

7 Functional device operation

7.1 SPI protocol description

Output (SO), Serial Clock (SCLK), and Chip Select (CS). significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels. Figure 10. Single 16-bit word SPI communication

7.2 Operational modes

The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input. Figure 11. IN_ON[x] internal signal

• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3],
• f a i l = ( VDD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground),
• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and OV_dis). CSCSB SI SCLK SO D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10 OD12 OD13 OD14 OD15 OD6OD7OD8OD9OD10OD11 OD1 OD2 OD3 OD4OD5 1. RSTB is in a logic H state during the above operation. 2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC NOTES: OD0 CS device. 1. RST is a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of data into the device. 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device. Notes IN_ON[x] IN[x] tIN

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Figure 12. Operating modes

7.2.1 Sleep mode

• V PWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• f a u l t = X . This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST and IN_ON[0:3] are logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0].

Table 7. 10XS3412 operating modes Sleep 0 x x Device is in Sleep mode. All outputs are OFF. Normal 1 0 0 Device is currently in Normal mode. Watchdog is active if enabled. input in case the FSI is open. Fault 1 X 1 Device is currently in Fault mode. The faulted output(s) is (are) OFF. The safe autoretry circuitry is active to turn-on again the output(s).

7.2.2 Normal mode

• V PWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]).

7.2.2.1 Programmable PWM module

The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1]. the CLOCK_fail bit reports [1]. Table 8. Output PWM resolution

0 X OFF

Table 9. Output PWM switching delay

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7.2.2.2 Calibratable internal clock

The internal clock can vary as much as +/-30 percent corresponding to typical fPWM(0) output switching period. to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128. Figure 13. Internal clock calibration diagram internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before. The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1].

7.2.3 Fail-safe mode

• V PWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• f a u l t = 0 .

7.2.3.1 Watchdog

clamp current according to the specification. minimum watchdog timeout period (WDTO), the device will operate normally.

7.2.3.2 Fail-safe conditions

mode transition paragraph) and VDD is within the normal voltage range. (except POR bit) and fault protections are fully operational. Table 10. SPI watchdog activation

The Fail-safe mode can be detected by monitoring the NM bit is set to [0].

7.2.4 Normal and Fail-safe mode transitions

7.2.4.1 Transition Fail-safe to Normal mode

To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to logic [1] ; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included). Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0].

7.2.4.2 Transition Normal to Fail-safe mode

To leave the Normal mode, a Fail-safe condition must occurred ( fail=1). The previous latched faults are reset by the transition into Fail- safe mode (autoretry included).

7.2.5 Fault mode

The 10XS3412 is in Fault mode when:

• V PWR and VDD are within the normal voltage range
• wake-up = 1
• f a i l = X
• f a u l t = 1 This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up:
• Overtemperature fault
• Overcurrent fault
• Severe short-circuit fault
• Output(s) shorted to VPWR fault in OFF state
• Openload fault in OFF state
• Overvoltage fault (e nabled by default)
• Undervoltage fault The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent , severe short-circuit, overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS pin.

7.2.6 Start-up sequence

The 10XS3412 enters in Normal mode after start-up if following sequence is provided:

• VPWR and VDD power supplies must be above their undervoltage thresholds,
• generate wake-up event (wa ke-up=1) from 0 to 1 on RST. The device switches to Normal mode with SPI register content is reset (as defined in Table 12 and Table 24). All features of the 10XS3412 will be available after 50 μs typical and all SPI registers are set to default values (set to logic [0]). The UV fault is reported in the SPI status registers. And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• apply PWM clock on IN0 in put pin after maximum 200 μs (min. 50 μs). If the correct start-up sequence is not provided, the PWM function is not guaranteed.

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7.3 Protection and diagnostic features

7.3.1 Protections

7.3.1.1 Overtemperature fault

The 10XS3412 incorporates overtemperature detection and shutdown circuitry for each output structure.

• If the output command is ON: t he corresponding output is latched OFF. FS will be also latched to logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
• If the output command is OFF: FS will go to logic [0] till the corresponding output temperature will be below TSD. For both cases, the fault register OT[0:3] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after a SPI read command.

7.3.1.2 Overcurrent fault

profiles, selectable separately by Xenon bit and 28 W bits (as illustrated Figure 17, page 39). is programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in case of OCHI bit is set to [1]. Figure 14. Overcurrent detection profile OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits. of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (OC[0:3] bits) is removed after a read operation. illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits.

Figure 15. Bulb cooling principle

7.3.1.3 Severe short-circuit fault

The 10XS3412 provides output shutdown in order to protect each output in case of severe short-circuit during of the output switching. output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (SC[0:3] bits) is removed after a read operation.

7.3.1.4 Overvoltage faul t (enabled by default)

< VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold. still protected with overtemperature protection in case the overvoltage feature is disabled.

7.3.1.5 Undervoltage fault

internal logic states within the device will remain (configuration and reporting). [0], and the fault register UV bit will be set to [1].

• If outputs command are low, FS will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning report).
• If the output c ommand is ON, FS will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new OT fault is detected (VDD failure included) and reported throug h SPI above VPWR(UV). The output state is not changed as long as the VPWR voltage does not drop any lower than 3.5 V typical. All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
• V DD < VDD(FAIL) with VPWR in nominal voltage range,
• V DD and VPWR supplies is below VSUPPLY(POR) voltage value. Over-current thresholds toff depending to toff Cooling PWM hson signalfault_control hson Depending on toff

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Figure 16. Autoretry state machine

7.3.2 Autoretry

conditions to provide a high availability of the load. retry[x] = OC[x] or OT[x] or UV. Retry_dis bit toggling. At each autoretry, the overcurrent detection will be set to default values in order to sustain the inrush current. The Figure 16 describes the autoretry state machine.

7.3.3 Diagnostic

7.3.3.1 Output shorted to VPWR fault

register will be cleared after reading the register. The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:3] bit).

7.3.3.2 Openload faults

The 10XS3412 incorporates three dedicated openload detection circuitries on the output to detect in OFF and in ON state.

7.3.3.3 Openload detection in OFF state

The OFF output openload fault is detected when the output volta ge is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output openload fault is latched into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:3] fault bit is set in the status register. If the open load fault is removed (FS output pin goes to high), the status register will be cleared after reading the register. The OFF output openload protection can be disabled through SPI (OLOFF_DIS[0:3] bit).

7.3.3.4 Openload detection in ON state

The ON output openload current thresholds can be chosen by SPI to detect a standard bulbs or LEDs (OLLED[0:3] bit set to logic [1]). In the cases where load current drops below the defined current threshold, the OLON bit is set to logic [1], and the output stays ON and FS will not be disturbed.

7.3.3.5 Openload detectio n in ON state for LED

Open load for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically each t OLLED (fully-on, D[7:0]=FF). To detect OLLED in the fully-on state, the output must be ON at least t OLLED and PWM module must be enabled (PWM_en = 1 in GCR register). To delatch the diagnosis, the condition should be removed and SPI read operation is needed (OL_ON[0:3] bit). The ON output openload protection can be disabled through SPI (OLON_DIS[0:3] bit).

7.3.4 Analog current recopy and temperature feedback

The CSNS pin is an analog output reporting a current proportion al to the designed output curren t or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum current is 2.0 mA typical. The typical value of external CSNS resistor connected to the ground is 4.7 kΩ. The current recopy is not active in Fail-safe mode.

7.3.4.1 Temperature p rewarning detection

In Normal mode, the 10XS3412 provides a temperature prewarning reported via SPI in case of the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed.

7.3.5 Active clamp on VPWR

The device provides an active ga te clamp circuit in order to li mit the maximum transient VPWR voltage at VPWR (CLAMP). In case of an overload on an output, the corresponding output is turned off, which leads to a high-voltage at VPWR with an inductive VPWR line. When VPWR voltage exceeds VPWR (CLAMP) threshold, the turn-off on the corresponding output is deactiv ated and all HS[0:3] outputs are switched ON automatically to demagnetize the inductive Battery line. For a long battery line between the battery and the device (> 2 0 meters), the smart high-side swit ch output may exceed the energ y capability in case of a short-circuit. It is recommended to implement a voltage transient suppressor to drain the battery line energy.

7.3.6 Reverse battery on VPWR

The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is 2 times higher than typical ohmic value in forward mode. No additional passive components are required except on VDD current path.

7.3.7 Ground disconnect protection

In the event the 10XS3412 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection (maximum VPWR=16 V). A 10 kΩ resistor needs to be added between the MCU and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings.

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7.3.8 Loss of supply lines

7.3.8.1 Loss of VDD

operational with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from VPWR to VDD.

7.3.8.2 Loss of VPWR

provided for RST is set to logic [1] under VDD in nominal conditions. The SPI pull-up and pull-down current s ources are not operational. current is conducted from VDD to VPWR.

7.3.8.3 Loss of VPWR and VDD

contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset.

7.3.9 EMC performances

All following tests are performed on NXP evaluation board in accordance with the typical application schematic. The device is protected in case of positive and negative transients on the VPWR line (per ISO 7637-2).

7.4 Logic commands and registers

7.4.1 Serial input communication

Table 11. SI message bit assignment MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D14 : D13 Register address bits used in some cases for output selection (Table 12). D12 : D10 Register address bits. D9 Not used (set to logic [0]). LSB D8:D0 Used to configure the inputs, outputs, and the device protection features and SO status content.

7.4.2 Device register addressing

The following section describes the possible register addresses (D[14:10]) and their impact on device operation.

7.4.2.1 Address XX000 — Status register (STATR_S)

(see Serial output communication (device status return data).

7.4.2.2 Address A 1A0001— Output PWM control register (PWMR_S)

selected for configuration based on the state of the D14 : D13 bits (Table 13). and cooling responses are dedicated to 28 W lamp. Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down). Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 8. Table 12. Serial input address and configuration bit map

4 D13 D1

0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

s = Output selection with the bits A1A0 as defined in Table 13. Table 13. Output selection

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7.4.2.3 Address A 1A0010— Output configuration register (CONFR0_S)

independently selected for configuration based on the state of the D14 : D13 bits (Table 13). the output from direct control (in this case, the output is only controlled by On bit). value [00] corresponds to the medium speed slew rate (Table 14). shown Table 9, (only available for PWM_en bit is set to logic [1]).

7.4.2.4 Address A 1A0011 — Output configuration register (CONFR1_S)

is independently selected for configuration based on the state of the D14 : D13 bits (Table 13). corresponds to enable autoretry feature without time limitation. [0] corresponds to enable this feature. corresponds to enable this feature (Table 15). corresponds to enable this feature. [0] corresponds to ON output openload detection is set for bulbs (Table 15). Table 14. Slew rate speed selection

7.4.2.5 Address A 1A0100 — Output overcurrent register (OCR)

is independently selected for configuration based on the state of the D14 : D13 bits (Table 13). A logic [1] on bit D8 (Xenon_s) enables the bulb overcurrent profile, as described Figure 17. Figure 17. Overcurrent profile depending on Xenon bit Table 15. ON openload selection

1 X disable

Table 16. Current sense ratio selection

0 CRS0 (default)

1 CRS1

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A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 18. Figure 18. Overcurrent profile with OCHI bit set to ‘1’ The wire harness is protected by one of four possible current levels in steady state, as defined in Table 19. Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 20.

7.4.2.6 Address 00101 — Global configuration register (GCR)

The GCR register allows the MCU to configure the device through the SPI. Table 17. Cooling curve selection Table 18. Inrush curve selection Table 19. Output steady state selection Table 20. Overcurrent mode selection

register (the direct input states are ignored). Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 21. Bits D5:D4 allow the MCU to select one of two analog feedbacks on the CSNS output pin, as shown in Table 22. The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).

7.4.2.7 Address 00111 — Calibration register (CALR)

The CALR register allows the MCU to calibrate internal clock, as explained in Figure 16.

7.4.3 Serial output communicat ion (device status return data)

previously written SPI word. pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification. now able to accept new fault status information. registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers. selected during the most recent STATR write until changed with an updated STATR write.

• The previous SPI communication was determined to be invalid. I n this case, the status will be reported as though the invalid SPI communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU.

Table 21. PWM module selection

0 X PWM module disabled (default)

Table 22. CSNS reporting selection Table 23. Output current recopy selection

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7.4.4 Serial output bit assignment

summarizes SO returned data for bits OD15 : OD0.

• Bit OD15 is the MSB; it reflec ts the state of the Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect th e state of the bits SOA4 : SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 24.

7.4.4.1 Previous address SOA4 : SOA0 = A1A0000 (STATR_S)

SOA4:SOA3 = A1A0 (Table 24).

• OC_s: overcurrent fault detec tion for a selected output,
• SC_s: severe short-circuit faul t detection for a selected output,
• OS_s: output shorted to VPWR faul t detection for a selected output,
• OLOFF_s: openload in OFF state fa ult detection for a selected output,
• OLON_s: openload in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,
• OV: overvoltage fault detection,
• UV: undervoltage fault detection
• POR: power on reset detection. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).

Table 24. Serial output bit map description

10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

7.4.4.2 Previous address SOA4 : SOA0 = A1A0001 (PWMR_S)

The returned data contains the programmed values in the PWMR register for the output selected with A1A0.

7.4.4.3 Previous address SOA4 : SOA0 = A1A0010 (CONFR0_S)

The returned data contains the programmed values in the CONFR0 register for the output selected with A1A0.

7.4.4.4 Previous address SOA4 : SOA0 = A1A0011 (CONFR1_S)

The returned data contains the programmed values in the CONFR1 register for the output selected with A1A0.

7.4.4.5 Previous address SOA4 : SOA0 = A1A0100 (OCR_S)

The returned data contains the programmed values in the OCR register for the output selected with A1A0.

7.4.4.6 Previous address SOA4 : SOA0 = 00101 (GCR)

The returned data contains the programmed values in the GCR register.

7.4.4.7 Previous address SOA4 : SOA0 = 00111 (DIAGR0)

The returned data OD2 reports logic [1] in case of PWM clock on IN0 pin is out of specified frequency range. The returned data OD1 reports logic [1] in case of calibration failure. The returned data OD0 reports logic [1] in case of an overtemperature prewarning (temperature of the GND flag is above TOTWAR).

7.4.4.8 Previous address SOA4 : SOA0 = 01111 (DIAGR1)

The returned data OD4: OD1 report in real time the state of the direct input IN[3:0]. state due to watchdog timeout as explained in the following Table 25.

7.4.4.9 Previous Address SOA4 : SOA0 = 10111 (DIAGR2)

The returned data is the product ID. Bits OD2:OD0 are set to 000 for protected dual 10 mΩ and 12 mΩ high-side switches.

7.4.5 Default device configuration

• HS output is commanded by corre sponding IN input or On bit through SPI. The medium slew rate is used,
• HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage and the overtemperature protection. The autoretry feature is enabled,
• Openload in ON and OFF state a nd HS shorted to VPWR detections are available,
• No current recopy and no analog temperature feedback active,
• Overvoltage protec tion is enabled,
• SO reporting fault status from HS0,
• VDD failure detection is disabled.

Table 25. Watchdog activation report

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8 Typical applications

It is recommended to locate a 22 nF decoupling capacitor to the module connector. Figure 19. Typical application schematic

9 Packaging

9.1 Soldering information

The 10XS3412 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for printed circuit board design and assembly.

9.2 Package mechanical dimensions

Package dimensions are provided in package drawings. To find th e most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package Suffix Package outline drawing number 24-pin PQFN CHFK 98ARL10596D JHFK 98ASA00426D

46 NXP Semiconductors

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52 NXP Semiconductors

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10 Additional documentation

10.1.1 Introduction

packaging information is provided in the data sheet.

10.1.2 Package and thermal considerations

and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. obtained by measurement and simulation according to the standards listed below.

10.1.3 Standards

Table 26. Thermal performance comparison

1. Per JEDEC JESD51-2 at natural convection, still air condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and JESD51 -5.
5. Thermal resistance between the die junction and the exposed p ad, “infinite” heat sink attached to exposed pad.

56 NXP Semiconductors

Figure 22. 2s2p JDEC thermal test board Figure 23. Thermal test board

10.1.4 Device on thermal test board

RθJA is the thermal resistance between die junction and ambient air. Figure 24. Steady state thermal resistance in dependence on heat spreading area; Table 27. Thermal resistance performance

58 NXP Semiconductors

Figure 25. Transient thermal 1W step response; device on Figure 26. Transient thermal 1W step response;

Revision Date Description of changes 7.0 10/2008 • Initial release 8.0 10/2008

• Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5.
• Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics Table on page 8. 9.0 7/2009 • Added MC10XS3412DPNA part number. The “D” version has differen t soldering limits. 10.0 10/2009
• Corrected minor formatting
• Separated definitions for the 10XS3412C and 10XS3412D in the S tatic and Dynamic Tables and created a Device Variation Table on page 2. 11.0 5/2012
• Added MC10XS3412CHFK and removed MC10XS3412CPNA from the order ing information
• Added MC10XS3412DHFK and removed MC10XS3412DPNA from the order ing information
• Updated the pin soldering temperature limit from 10 seconds to 40 seconds (Note (2) and (9)).
• Updated Freescale form and style 12.0 2/2013
• Removed MC10XS3412DPNA from the ordering information
• Added MC10XS3412JHFK
• Added a new Max Solder Reflow temp of the JHFK package.
• Added the package drawing for 98ASA00426D 13.0 8/2018
• Updated as per CIN 201808007I
• Corrected TOLLED values in Table 6, Dynamic electrical characteristics
• Updated Openload detection in ON state for LED (added clarification for the usage of openload LED function and changed D[6:0]=7F to D[7:0]=FF)

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2018. Document Number: MC10XS3412 Rev. 13.0