10941 ETC
Document overview
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Technical content
10941 ¢ 10939 TY 10941 and 10939 Alphanumeric and Bargraph Rockwell Display Controller DESCRIPTION FEATURES The Rockwell 10939 and 10941 Alphanumeric and Bargraph ‘© 20-character display driver cascadable to 80 characters Dispiny Coral’ isamwoche Moss! Logit eonegh ane '* Direct drive capability for vacuum-fiuorescent displays: controller system designed to interface with bargraph ar * 128x418 Pl nt decodk ‘ASCII segmented displays (vacuum-fluorescent or LED). ex fan cape pred and bargreph mites ‘The two-chip set will drive displays with up to 16 segments (plus . Sere! operate! data input for €-bit display and contro! decimal point and comma tail) and up to 20 grids (characters) a plus a cursor. The chips can be cascaded to drive larger displays * Brightness, refresh rate, and display mode controls of 80 characters. Segment decoding for ASCII characters and ‘Separate cursor driver output bargraph patterns is accomplished through an internal PLA. * 1099—40-pin DIP package + 10841—24-pin DIP package
ORDERING INFORMATION
Type Range (°C) 70961P Plastic Oto +70 10961PE Plastic =40 10 +85 10939P Plastic 010 +70 10936PE Plastic -40 10 +85 sat] [emer fomesme ‘wont = as wee Lisa | (reve | Derect| || scuK-ois leo [ax wri] [10 ournoe|—"F Losic Ser SHIFT DATALOAD| REGISTER [4 Block Diagram of 10941 and 10939 Document No. 29000097 Data Sheet Order No. D97 5-31 Rev. 3, June 1987
10941 ¢ 10939 Alphanumeric and Bargraph Display Controller ——a—SE—re OS INTERFACE DESCRIPTION
10941 Pin Functions 10939 Pin Functions
Veg. 2 Power and signal reference Vss 36 ‘Power and signal reference SG01-SG16 | 6-15, 17-22 | Segment driver outputs Voo 37 DC Power ‘SCLK-DIS 23 ‘Serial data shift clock ‘CLOCK 3 ‘Synchronization Clock DATALOAD 24 | Serial data outpuviatch contro! ‘CURSOR 14 | Cursor driver output PNT 4 Decimal Point driver output MASTER 39 Master/Slave Mode control TAIL 5 ‘Comma Tail driver output sip 3 ‘Sync Input Yoo. 1 OC Power SOP 2 ‘Syne Output Veo. 16 Display voltage 0-07 613 Serial or parallel data input o 5 | Input data strobe POR 4 Power-on reset ‘SCLK-DIS 1 ‘Serial data shitt clock DATA-LOAD 40 ‘Serial data output/latch control STROO-STR19 15-34 Grid Driver Outputs: vo da 2b pataLoap Vou 35 _| Display voltage Ves G2 235 SCLK-DIS PAT C3 2D sco Ta 4 216 saoz Nor useD 5 205 saos sais G6 12 saos SCLK-DIS G1 40 DATA-LOAD sats j7 18 B sa0s sop q2 39) MASTER sav qs 175 soos SIP 3 38 clock sors Ge 16 B Vag por d4 37D Voo sa12 10 185 sor uw ds 36 Vee son qi 145 soos po de 35D Veo SG10 12 13/5 scoo pid? 34 sthoo v2 de 33 sTrot os ds 32) STRO2
10941 Pin Configuration ay 3B srnos
‘STRIS C19 22 STRi2 sTRt4 20 zip staia SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS” 10939 Pin Configuration Voltages are referenced to Ves [Parameter Symbot | Vaiue [unit | “NOTE: Stresses above those listed under ABSOLUTE MAXI- Operating Temperature MUM RATINGS may cause permanent damage to the device. Commercial Oto +70 °C ‘This is a stress rating only and functional operation of the device Industrial Te ~40 to +85 °c at these or any other conditions above those indicated in other Storage Temperature Ti -55 to +125 | °C ‘sections of this document is not implied. Exposure to absolute ‘Operating Voltage Voo | -22t0-18 | Vdc maximum rating conditions for extended periods may affect =20 (typical) device reliability. [Operating Display Vowege | Vos | -80 | vee | 5-32
10941 ¢ 10939 Alphanumeric and Bargraph Display Controller i ic ahaa tenses Dhaene DC CHARACTERISTICS All voltages referenced to Vss [Parameter Symbot win tye mee Tt T0941 Output Segments Loge "1" tloag = 2 mA) Vou Vss v Logic "1" (aan = 0 mA) Vou 0.98 Voo v 10989 Input 00-07, LD, SIP Logie 1" Ver -12 v Logie “0” Va Vos v Input POR: Logic "1" Vueo -30 v Logic “0” Vuro Yoo Mi Output SOP Logic “1"" ~12 Ves. v Logic "0" Yoo 42 v Output Digits, Cursor Logie "1" (hag = 10.mA) Ves Logic "0" (Ieag = 0 mA) 0.95 x Vog OPERATING CURRENTS Industrial ‘Commercial TAs ~40°C TA = 0°C TA = 25°C Voo = 22 Vde Voo = ~22 Vde Voo = ~20 Vide Voq = 50 Vee Veo = ~50 Vde Veo = ~50 Vee yo04t too 45 mA leo. 57 mA 10939 (master) too 109 60 ma loa Cr) 05 mA 10939 (slave) bo 73 mA lea 08 ma Notes: 1. Tho 10941 has 18 intoral drivers which are brought out. lag is proportional to the number of drivers on. The values given are for ail 18 drivers on. Divide log shown by 18 to determine lag for one driver 2. The 10939 will never have more than two drivers on at any one time; one grid driver and the cursor. The values shown are for two drivers on with 100% duty cycle. 5-33
10941 ¢ 10939 Alphanumeric and Bargraph Display Controller AC CHARACTERISTICS [Parameter Symbot min typ ax unit GENERAL INTERFACE TIMING ‘Data Load (LD) On Time Ton 10 ‘Off time Tot Commercia! 400 Industrial us Cycle Time Tracye ‘Commerical 60.0 Industrial 66.7 SERIAL INTERFACE TIMING ‘Serial Clock (D1) On Time Troon 1.0 Off Time Teor 10 Cycle Time Troe 20 Serial Data (00) Setup Time Twsip 400 Hold Time Trnotd 400 ‘Serial Clock to LD Time Te 10 LD to Serial Clock Te 10 PARALLEL INTERFACE TIMING ; Parallel Data (D0-D7) | ‘Setup Time Tpeetp | Hola Time Tee | TIMING WAVEFORMS | _ . Ton —> ft Toco | b1 ' (SERIAL CLOCK). bete-o} Las Lo — ST | Fe —] Teno Taal “- Serial Interface Timing Waveforms a no »o — J Li Js” Tonote Parallel intertace Timing Waveforms: 5-34
10941 * 10939 Alphanumeric and Bargraph Display Controller FUNCTIONAL DESCRIPTION Table 1. Control Word Assignments Once the display butfer has been loaded from the host proc- [Wexvawe[Funetion essor, the 10941/10939 system generates all timing signals 00 Not used required to control the display. ot Load 01 into Data Butter 02 | Not used 03 | Not used Input data is loaded into the Display Data Butfer as a series of 04 Not used @-bit words via the Serial or Parallel Data Input channel on the 05 | Set digit time to 16 cycles per grid 10999. Internal timing and contrat logic synchronize the digit out- 06 —_| Set digit time to 32 cycles per grid put signals with the Serial Data and Load signals to the 10941 87 | Sot eat ime to 64 cycles par arid to provide the proper timing for the multiplexing operation. A 08 en omrol ty Mode (M88 In data words 128 x 18 bit PLA is provided for decoding the character set and 09 | Enable Blank Mode (data words with MSB = 1 will bargraph codes. be blanked and cursor will be on) 0A Enable Inverse Mode (data words with MSB = 1 The parallel data input mode is implemented by toggling any on | pile anversed” and cursor wil be on) of data lines D2-D7 after POR has gone low. Once the parallel cc | Notused data load mode has been implemented, a power-on reset pro- 0D Not used cedure must be performed to return to serial data load mode. OE ‘Start Display Refresh Cycle (use only once after Parallel data transfer is accomplished by putting the command reset) or display data on the data lines, then pulsing the LD line. The roar | NOt OSes oad cycle time must be at least 60 xs with the LD line set high Be te . Duty Cycle Register with lower 6 bits (0-63) for at least one xs and held low for at least 40 ys. 80-9F Load Digit Counter (0 = 32, 81=1, 82=2, etc.) A0-BF | Not used ; The serial data input mode is implemented during the power- oor toad Buttor Pointer Register with lower 5 bits on reset procedure. In those systems using serial mode, ports D2-D7 should be tied low to prevent the inadvertent implemen- tation of the parallel load mode. Serial data bytes are shifted into a data buffer MSB first on line DO using line D1 as the serial Table 2. Butter Pointer Control Codes clock. The last eight bits clocked in are latched into the display controlier by a pulse on the LD line, The cycle time for each data bit is 2 us and the load time for each byte is 60 us. co 0 ry cr or 1 Input data may be Control or Display data. The following c2 o2 2 paragraphs describe the format and functions of these contro! 3 be 3 and display data words. cs 05 5 ce 8 6 co o7 7 CONTROL DATA WORDS ca 08 a Control data words are used to select the operating parameters 4 a 0 of the display controller. They must be preceded by a Control cB 8 " Prefix word (0000 0001, hexadecimal 01) to be distinguished ce oc 12 from Display Data words. Table 1 shows the Control Word code cp 00 13 assignments and functions. ce OE 14 oF oF 1 i) 10 16 oF W 7 Butfer Pointer Control be 2 4 The Butfer Pointer Control code sets the Display Data Butter 08 33 1° pointer. The lower 5 bits of the code are loaded into the buffer Note: pointer (see Table 2). DO NOT USE CHARACTER POSITIONS 20-31 (Codes D4-DF). 5-35
Table 3. Digit Counter Control Codes s | 3 | 3 || s | a | %
81 On 1 7 13 3 29 3 58 6
80 00 13 or Normal Display mode. °o 1% FS is enabled on all characters with the MSB equal to one.
a 10941 * 10939 Alphanumeric and Bargraph Display Controller Start Refresh SEGMENT (ANODE) DRIVERS (SG01-SG16, PNT, TAIL) ‘At power on, the 10939 is held in an internal hatt mode. The Eighteen Segment (Anode) Drivers are provided in the 10941. normal display refresh sequence starts upon receipt of a ‘Start ‘The output states for each character pattern and each bargraph Refresh control code. This is particularly useful for synchroniz- pattern are internally decoded from the 8-it characters receiv- ing systems using more than one 10839. Only the Master 10939 ed from the 10939 by means of a 128 x 16-bit PLA. Data codes in a multi-chip system will recognize the Start Retresh code. The and the corresponding segment patterns are shown in Figure 1. Master starts the Siave(s) at the appropriate time, using the SOP Data codes and the corresponding bargraph patterns are shown signal. in Figure 2. ayia cnn ot HAGUE UALUHLE Display data words are loaded as 8-bit codes. The eighth (most 8 significant) bit specifies normal (0) or blank/inverse (1) display iY Zi} mode, depending on the blank/inverse mode selection (see Con- Wt trol data words 09 and 0A in Table 1). This bit also controls the Tv cursor. wlan mm ‘Twenty display data words must be entered to completely load WZ 4 the Display Data Butter. The Butter Pointer automatically incre- Tol ments after each data word is stored in the buffer. To select a ae espe del | "24 character position to be toaded out of sequence, use the Butter san aioe Pointer control code. The Butter Pointer will automaticaly reset ea i Be Ce eee cia 7 to character position 0 when its value is equal to the programmed = ~ On Det com PLEO BOK RPL bi AP Pas Z : POWER-ON RESET Pe PISS picopl ‘The Power-On Reset (POR) initializes the internal circuits of the I TT, n 10839, This is normally accomplished when power (Voo) is P| Le “f= SF applied. The following conditions are established by application ST Th Lr ror SRR LOe Ee kc 1a, The Grid Drivers (STROO-STA19) on the 10939 are in the [-4 lal teli< elle Mel fel | off state. == == == == b. The Segment Drivers (SGO1-SG16) on the 10941 are in the so ox! Noa! ePle| ' lel bl ! off state. I _\\I \\ | UAL c. The Duty Cycle is set to 0. PY EL” KS | d. The Digit Counter is set to 32. A) ye. \\ --| ‘e. The Buffer Pointer is set to 0. {The Digit time is set to 64. g. The Normal display mode is set v h. DATA-LOAD is set to high impedance state. -! H el | - | i. SCLK-DIS is set to Voy to disable the anode drivers in the =] =| =] = RCRA RR FH |. SOP is set to Vo, to disable the sync pulse. oe ee : iAP SYS NPIS” | ZIN” |Z 1ST 1. When the POR signal is removed, SCLK-DIS is set to the high (CHARACTER impedance state. a Cc 2. During the initial rise time of Vpo at power turn-on, the Goa) Gow) magnitude of Veg should not exceed the magnitude of Voo. 6) DIGIT (GRID) DRIVERS (STROO-STR19) PLUS CURSOR ‘The 20 Digit (Grid) Drivers solect each of the display character ( ( eon positions sequentially during a refresh scan. Display segments J TAL are illuminated when both the Digit Drivers and Segment Drivers for a particular character are energized simultaneously. The Cur- sor segment is generated by the 10939, but its timing charac- SEGMENT DRIVER ASSIGNMENTS teristics are identical to the 16 segments generated by the 10941. Figure 1. 16-Segment PLA Character Codes 537
Figure 2. 16-Segment BarGraph Codes
Figure 5. Typical Display System with Parallel Interface to Host and Two 10939 Devices