1014B

MAX11014 MAXIM

Document overview

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Technical content

Features

♦ Dual Drain-Current-Sense Gain Amplifier Preset Gain of 4 ±0.5% Accuracy for Sense Voltages Between 75mV and 625mV (MAX11014) ♦ Common-Mode Sense-Resistor Voltage Range 0.5V to 11V (MAX11014) 5V to 32V (MAX11015) ♦ Low-Noise Output GATE Bias with ±10mA GATE Drive ♦ Fast Clamp and Power-On Reset ♦ 12-Bit DAC Controls MESFET GATE Voltage ♦ Internal Temperature Sensor/Dual Remote Diode Temperature Sensors ♦ Internal 12-Bit ADC Measures Temperature and Voltage ♦ Pin-Selectable Serial Interface 3.4MHz I2C-Compatible Interface 20MHz SPI-/MICROWIRE-Compatible Interface MAX11014/MAX11015 Automatic RF MESFET Amplifier Drain-Current Controllers PART PIN-PACKAGE PKG CODE AMPLIFIER MAX11014BGTM+ 48 Thin QFN-EP** T4877-6 Class A MAX11015BGTM+* 48 Thin QFN-EP** T4877-6 Class AB

Ordering Information

Applications

19-3985; Rev 0; 2/06 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. + Denotes a lead-free package. *Future product—contact factory for availability. **EP = Exposed pad. Note: All devices are specified over the -40°C to +105°C operating temperature range. Pin Configuration and Typical Operating Circuit appear at end of data sheet. Cellular Base-Station RF MESFET Bias Controllers Point-to-Point or Point-to-Multipoint Links Industrial Process Control

Automatic RF MESFET Amplifier Drain-Current Controllers ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VREFDAC = +2.5V, CREFADC = CREFDAC = 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+ = +5V, CFILT1 = CFILT3 = 1nF, CFILT2 = CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0, VACLAMP1 = VACLAMP2 = -5V, TJ = TMIN to TMAX, unless otherwise noted. All typical values are at TJ = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CURRENT-SENSE AMPLIFIER (Note 1) MAX11014 0.5 11.0Common-Mode Input Voltage Range VRCS+ MAX11015 5 32 V 0.5V < VRCS_+ < 11V for the MAX11014 90Common-Mode Rejection Ratio CMRR 5V < VRCS_+ < 32V for the MAX11015 90 dB IRCS+ 200Input-Bias Current IRCS- VSENSE < 100mV over the common-mode range ±2 µA Full-Scale Sense Voltage VSENSE VSENSE = VRCS+ - VRCS- 625 mV To within ±0.5% accuracy 75 625 To within ±2% accuracy 20 625Sense Voltage Range To within ±20% accuracy 2 625 mV Total Current Set Error V SENSE = 75mV ±0.1 ±0.5 % Current-Sense Settling Time t HSCS Settles to within ±0.5% of final value < 25 µs Saturation Recovery Time Settles to within ±0.5% accuracy, from VSENSE = 1.875V < 45 µs CLASS AB INPUT CHANNEL Untrimmed Offset 19 Bits Offset Temperature Coefficient 0 Bits/ o C Gain 4 Gain Error 0.1 % AV RCS1+, RCS1-, RCS2+, RCS2- to GATEVSS RCS1+, RCS1-, RCS2+, RCS2- to AGND GATEV SCLK/SCL, DIN/SDA, CS/A0, N.C./A2, CNVST, OPSAFE1, DOUT/A1, SPI/I2C, ALARM, BUSY Continuous Power Dissipation (T A = +70°C) 48-Pin Thin QFN (derate 27.0mW/°C

Automatic RF MESFET Amplifier Drain-Current Controllers PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLASS AB OUTPUT CHANNEL Untrimmed Offset (Note 1) 50 µV Offset Temperature Coefficient 0 mV/ o C Gain -2 Gain Error 0.1 % GATE-DRIVE AMPLIFIER/INTEGRATOR IGATE = -1mA VGATEVSS + 1 V IGATE = +1mA -0.15 -4 mV IGATE = -10mA VGATEVSS + 1.2 V Output Gate-Drive Voltage Range (Note 2) VGATE IGATE = +10mA -1 -20 mV Gate Voltage Settling Time— MAX11015 tGATE S ettl es to w i thi n ± 0.5% of fi nal val ue, RS = 50Ω , C GAT E = 15µF, see GATE O utp ut Resi stance vs. GATE V ol tag e i n the Typ i cal O p er ati ng C har acter i sti cs 1.1 ms No series resistance, RS = 0Ω 0 0.5Output Capacitive Load (Note 3) CGATE RS = 500Ω 0 15,000 nF Gate Voltage Noise RMS noise, 1kHz to 1MHz 250 nV/√Hz Maximum Power-On Transient C LOAD = 1nF ±100 mV Output Short-Circuit Current Limit ISC Sinking or sourcing ±25 mA Output Safe Switch On- Resistance ROPSW Clamp GATE1 to ACLAMP1, GATE2 to ACLAMP2 (Note 4) 3.6 k Ω ADC DC ACCURACY Resolution 12 Bits Differential Nonlinearity DNLADC No missing codes ±1 LSB Integral Nonlinearity INLADC (Note 5) ±1.25 LSB Offset Error ±2 ±4 LSB Gain Error (Note 6) ±2 ±4 LSB Gain Temperature Coefficient ±0.4 ppm/ o C Offset Temperature Coefficient ±0.4 ppm/ o C Channel-to-Channel Offset Matching ±0.1 LSB Channel-to-Channel Gain Matching ±0.1 LSB ELECTRICAL CHARACTERISTICS (continued) VREFDAC = +2.5V, CREFADC = CREFDAC = 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+ = +5V, CFILT1 = CFILT3 = 1nF, CFILT2 = CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0, VACLAMP1 = VACLAMP2 = -5V, TJ = TMIN to TMAX, unless otherwise noted. All typical values are at TJ = +25°C.)

Automatic RF MESFET Amplifier Drain-Current Controllers PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC DYNAMIC ACCURACY (1kHz sine-wave input, -0.5dB from full scale, 94.4ksps) Signal-to-Noise Plus Distortion SINAD 70 dB Total Harmonic Distortion THD Up to the 5th harmonic -84 dB Spurious-Free Dynamic Range SFDR 86 dB Intermodulation Distortion IMD f IN1 = 9.9kHz, fIN2 = 10.2kHz 76 dB Full-Power Bandwidth -3dB point 1 MHz Full-Linear Bandwidth S / (N + D) > 68dB 100 kHz ADC CONVERSION RATE External reference 0.8Power-Up Time t PU Internal reference 50 µs GATE_ and sense voltage measurements 40Acquisition Time (Note 3) t ACQ All other measurements 1.5 µs Conversion Time t CONV Internally clocked 6.5 µs Aperture Delay 30 ns ADCIN1, ADCIN2 INPUTS Input Range VADCIN_ Relative to AGND (Note 7) 0 VREFADC V Input Leakage Current V ADCIN_ = 0V or VAVDD ±0.01 ±1 µA Input Capacitance CADCIN_ 34 pF TEMPERATURE MEASUREMENTS TJ = +25°C ±0.25 TJ = -40°C to +85°C (Note 3) ±1.0 ±2.5Internal Sensor Measurement Error TJ = -40°C to +105°C (Note 3) ±1.0 ±3.5 TJ = +25°C ±1.0External Sensor Measurement Error (Note 8) TJ = -40°C to +105°C ±3 °C Temperature Resolution 0.125 °C/LSB External Diode Drive 3.26 75.00 µA External Temperature Sensor Drive Current Ratio 16.6 INTERNAL REFERENCE Reference Output Voltage V REFADC = VREFDAC +2.490 +2.500 +2.510 V Reference Output Temperature Coefficient ±15 ppm/ o C Reference Output Impedance 6.5 k Ω Power-Supply Rejection Ratio PSRR V AVDD = +5V ±5% -83 dB ELECTRICAL CHARACTERISTICS (continued) VREFDAC = +2.5V, CREFADC = CREFDAC = 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+ = +5V, CFILT1 = CFILT3 = 1nF, CFILT2 = CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0, VACLAMP1 = VACLAMP2 = -5V, TJ = TMIN to TMAX, unless otherwise noted. All typical values are at TJ = +25°C.)

Automatic RF MESFET Amplifier Drain-Current Controllers PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCES REFADC Input Voltage Range VREFADC +1.0 V AVDD V VREFADC = +2.5V, fSAMPLE = 178ksps 60REFADC Input Current IREFADC Acquisition/between conversions ±0.01 µA REFDAC Input Voltage Range VREFDAC +0.50 +2.52 V REFDAC Input Current 26 µA DAC DC ACCURACY Resolution 12 Bits Integral Nonlinearity INLDAC Measured at FILT_ ±1 LSB Differential Nonlinearity DNLDAC Measured at FILT_, guaranteed monotonic ±0.4 ±1 LSB POWER SUPPLIES Analog Supply Voltage V AVDD +4.75 +5.25 V Digital Supply Voltage V DVDD +2.7 AV DD V Negative Supply Voltage VGATEVSS, VAVSS VGATEVSS = VAVSS -5.50 -4.75 V Analog Supply Current I AVDD VAVDD = +5.25V 2.8 5 mA Digital Supply Current I DVDD VDVDD = +5.25V 1.5 5 mA Negative Supply Current IGATEVSS + IAVSS VGATEVSS = VAVSS = -5.5V 1.1 1.7 mA Analog Shutdown Current V AVDD = +5.25V 0.8 µA Digital Shutdown Current V DVDD = +5.25V 0.2 µA Negative Shutdown Current V GATEVSS = VAVSS = -5.5V 0.6 µA SERIAL-INTERFACE SUPPLIES VIL 0.3 x DVDD Input Voltage VIH 0.7 x DVDD V Input Hysteresis V HYS 0.05 x DVDD V Output Low Voltage V OL BUSY: ISINK = 0.5mA; DOUT, ALARM: ISINK = 3mA 0.4 V Output High Voltage V OH SPI/ I2C = DVDD; BUSY: ISOURCE = 0.5mA; DOUT, ALARM: ISOURCE = 2mA DVDD - 0.5V V Input Current I IN ±0.01 ±10 µA Input Capacitance C IN 5p F ELECTRICAL CHARACTERISTICS (continued) VREFDAC = +2.5V, CREFADC = CREFDAC = 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+ = +5V, CFILT1 = CFILT3 = 1nF, CFILT2 = CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0, VACLAMP1 = VACLAMP2 = -5V, TJ = TMIN to TMAX, unless otherwise noted. All typical values are at TJ = +25°C.)

Automatic RF MESFET Amplifier Drain-Current Controllers SPI-INTERFACE TIMING CHARACTERISTICS (Note 9) (See Figure 1.) I2C-INTERFACE SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 9) (See Figure 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period t CP 40 ns SCLK High Time t CH 16 ns SCLK Low Time t CL 16 ns DIN to SCLK Rise Setup Time tDS 10 ns DIN to SCLK Rise Hold Time t DH 0n s SCLK Fall to DOUT Transition tDO CL = 30pF 20 ns CS Fall to DOUT Enable t DV CL = 30pF (Note 3) 40 ns CS Rise to DOUT Disable t TR CL = 30pF (Note 10) 40 ns CS Rise or Fall to SCLK Rise t CSS 10 ns CS Pulse-Width High t CSW (Note 3) 40 ns Last SCLK Rise to CS Rise t CSH (Note 3) 0 ns PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL 0 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Hold Time (Repeated) for START Condition tHD;STA After this period, the first clock pulse is generated 0.6 µs Setup Time for a Repeated START Condition tSU;STA 0.6 µs SCL Pulse-Width Low t LOW 1.3 µs SCL Pulse-Width High t HIGH 0.6 µs Data Setup Time t SU;DAT 100 ns Data Hold Time t HD;DAT (Note 11) 0 0.9 µs SDA, SCL Rise Time, Receiving t R (Notes 3, 12) 0 300 ns SDA, SCL Fall Time, Receiving t F (Notes 3, 12) 0 300 ns SDA Fall Time, Transmitting t F (Notes 3, 12, 13) 20 + 0.1 x C B 250 ns Setup Time for STOP Condition t SU;STO 0.6 µs Capacitive Load for Each Bus Line C B (Notes 3, 14) 400 pF Pulse Width of Spikes Suppressed By the Input Filter tSP (Note 15) 50 ns

Automatic RF MESFET Amplifier Drain-Current Controllers I2C-WIRE-INTERFACE HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 9) (See Figure 3.) CB = 100pF max C B = 400pFPARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS Serial Clock Frequency f SCL 0 3.4 0 1.7 MHz Setup Time (Repeated) START Condition tSU;STA 160 160 ns Hold Time (Repeated) START Condition tHD;STA 160 160 ns SCL Pulse-Width Low t LOW 160 320 ns SCL Pulse-Width High t HIGH 60 120 ns Data Setup Time tSU;DAT 10 10 ns Data Hold Time tHD;DAT (Note 11) 0 70 0 150 ns SCL Rise Time t RCL (Note 3) 10 40 20 80 ns SCL Rise Time, After a Repeated START Condition and After an Acknowledge Bit tRCL1 (Note 3) 10 80 20 160 ns SCL Fall Time t FCL (Note 3) 10 40 20 80 ns SDA Rise Time t RDA (Note 3) 10 80 20 160 ns SDA Fall Time t FDA (Note 3) 10 80 20 160 ns Setup Time for STOP Condition tSU;STO 160 160 ns Capacitive Load for Each Bus Line CB (Note 14) 100 400 pF Pulse Width of Spikes Suppressed By the Input Filter tSP (Note 15) 0 10 0 10 ns

Automatic RF MESFET Amplifier Drain-Current Controllers MISCELLANEOUS TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Minimum Time to Wait After a Write Command Before Reading Back Data from the Same Location tRDBK (Note 16) 1 µs CNVST Active-Low Pulse Width in ADC Clock Mode 01 tCNV01 (Note 3) 20 ns CNVST Active-Low Pulse Width in ADC Clock Mode 11 to Initiate a Temperature Conversion tCNV11 (Note 3) 20 ns CNVST Active-Low Pulse Width in ADC Clock Mode 11 for ADCIN1/2 Acquisition tACQ11A (Note 3) 1.5 µs ADC Power-Up Time (External Reference) tAPUEXT 0.8 µs ADC Power-Up Time (Internal Reference) tAPUINT 50 µs DAC Power-Up Time (External Reference) tDPUEXT 2µ s DAC Power-Up Time (Internal Reference) tDPUINT 50 µs Acquisition Time (Internally Timed in ADC Clock Modes 00 or 01) tACQ 0.6 µs Conversion Time (Internally Clocked) tCONV 6.5 µs Delay to Start of Conversion Time tCONVW (Note 17) 1 µs Temperature Conversion Time (Internally Clocked) tCONVT 30 µs

Automatic RF MESFET Amplifier Drain-Current Controllers Note 1: All current-sense amplifier specifications are tested after a current-sense calibration (valid when drain current = 0mA). See RCS Error vs. GATE Current in the Typical Operating Characteristics. The calibration is valid only at one temperature and supply voltage and must be repeated if either the temperature or supply voltage changes. Note 2: The hardware configuration register’s CH_OCM1 and CH_OCM0 bits are set to 0. See Table 10a. The max specification is limited by tester limitations. Note 3: Guaranteed by design. Not production tested. Note 4: At power-on reset, the output safe switch is closed. See the ALMHCFG (Read/Write) section. Note 5: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors have been calibrated out. Note 6: Offset nulled. Note 7: Absolute range for analog inputs is from 0 to VAVDD. Note 8: Device and sensor at the same temperature. Verified by the current ratio (see the Temperature Measurements section). Note 9: All timing specifications referred to VIH or VIL levels. Note 10: DOUT goes into tri-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled before it goes to tri-state. Note 11: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 12: tR and tF measured between 0.3 x DVDD and 0.7 x DVDD. Note 13: CB = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be linearly interpolated. Note 14: An appropriate bus pullup resistance must be selected depending on board capacitance. For more information, refer to the I2C documentation on the Philips website. Note 15: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 16: When a command is written to the serial interface, it is passed to the internal oscillator clock to be executed. There is a small synchronization delay before the new value is written to the appropriate register. If the user attempts to read the new value back before tRDBK, no harm will be caused to the data, but the read command may not yet show the new value. Note 17: This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of the wrong ADC channel). MISCELLANEOUS TIMING CHARACTERISTICS (continued)

Automatic RF MESFET Amplifier Drain-Current Controllers DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX11014 toc01 DVDD SUPPLY VOLTAGE (V) DVDD SUPPLY CURRENT (mA) AVDD = 5.25V 2.40 2.41 2.43 2.42 2.44 2.45 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX11014 toc02 AVDD SUPPLY VOLTAGE (V) AVDD SUPPLY CURRENT (mA) -0.4 -0.2 0.2 0.4 RCS ERROR vs. TEMPERATURE MAX11014 toc03 TEMPERATURE (°C) RCS ERROR (mV) -50 25 50-25 0 75 100 125 AFTER CALIBRATION BEFORE CALIBRATION 40μs/div -5V MAX11014 toc04 VGATE 1V/div GATE VOLTAGE POWER-UP 200 100 400 300 500 600 05 0 0 FILT1/FILT3 SETTLING TIME vs. FILT1/FILT3 CAPACITIVE LOAD MAX11014 toc05 CAPACITIVE LOAD (pF) SETTLING TIME (μs) 200100 300 400 10% TO 90% tRISE tFALL 0.50 0.25 -0.25 -0.50 -10 0 -5 5 10 RCS ERROR vs. GATE CURRENT MAX11014 toc06 GATE CURRENT (mA) RCS ERROR (mV) SOURCING SINKING -5 -3 -4 -2 -1 0 MAX11014 toc07 VGATE (V) GATE OUTPUT RESISTANCE (Ω) GATEVSS = AVSS = -5V GATE OUTPUT RESISTANCE vs. GATE VOLTAGE 1μs/div FILT1 1mV/div AC-COUPLED MAX11014 toc08 GLITCH IMPULSE -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 DAC INTEGRAL NONLINEARITY vs. OUPUT CODE MAX11014 toc09 OUTPUT CODE DAC INL (LSB) Typical Operating Characteristics (VGATEVSS = -5.5V; VAVDD = VDVDD = +5V, GATEVSS = AVSS = -5V, external VREFADC = +2.5V; external VREFDAC = +2.5V; CREF = 0.1µF; TA = TMIN to TMAX, unless otherwise noted.)

Automatic RF MESFET Amplifier Drain-Current Controllers Typical Operating Characteristics (continued) (VGATEVSS = -5.5V; VAVDD = VDVDD = +5V, GATEVSS = AVSS = -5V, external VREFADC = +2.5V; external VREFDAC = +2.5V; CREF = 0.1µF; TA = TMIN to TMAX, unless otherwise noted.) -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 DAC DIFFERTIAL NONLINEARITY vs. OUTPUT CODE MAX11014 toc10 OUTPUT CODE DAC DNL (LSB) -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX11014 toc11 OUTPUT CODE ADC INL (LSB) -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX11014 toc12 OUTPUT CODE ADC DNL (LSB) 0.1 10 1 100 1000 ADC SINAD vs. FREQUENCY MAX11014 toc13 FREQUENCY (kHz) SINAD (dB) 100 0.1 10 1 100 1000 ADC SFDR vs. FREQUENCY MAX11014 toc14 FREQUENCY (kHz) SFDR (dB) 0.001 0.01 0.1 0.1 10 1 100 1000 ADC TOTAL HARMONIC DISTORTION vs. FREQUENCY MAX11014 toc15 FREQUENCY (kHz) THD (%) -120 -80 -100 -40 -60 -20 05 0 ADC FFT PLOT MAX11014 toc16 ANALOG INPUT FREQUENCY (kHz) AMPLITUDE (dB) 2010 30 40 fANALOG_IN = 9.982kHz fCLK = 3.052MHz SINAD = 71.28dBc SNR = 71.51dBc THD = -84.18dBc SFDR = -86.94dBc 0.1 10 1 100 1000 DIGITAL SUPPLY CURRENT vs. SAMPLING RATE MAX11014 toc17 SAMPLING RATE (ksps) DVDD SUPPLY CURRENT (mA) AVDD = DVDD = 5V 2.5026 2.5024 2.5022 2.5020 2.5018 ADC INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX11014 toc18 SUPPLY VOLTAGE (V) ADC REFERENCE VOLTAGE (V) AVDD = DVDD

Automatic RF MESFET Amplifier Drain-Current Controllers 2.5018 2.5016 2.5014 2.5012 2.5010 DAC INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX11014 toc19 SUPPLY VOLTAGE (V) DAC REFERENCE VOLTAGE (V) AVDD = DVDD 2.48 2.49 2.50 2.51 2.52 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX11014 toc20 TEMPERATURE (°C) REFERENCE VOLTAGE (V) -50 25 50-25 0 75 100 125 VREFDAC VREFADC 2.0 1.5 1.0 0.5 ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE MAX11014 toc21 AVDD (V) ADC OFFSET ERROR (LSB) ADC OFFSET ERROR vs. TEMPERATURE MAX11014 toc22 TEMPERATURE (°C) ADC OFFSET ERROR (LSB) -50 25 50-25 0 75 100 125 1.0 0.5 2.0 1.5 2.5 3.0 ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX11014 toc23 AVDD (V) ADC GAIN ERROR (LSB) -50 0 25-25 50 75 100 125 ADC GAIN EROR vs. TEMPERATURE MAX11014 toc24 TEMPERATURE (°C) ADC GAIN ERROR (LSB) INTERNAL TEMPERATURE SENSOR ERROR vs. TEMPERATURE MAX11014 toc25 -1.00 -0.75 -0.25 -0.50 0.50 0.75 0.25 1.00INTERNAL TEMPERATURE SENSOR ERROR (°C) -50 0 25-25 50 75 100 125 TEMPERATURE (°C) GND VRCS1- 100mV/div VPGAOUT1 200mV/div VFILT1 200mV/div

0 TO 100mV VSENSE

0 TO 250mV VSENSE

Typical Operating Characteristics (continued) (VGATEVSS = -5.5V; VAVDD = VDVDD = +5V, GATEVSS = AVSS = -5V, external VREFADC = +2.5V; external VREFDAC = +2.5V; CREF = 0.1µF; TA = TMIN to TMAX, unless otherwise noted.)

Automatic RF MESFET Amplifier Drain-Current Controllers Pin Description PIN NAME FUNCTION 1 DIN/SDA Serial Data Input. Data is latched into the serial interface on the rising edge of SCLK in SPI mode. Connect a pullup resistor to SDA in I2C mode.

2 DOUT/A1

Serial Data Output in SPI Mode/Address Select 1 in I2C Mode. Data transitions on the falling edge of SCLK. DOUT is high impedance when CS is high. Connect A1 to DVDD or DGND to set the device address to I2C mode.

3 ADCIN1 Analog Input 1

4 ADCIN2 Analog Input 2

5 DXN1 Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to DXN1. 6 DXP1 Remote-Diode Current Source. Connect DXP1 to the base/collector of a remote temperature-sensing npn transistor. Do not leave DXP1 open; connect to DXN1 if no remote diode is used. 7 DXN2 Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to DXN2. 8 DXP2 Remote-Diode Current Source. Connect DXP2 to the base/collector of a remote temperature-sensing npn transistor. Do not leave DXP2 open; connect to DXN2 if no remote diode is used. 9 REFDAC DAC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See the HCFG (Read/Write) section. 10 REFADC ADC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See the HCFG (Read/Write) section. 11, 27 AV DD Positive Analog Supply Voltage. Set AVDD between +4.75V and +5.25V. Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND. 12, 26 AGND Analog Ground

13 ACLAMP2 MESFET2 External Clamping Voltage Input

14 GATE2 MESFET2 Gate Connection. See the Gate-Drive Amplifiers section.

15 GATEVSS

Gate-Drive Amplifier Negative Power-Supply Input. Set GATEVSS between -4.75V and -5.5V. Connect externally to AVSS. Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND. 16, 28, 29, 34–37 N.C. No Connection. Not internally connected.

17 ACLAMP1 MESFET1 External Clamping Voltage Input

18 GATE1 MESFET1 Gate Connection. See the Gate-Drive Amplifiers section. 19 FILT1 Channel 1 Filter 1 Input. See Figures 5 and 6. 20 FILT2 Channel 1 Filter 2 Input. See Figures 5 and 6. 21 FILT3 Channel 2 Filter 3 Input. See Figures 5 and 6. 22 FILT4 Channel 2 Filter 4 Input. See Figures 5 and 6. 23 PGAOUT1 Channel 1 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6. 24 PGAOUT2 Channel 2 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6.

25 AV SS

Negative Analog Supply Voltage. Set AVSS between -4.75V and -5.5V. Connect externally to GATEVSS. Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND.

Automatic RF MESFET Amplifier Drain-Current Controllers Pin Description (continued) PIN NAME FUNCTION

30 RCS2+

Channel 2 Current-Sense-Resistor Connection. Connect to the external supply powering channel 2’s MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS1+. 31 RCS2- Channel 2 Current-Sense-Resistor Connection. Connect to the channel 2 MESFET drain. Decouple as required by the application. If unused, connect to RCS2+. 32 RCS1- Channel 1 Current-Sense-Resistor Connection. Connect to the channel 1 MESFET drain. Decouple as required by the application. If unused, connect to RCS1+.

33 RCS1+

Channel 1 Current-Sense-Resistor Connection. Connect to the external supply powering channel 1’s MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS2+. 38 OPSAFE1 Operating Safe Channel 1 Input. Set OPSAFE1 high to clamp GATE1 to ACLAMP1 for fast protection of enhancement FET power transistors. 39 OPSAFE2 Operating Safe Channel 2 Input. Set OPSAFE2 high to clamp GATE2 to ACLAMP2 for fast protection of enhancement FET power transistors. 40 BUSY BUSY Output. BUSY asserts high under certain conditions when the device is busy. See the BUSY Output section.

41 DV DD

Digital Supply Voltage. Set DVDD between +2.7V and AVDD. Bypass with a 1µF and a 0.1µF capacitor in parallel to DGND.

42 DGND Digital Ground

43 CNVST Active-Low Conversion Start Input. Set CNVST low to begin a conversion in clock modes 01 and 11. Connect CNVST to DVDD when issuing conversion commands through the serial interface. 44 ALARM Alarm Output. ALARM asserts when the temperature or voltage measurements exceed their preset high or low thresholds.

45 CS/A0

Chip-Select Input in SPI Mode/Address Select 0 in I2C Mode. CS is an active-low input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. Connect A0 to DVDD or DGND to set the device address in I2C mode. 46 SPI/ I2C SPI-/I2C-Interface Select Input. Connect SPI/I2C to DVDD to select SPI mode. Connect SPI/I2C to DGND to select I2C mode. 47 N.C./A2 No Connection in SPI Mode/Address Select 2 in I2C Mode. Connect A2 to DVDD or DGND to set the device address in I2C mode.

48 SCLK/SCL

Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) Connect a pullup resistor to SCL in I2C mode. See Table 10 for details on programming the clock mode. —E P Exposed Pad. Connect to AGND and a large copper plane to meet power dissipation specifications. Do not use as a ground connection.

Automatic RF MESFET Amplifier Drain-Current Controllers Detailed Description The MAX11014/MAX11015 set and monitor the bias con- ditions for dual MESFET power devices found in cellular base stations and point-to-point microwave links. The internal DAC sets the voltage across the current-sense resistor by controlling the GATE voltage. These devices integrate a 12-bit ADC to measure voltage, internal and external temperature, and communicate through a 4-wire 20MHz SPI-/MICROWIRE-compatible serial interface or 2-wire 3.4MHz I 2C-compatible serial interface (pin-selectable). The MAX11014/MAX11015 operate from an internal +2.5V reference or individual ADC and DAC external references. The external current-sense resistors moni- tor voltages over the 0 to (V DACREF / 4) range. Two cur- rent-sense amplifiers with a preset gain of four monitor the voltage across the sense resistors. The MAX11014/MAX11015 accurately measure their inter- nal die temperature and two external remote diode tem- perature sensors. The remote pn junctions are typically the base-emitter junction of an npn transistor, either discrete or integrated on a CPU, FPGA, or ASIC. The MAX11014/MAX11015 also feature an alarm output that can be triggered during an internal or external overtemperature condition, an excessive current-sense voltage, or an excessive GATE voltage. Figure 4 shows the MAX11014’s functional diagram. The MAX11014 integrates complete dual analog closed-loop drain-current controllers for Class A MESFET amplifier operation. See the MAX11014 Class A Control Loop section. The analog control loop sets the drain current through the current-sense resistors. The MESFET gate-drive amplifier can vary the DAC code accordingly if the temperature or other system variables change. Implement Class A amplifier operation with the follow- ing three steps: 1) Characterization Characterize the MESFET over temperature to deter- mine the amplifier’s set of drain-current values, assuming the part-to-part calibration curve is consis- tent. There may be an offset shift, but no important change in the shape of the function. Load these val- ues into the MAX11014 LUTs at power-up. In opera- tion, there is a linear interpolation between the values stored in the LUTs. Adjust the drain current for other variables such as output power or drain voltage by loading values into the numerical K LUTs. 2) Calibration In production of the power amplifier, measure the quiescent drain current at a fixed calibration temper- ature (probably room) and adjust the V SET(CODE) value until the drain current is within the specified limits for that temperature. The V SET(CODE) value is stored for loading after power-up. Prior to operation, command a PGA calibration after powering up by writing to the PGA calibration control register, setting the TRACK bit to 0 and the DOCAL bit to 1 (see Table 18). 3) Operation Upon request, the MAX11014 measures the temper- ature of the MESFET and compares it with the previ- ous reading. If the temperature reading has changed, the MAX11014 reads the LUTs with the characterization data and updates the DAC to cor- rect the drain current. Setting the TRACK, DOCAL, and SELFTIME bits to 1 in the PGA calibration con- trol register starts automatic monitoring and adjust- ment of drain current for variations in temperature. Also, if the K LUTs are used, their values are monitored for changes. A DAC correction is then made if necessary. For Class AB operation with the MAX11015, measure the MESFET temperature and set the GATE_ voltage through the LUTs and DAC to control the drain current. See the MAX11015 Class AB Control section. Implement Class AB amplifier operation with the same three steps as Class A operation, with the exception that the LUTs set the GATE_ voltage for constant drain current with varying temperature. Power-On Reset On power-up, the MAX11014/MAX11015 are in full power-down mode (see the SHUT (Write) section). To change to normal power mode, write two commands to the shutdown register. Set the FULLPD bit to 0 (other bits in the shutdown register are ignored) on the first command. A second command to this register then activates the internal blocks. MAX11014 Class A Control Loop The MAX11014 is designed to set and continuously control the drain current for MESFET power amplifiers configured to operate in Class A. Set the DAC code to control the voltage across the RCS_+ and RCS_- cur- rent-sense resistor connections. The MAX11014 inter- nal control loop automatically keeps the voltage across the current-sense resistor to the value set by the DAC. See the 12-Bit DAC section.

1 DAC

2 DAC

Figure 4. Functional Diagram

Automatic RF MESFET Amplifier Drain-Current Controllers Once the control loop has been set, the MAX11014 automatically maintains the drain-current value. Figure 5 details the amplifiers that bias the channel 1 and channel 2 control loops. The dual current-sense amplifiers amplify the voltage between RCS_+ and RCS_- by four and add an offset voltage (+12mV nominally). These current-sense ampli- fiers amplify sense voltages between 0 and 625mV when V REFDAC = +2.5V. See the Current-Sense Amplifiers section. The current-sense amplifier output injects a scaled-down replica of the MESFET drain current at the summing node to complete the internal analog feedback loop. The summing node drives the gate-drive amplifier through a 100kΩ series resistor. The gate-drive amplifier is config- ured as an integrator by the external capacitor connect- ed between GATE1/GATE2 and FILT2/FILT4. The gate-drive amplifier includes automatic offset cancella- tion between 0 and 24mV to null the 12mV offset from the current-sense amplifier. See the Register Descriptions and PGACAL (Write)sections. The MAX11014’s analog control loop setpoint is described by the following equation: where: V FILT(CODE = 000h) = V FILT1 (channel 1) and V FILT3 (channel 2) when the THRUDAC1/THRUDAC2 register code is set to 000h. VFILT = VFILT1 (channel 1) and VFILT3 (channel 2). VRCS+ - VRCS- = the voltage drop across the current- sense resistor. Connect a capacitor from FILT2 to GATE1 to form an integrator (setting the control-loop dominant pole) with the channel 1 internal 100k Ω resistor. Connect a capacitor from FILT4 to GATE2 to form an integrator (setting the control-loop dominant pole) with the chan- nel 2 internal 100k Ω resistor. The gate-drive amplifier’s output drives the MESFET gates. See the Gate-Drive Amplifiers section. The channel 1 DAC voltage is output to FILT1 through a series 580k Ω resistor. The channel 2 DAC voltage is output to FILT3 through a series 580k Ω resistor. Connect a capacitor from FILT1 to AGND and FILT3 to AGND to set the filter’s time constant for the respective channel. MAX11015 Class AB Control The MAX11015 is designed to be used with a Class AB amplifier configuration to independently measure the drain current and set the GATE_ output voltages through the serial interface. After sensing the drain current with no RF signal applied, set the DAC code to obtain the desired GATE_ voltage. Figure 6 details the amplifiers that bias the channel 1 and channel 2 control. The MAX11015 internal 12-bit DAC voltage is applied to the gate-drive amplifier, which has a preset gain of -2. See the Gate-Drive Amplifiers section. Setting the DAC code between FFFh and 000h typically produces a GATE_ voltage between 0 and (-2 x V REFDAC). See the HCFG (Read/Write) section for details on adjusting the GATE_ maximum voltage. The channel 1 DAC voltage is output to FILT1 through a series 580k Ω resistor. The channel 2 DAC voltage is output to FILT3 through a series 580k Ω resistor. Connect a capacitor from FILT1 to AGND and FILT3 to AGND to set the filter’s time constant for the respective channel. Connect FILT2 and FILT4 to AGND (MAX11015 only). The dual current-sense amplifiers amplify the voltage between RCS_+ and RCS_- by four and add an offset voltage (+12mV nominally). The current-sense ampli- fiers amplify sense voltages between 0 and 625mV when V REFDAC = +2.5V. See the Current-Sense Amplifiers section. Current-Sense Amplifiers The dual current-sense amplifiers amplify the voltage between RCS_+ and RCS_- and add an offset voltage. Connect a resistor between RCS_+ and RCS_- to sense the MESFET drain current. The current-sense amplifiers scale the sense voltage by four. These amplifiers also reject the drain supply voltage that appears as a DC common-mode level on the current signal. The gate-drive amplifier includes automatic offset can- cellation between 0 and 24mV to null the 12mV offset from the current-sense amplifier. See the PGACAL (Write) section. Gate-Drive Amplifiers The gate-drive amplifiers control the MESFET gate bias settings. The MAX11014’s channel 1 and channel 2 DAC voltages are routed through a summing node and into the gate-drive amplifiers. The MAX11015’s channel 1 and channel 2 DAC voltages are routed directly to the gate-drive amplifiers, which have a preset gain of -2. See the 12-Bit DAC section for details on setting the DAC codes. VV V CODE h V RCS RCS FILT FILT+−−= =−() 000

Figure 5. MAX11014 Class A Analog Control Loop

Figure 6. MAX11015 Class AB Analog Control

REFDAC to turn the MESFET fully off. ALMHCFG (Read/Write) sections. Function section for more details. ings, current-sense voltages, and ADCIN_ voltages. back data words either one at a time or continuously. placing a 1µF capacitor between ADCIN_ and AGND. filter that limits the analog-input bandwidth. Figure 7. DAC Code Range

(AGND - 0.3V) to (AV DD + 0.3V) without damage. exceeds the supplies, limit the input current to 2mA. ture measurements with a diode-connected transistor. calibration of 1 LSB corresponding to +0.125°C. registers. See Tables 3, 4, and 5. temperature measurement in an ADC conversion scan. Figure 8. ADC Equivalent Input Circuit

Automatic RF MESFET Amplifier Drain-Current Controllers the ADC conversion register’s continuous convert bit (CONCONV) is set to 1 and the current ADC conver- sion includes a temperature channel. The temperature- sensor circuits remain powered up until the CONCONV bit is set low. The external temperature sensor drive current ratio has been optimized for a 2N3904 npn transistor with an ide- ality factor of 1.0065. The nonideality offset is removed internally by a preset digital coefficient. Using a transis- tor with a different ideality factor produces a proportion- ate difference in the absolute measured temperature. For more details on this topic and others related to using an external temperature sensor, see Application Note 1057 “ Compensating for Ideality Factor and Series Resistance Differences between Thermal-Sense Diodes ” and Application Note 1944 “ Temperature Monitoring Using the MAX1253/54 and MAX1153/54 ” on Maxim’s website: www.maxim-ic.com. 12-Bit DAC The MAX11014/MAX11015 include two voltage-output, 12-bit monotonic DACs with ±1 LSB integral nonlineari- ty error and ±0.4 LSB differential nonlinearity error. The DAC operates from the internal +2.5V reference or an external reference voltage supplied at REFDAC. When using an external voltage reference, bypass REFDAC with a 0.1µF capacitor to AGND. The REFDAC external voltage range is +0.7V to +2.5V. The MAX11014’s channel 1/channel 2 DACs set the sense voltage between RCS_+ and RCS_- by control- ling the GATE_ bias. See the MAX11014 Class A Control Loop section. The MAX11015’s channel 1/chan- nel 2 DACs drive the GATE_ outputs directly, indepen- dent of the current-sense voltages, through the gate-drive amplifier with a gain of -2. See theMAX11015 Class AB Control section. Set the channel 1/channel 2 DAC code by writing to the respective channel’s DAC input registers, DAC input and output registers, or V SET registers. Write to the DAC input registers (Table 16) and use a subsequent write to the software load DAC register (Table 21) to control the timing of the update. Write to the DAC input and output registers (Table 17) to set the DAC output voltage code directly, independent of the software load DAC register bits. Write to the V SET registers (Table 14) to include LUT data in the DAC code. Writing to the V SET registers triggers a V DAC(CODE) calculation as shown in the following equation: where VDAC(CODE) = The modified channel1/channel 2 12-bit DAC code. VSET(CODE) = The 12-bit DAC code written to the chan- nel 1/channel 2 VSET registers. LUTK[K] = The interpolated, fractional 12-bit K LUT value. The K LUT data is derived from a variety of sources, including: the V SET register value, the K para- meter register value, or various ADC channels. See the SRAM LUTs section. LUT TEMP[TEMP] = The interpolated, fractional 12-bit two’s-complement temperature LUT value. The tempera- ture LUT data is derived from either internal or external temperature values. See the SRAM LUTssection. The V DAC(CODE) equation code is then loaded into the DAC input register or DAC output register, depending on the corresponding channel’s LDAC bit in the soft- ware configuration register. See Table 11. Self-Calibration Calibrate channel 1 and channel 2 by writing to the PGA calibration control register. The MAX11014/MAX11015 function after power-up without a calibration. However, for best performance after pow- ering up, command a calibration by setting the TRACK bit to 0 and the DOCAL bit to 1 (see Table 18). Subsequently, set the TRACK, DOCAL, and SELFTIME bits to 1 to minimize loss of performance over tempera- ture and supply voltage. The self-calibration algorithm cancels offsets at the gate-drive amplifier inputs in approximately 95µV incre- ments to improve accuracy. The self-calibration routine can be commanded when the DACs are powered down, but the results will not be accurate. For best results, run the calibration after the DAC power-up time, t DPUEXT. The ADC’s operation is suspended during a self-calibration. The end of the self-calibration routine is indicated by the BUSY output returning low. See the BUSY Output section. Wait until the end of the self-cali- bration routine before requesting an ADC conversion. V V LUT K x LUT TEMPDAC CODE SET CODE K TEMP() () ( [ ] [ ])== + 1

Automatic RF MESFET Amplifier Drain-Current Controllers ADC/DAC References The MAX11014/MAX11015 provide an internal low- noise +2.5V reference for the ADCs, DACs, and tem- perature sensors. Set bits D3–D0 within the hardware configuration register to control the source of the DAC and ADC references. See Tables 10c and 10d. Connect a voltage source to REFADC between +1.0V and AV DD in external ADC reference mode. Connect a voltage source to REFDAC between +0.7V to +2.5V in external DAC reference mode. When using an external voltage reference, bypass REFADC and REFDAC with 0.1µF capacitors to AGND. Power Supplies The MAX11014/MAX11015 operate from separate ana- log and digital power supplies. Set the analog supply voltage, AV DD, between +4.75V and +5.25V. Set the digital supply voltage, DV DD, between +2.7V and AVDD. Bypass AVDD with a 0.1µF and 1µF capacitor to AGND and DV DD with a 0.1µF and 1µF capacitor to DGND. The analog circuitry typically consumes 2.8mA of supply current and the digital circuitry 3.7mA. Set the negative analog supply voltages, AV SS and GATEVSS, between -4.75V and -5.5V. Connect AVSS and GATEVSS together externally. Bypass each of these neg- ative supplies with a 0.1µF and 1µF capacitor to AGND. The RCS_+ inputs supply the power to the input section of the current-sense amplifiers. Set RCS_+ between +0.5V and +11V on the MAX11014 and +5V to +32V on the MAX11015. Bypass RCS_+ with a 0.1µF and 1µF capacitor to AGND. Serial Interface The MAX11014/MAX11015 feature a pin-selectable I 2C/SPI serial interface. Connect SPI/ I2C to GND to select I 2C mode, or connect SPI/ I2C to V DD to select SPI mode. SDA and SCL (I 2C mode) and DIN, SCLK, and CS (SPI mode) facilitate communication between the MAX11014/MAX11015 and the master. SPI Compatibility (SPI/I2C = DVDD) The MAX11014/MAX11015 communicate through a ser- ial interface, compatible with SPI and MICROWIRE devices. For SPI, ensure that the SPI bus master (typi- cally a µC) runs in master mode so it generates the ser- ial clock signal. Set the SCLK frequency to 20MHz or less, and set the clock polarity (CPOL) and phase (CPHA) in the µC control registers to the same value. The MAX11014/MAX11015 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. See Figure 1. Temperature values are available in signed two’s-com- plement format, while all others are in straight binary. A high-to-low transition on CS initiates the 24-bit data input cycle. Once CS is low, write an 8-bit command byte (MSB first) at DIN to indicate which internal regis- ter is being accessed. The command byte also identi- fies whether the data to follow is to be written into the serial interface or read out. See the Register Descriptions section. After writing the command byte, write two data bytes at DIN or read two data bytes at DOUT. Keep CS low throughout the entire 24-bit word write. The serial-interface circuitry is common to the ADC and DAC sections. When writing data, write an 8-bit command word and 16 data bits at DIN. See Figure 9. Data is input to the serial interface on the rising edge of SCLK. When read- ing data, write an 8-bit command byte at DIN and read the following 16 data bits at DOUT. See Figure 10. Data transitions at DOUT on the falling edge of SCLK. DIN can be set high or low while data is being transferred out at DOUT.

2C slave devices that transfer and receive data. undershoot of the bus signals. remain high when the bus is not busy. transmitted between the START and STOP conditions.

1. If the receiver returns a not-acknowledge bit

word, the remaining bits are lost. Figure 11. START and STOP Conditions

master should reattempt communication at a later time. for a high logic state or DGND for a low logic state. accept or send data depending on bit 8, the R/W bit. Figure 12. Acknowledge Bits

010 A 2 1A 1 A 0 R / W A

SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF ADDRESS-SELECT INPUT PINS A2, A1, AND A0. Figure 13. Slave Address Byte

edge signal by pulling SDA low for one clock cycle.

1. Read from the MAX11014/MAX11015 through the

in Table 2) of the previously assigned command byte. Figure 16. Read Cycle

a read operation. Set bit C7 to 0 for a write operation. Register Descriptions section. Figure 19. MAX11014/MAX11015 I2C Default Read Timing Table 1. Input Command Bits

Table 2. Register Listing

by writing command bytes A0h and ACh, respectively. ment format, with the LSB corresponding to +0.125°C. by writing command bytes A2h and AEh, respectively. ment format, with the LSB corresponding to +0.125°C. writing command bytes A4h and B0h, respectively. Table 3. TH1 and TH2 (Read/Write) Table 5. TL1 and TL2 (Read/Write) Table 4. High/Low Temperature ALARM Threshold Examples

mum positive GATE1 output voltage. See Table 10. D1 and D0, to determine the DAC reference source. Maximum GATE2 voltage control bits. CH1OCM0 D8 0 Maximum GATE1 voltage control bits. Clock mode and CNVST configuration bits. Table 9. VL1 and VL2 (Read/Write) Table 10. HCFG (Read/Write)

Automatic RF MESFET Amplifier Drain-Current Controllers Bits D15–D12 of the software configuration register are don’t care. Set the LDAC2 bit, D11, to 1 to load the new value of V DAC2, upon completion of a V DAC2(CODE) calculation, into both the channel 2 DAC input and out- put registers. See Figure 20. Set to 0 to load the new value of V DAC2, upon completion of a V DAC2(CODE) calculation, to only the channel 2 DAC input register. Set the T2COMP1/0 bits, D10 and D9, to control the channel 2 temperature LUT. See Table 11a. Set the KSRC2-2/1/0 bits, D8, D7, and D6, to control the chan- nel 2 K parameter LUT. See Table 11b and the SRAM LUTs section. Table 10b. Clock Modes Table 10c. ADC Reference Modes Table 10a. Maximum GATE_ Voltage Modes CH_OCM1 CH_OCM0 FUNCTION 0 0 Maximum positive voltage at GATE_ = AGND. 0 1 Maximum positive voltage at GATE_ = AGND + 250mV. 1 0 Maximum positive voltage at GATE_ = AGND + 500mV. 1 1 Maximum positive voltage at GATE_ = AGND + 750mV. CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/SAMPLING 0 0 Internal Internally timed acquisitions and conversions. Default state. Begin a conversion by writing to the ADC conversion register to convert all channels specified in this register. 0 1 Internal Internally timed acquisitions and conversions. Begin a conversion by pulling CNVST low only once for at least 20ns to convert all of the channels selected in the ADC conversion register. 1 0 Reserved Do not use. 1 1 Internal Externally timed single acquisitions. Conversions internally timed. Begin each individual conversion by pulling CNVST low for each channel converted. See the Electrical Characteristics table for CNVST timing. The MAX11014/MAX11015 acquire while CNVST is low and sample when CNVST returns high. ADCREF1 ADCREF0 ADC VOLTAGE REFERENCE 0 X External. Bypass REFADC with a 0.1µF capacitor to AGND. 10 Internal. Leave REFADC unconnected. 1 1 Internal. Bypass REFADC with a 0.1µF capacitor to AGND for better noise performance. Table 10d. DAC Reference Modes DACREF1 DACREF0 DAC VOLTAGE REFERENCE 0 X External. Bypass REFDAC with a 0.1µF capacitor to AGND. 10 Internal. Leave REFDAC unconnected. 1 1 Internal. Bypass REFDAC with a 0.1µF capacitor to AGND for better noise performance. X = Don’t care. X = Don’t care.

into both the channel 1 DAC input and output registers. nel 1/channel 2 VSET registers. temperature values.See theSRAM LUTs section. must be configured to provide these samples. Figure 20. DAC Register Format

Table 11. SCFG (Read/Write) value from the DAC input register to the DAC output. T2COMP0 D9 0 Channel 2 temperature LUT control bits. Channel 2 K LUT control bits. from the DAC input register to the DAC output. Channel 1 temperature LUT control bits. Channel 1 K LUT control bits.

Automatic RF MESFET Amplifier Drain-Current Controllers Table 11a. Channel 1/Channel 2 Temperature LUT Control Modes Table 11b. Channel 1/Channel 2 K LUT Control Modes KSRC_-2 KSRC_-1 KSRC_-0 FUNCTION 000 No K LUT operations performed. This bit setting simplifies the VDAC(CODE) calculation to: VDAC(CODE) = VSET(CODE) (1 + LUTTEMP[TEMP])

001 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) (1 + LUTK[VSET] x LUTTEMP[TEMP])

010 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) (1 - LUTK[USRK] x LUTTEMP[TEMP])

011 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) (1 + LUTK[sense voltage] x LUTTEMP[TEMP])

100 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) (1 + LUTK[ADCIN_] x LUTTEMP[TEMP])

101 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) + USRK x LUTK[VSET] x LUTTEMP[TEMP]

110 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) + USRK x LUTK[sense voltage] x LUTTEMP[TEMP]

111 The VDAC(CODE) calculation simplifies to:

VDAC(CODE) = VSET(CODE) + USRK x LUTK[ADCIN_] x LUTTEMP[TEMP] T_COMP1 T_COMP0 FUNCTION A change in temperature does not trigger a VDAC(CODE) calculation. Any VDAC(CODE) calculation triggered in another way does not include the temperature lookup. This bit setting simplifies the VDAC(CODE) calculation to VDAC(CODE) = VSET(CODE) (1 + LUTK[K]). A change in temperature does not trigger a VDAC(CODE) calculation. Any VDAC(CODE) calculation triggered in another way does not include the temperature lookup. This bit setting simplifies the VDAC(CODE) calculation to VDAC(CODE) = VSET(CODE) (1 - LUTK[K]). A change in the channel 1/channel 2 external temperature sensor reading triggers a VDAC(CODE) calculation for the corresponding DAC channel. When a VDAC(CODE) calculation is triggered, the calculation includes the temperature lookup function. A change in the internal temperature sensor reading triggers a VDAC(CODE) calculation for the corresponding channel. When a VDAC(CODE) calculation is triggered, the calculation includes the temperature lookup function.

output in interrupt mode. See Figure 25. and channel 2. See Table 12b. ALARM output to be push-pull. comparisons for channel 2 to use the external temperature conversion result. ALMCMP D10 0 ALARM comparator bit. Set to 1 to configure the ALARM output in comparator mode. Set to 0 to configure the ALARM output in interrupt mode. voltage and temperature ALARM measurements in both channels. ALM2CLMP0 D4 0 Channel 2 ALARM clamp bits. ALM1CLMP0 D2 0 Channel 1 ALARM clamp bits. force the ALARM output to be active-high. configure the ALARM output as a push-pull output (no external resistor required). Table 12. ALMHCFG (Read/Write)

Automatic RF MESFET Amplifier Drain-Current Controllers ALMSCFG (Read/Write) The software ALARM configuration register controls which voltage and temperature channels trigger the ALARM output and whether the ALARM comparators operate in windowing or hysteresis mode. Set the com- mand byte to 3Eh to write to the software ALARM con- figuration register. Set the command byte to BEh to read the software ALARM configuration register. Bits D15–D12 are don’t care. Set the VALARM2 bit, D11, to 1 to enable alarm functionality for GATE2 voltage mea- surements. Set the VWIN2 bit, D10, to 1 to monitor the GATE2 voltage with the ALARM comparator in window- ing mode. Set VWIN2 to 0 to monitor the GATE2 voltage with the ALARM comparator in hysteresis mode. Set the TALARM2 bit, D9, to 1 to enable alarm function- ality for channel 2 temperature measurements. Set the TWIN2 bit, D8, to 1 to monitor the channel 2 tempera- ture with the ALARM comparator in windowing mode. Set TWIN2 to 0 to monitor the channel 2 temperature with the ALARM comparator in hysteresis mode. Set the IALARM2 bit, D7, to 1 to enable alarm functionality for channel 2 sense voltage (RCS2+ to RCS2-) measure- ments. Set the IWIN2 bit, D6, to 1 to monitor the chan- nel 2 sense voltage with the ALARM comparator in windowing mode. Set IWIN2 to 0 to monitor the channel 2 sense voltage with the ALARM comparator in hystere- sis mode. ITHYST1 ITHYST0 FUNCTION 0 0 8 LSBs of hysteresis. 0 1 16 LSBs of hysteresis. 1 0 32 LSBs of hysteresis. 1 1 64 LSBs of hysteresis. Table 12b. Sense Voltage/Temperature Hysteresis Levels ALM_CLMP1 ALM_CLMP0 FUNCTION Default state. The GATE_ outputs are clamped to the respective external voltage applied at ACLAMP_ independent of alarms. GATE_ remains clamped until this register value is changed or a software clear command is issued. The corresponding ALARM bit in the ALARM flag register goes high if an alarm condition is triggered by a conversion of sense voltage, temperature, or GATE_ voltage. However, the GATE_ outputs are not clamped. Fully automatic clamping. The GATE_ outputs are clamped to the respective external voltage applied at ACLAMP_ when an alarm condition is triggered. The clamp is removed if a subsequent temperature or sense voltage conversion removes the alarm condition. GATE_ remains clamped when a GATE_ voltage alarm is triggered. For a GATE_ voltage alarm, ALM_CLMP 10 mode functions the same as 11 mode. This exception breaks the feedback loop created by sampling GATE_ voltage and then clamping the same signal. Semi-automatic clamping. The GATE_ outputs are clamped to the respective external voltage applied at ACLAMP_ when an alarm condition is triggered. If an ALARM condition is triggered, the ALM_CLMP bits are overwritten to 00, causing a permanent clamp condition. Clear this permanent clamp condition with a subsequent write to reset the ALM_CLMP bits. Table 12c. ALARM Clamp Modes VGHYST1 VGHYST0 FUNCTION 0 0 8 LSBs of hysteresis. 0 1 16 LSBs of hysteresis. 1 0 32 LSBs of hysteresis. 1 1 64 LSBs of hysteresis. Table 12a. GATE Voltage Hysteresis Levels

ALARM comparator in hysteresis mode. channel 2 temperature measurements. temperature with the ALARM comparator in hysteresis mode. channel 2 sense voltage measurements. channel 2 sense voltage with the ALARM comparator in hysteresis mode. ALARM comparator in hysteresis mode. channel 1 temperature measurements. temperature with the ALARM comparator in hysteresis mode. channel 1 sense voltage measurements. channel 1 sense voltage with the ALARM comparator in hysteresis mode. Table 13. ALMSCFG (Read/Write)

the V SET(CODE) code in the V DAC(CODE) equations. to write to the channel 2 V SET register. See Table 14. K[K] code in the V DAC(CODE) equation.

1. See Table 11b. Use the K parameter as an index

don’t care. Bits D11–D0 contain the straight binary data. Table 14. VSET1 and VSET2 (Write) VSET11–VSET0 D11–D0 0000 0000 0000 VSET11 is the MSB and VSET0 is the LSB. Data format is straight binary. Table 15. USRK1 and USRK2 (Write) K11–K0 D11–D0 N/A K11 is the MSB and K0 is the LSB. Data format is straight binary.

registers. See Table 17. Bits D15–D12 are don’t care. Bits D11–D0 contain the straight binary data. the channel 1 and channel 2 current-sense amplifiers. and commanding a sense-voltage ADC conversion. Table 16. IPDAC1 and IPDAC2 (Write) DAC11–DAC0 D11–D0 0000 0000 0000 DAC11 is the MSB and DAC0 is the LSB. Data format is straight binary. Table 17. THRUDAC1 and THRUDAC2 (Write) DAC11–DAC0 D11–D0 N/A DAC11 is the MSB and DAC0 is the LSB. Data format is straight binary. Table 18. PGACAL (Write) PGAOUT2 output and the channel 2 current-sense conversion. PGAOUT1 output and the channel 1 current-sense conversion. performing the next self-timed calibration. calibration only occurs when DOCAL is set to 1.

Automatic RF MESFET Amplifier Drain-Current Controllers The current-sense calibration routine offers two opera- tion modes: acquisition and tracking. In acquisition mode, the calibration routine operates continuously until the error is minimized to 50µV or less. In tracking mode, the routine operates every 15ms to minimize interference and allow the calibration routine more averaging time. A sample-and-hold circuit prevents switching noise on GATE_ during tracking mode. Set the TRACK bit, D2, to 0 to run the calibration routine in acquisition mode. Set TRACK to 1 to run the calibration routine in tracking mode. Set TRACK to 0 for the first calibration. Set the DOCAL bit, D1, to 1 to run a current-sense self-calibration routine in both channel 1 and channel 2. At the end of the calibration routine, DOCAL is set back to 0. Set the SELFTIME bit, D0, to 1 to perform a cur- rent-sense calibration on a periodic basis, typically every 15ms. Use the DOCAL bit in conjunction with the SELFTIME bit. When a calibration routine is command- ed by DOCAL, and SELFTIME is set to 1, the internal timer is reset at the end of the routine and waits another 15ms before performing the next self-timed calibration. The self-calibration routine can be commanded when the DACs are powered down, but the results are not accurate. For best results, run the calibration after the DAC power-up time, t DPUEXT. ADCCON (Write) Write to the ADC conversion register to convert the ADCIN_, GATE_, internal DAC and sense voltages. The ADC conversion register also converts the internal and external temperature readings and sets the interface for continuous conversion. See Table 19. Set the com- mand byte to 62h to write to the ADC conversion regis- ter. Bits D15–D12 are don’t-care bits. The ADCMON bit in the hardware configuration register must be set to 1 to load ADC results into the FIFO. Set the CONCONV bit, D11, to 1 for continuous ADC conversions. Set the CH10 bit, D10, to 1 to convert the ADCIN2 volt- age. Set the CH9 bit, D9, to 1 to convert the GATE2 voltage. Set the CH8 bit, D8, to 1 to convert the channel 2 DAC code. Set the CH7 bit, D7, to 1 to convert the channel 2 sense voltage. Set the CH6 bit, D6, to 1 to convert the channel 2 external temperature sensor measurement. Set the CH5 bit, D5, to 1 to convert the ADCIN1 voltage. Set the CH4 bit, D4, to 1 to convert the GATE1 voltage. Set the CH3 bit, D3, to 1 to convert the channel 1 DAC code. Set the CH2 bit, D2, to 1 to convert the channel 1 sense voltage. Set the CH1 bit, D1, to 1 to convert the channel 1 external temperature sensor measurement. Set the CH0 bit, D0, to 1 to con- vert the internal temperature sensor measurement. Convert any combination of ADC channels through the ADC conversion register. When requesting a conver- sion of more than one channel, the channels are con- verted in numerical order from CH0 to CH10. Setting the CONCONV bit to 1 may cause the FIFO to overflow if data is not read out quickly enough. Continuous-conversion mode is only available in clock modes 00 and 01. See the Clock Mode 00 and Clock Mode 01 sections. The ADC does not trigger a busy signal when the CONCONV bit is set. If a temperature channel is included in the scan when CONCONV is set, the internal reference and temperature sensor remain powered up until CONCONV is set to 0. Similarly, if an ADC measurement using the internal reference is included in the scan, the internal reference is turned on prior to the first conversion and remains on until CONCONV is set to 0. In clock modes 00 and 01, when the CONCONV bit is set to 0 and the current scan (not just the current con- version) is completed, the ADC goes to an idle state awaiting the next command. The BUSY output is set high when the CONCONV bit is set to 0 and remains high until the current scan is completed. See the BUSY Output section. SHUT (Write) Shut down all internal blocks, as well as the DACs, ADCs, and gate-drive amplifiers individually, through the shutdown register. See Table 20. Set the command byte to 64h to write to the shutdown register. Bits D15–D12 are don’t care. Set the FULLPD bit, D11, to 1 to shut down all internal blocks and reduce AV DD sup- ply current to 0.8µA. The FULLPD bit is set to 1 at power-up. Set the FULLPD bit to 0 before writing any other commands to activate all internal blocks and functionality. Set the FBGON bit, D10, to 1 to keep the internal bandgap reference powered up. Set the WDGPD bit, D9, to 1 to turn off the watchdog oscillator and prevent self-monitoring of the watchdog timer. Set the OSCPD bit, D8, to 1 to power down the internal oscillator. Set the PD2-3 bit, D7, to 1 to power down the channel 2 current-sense amplifier. Set the PD2-2 bit, D6, to 1 to power down the channel 2 gate-drive amplifier. Set the PD2-1 bit, D5, to 1 to power down the channel 2 DAC summing node. Set the PD2-0 bit, D4, to 1 to power down the channel 2 DAC. Set the PD1-3 bit, D3, to 1 to power down the channel 1 current-sense amplifier. Set the PD1-2 bit, D2, to 1 to power down the channel 1 gate-drive amplifier. Set the PD1-1 bit, D1, to 1 to power down the channel 1 DAC summing node. Set the PD1-0 bit, D0, to 1 to power down the channel 1 DAC.

write to the software load DAC register. See Table 21. Table 19. ADCCON (Write) CH10 D10 0 Set to 1 to convert the ADCIN2 voltage in the next ADC conversion cycle. CH9 D9 0 Set to 1 to convert the GATE2 voltage in the next ADC conversion cycle. Also, the PD2-3 bit in the shutdown register must be set to 0. measurement in the next ADC conversion cycle. CH5 D5 0 Set to 1 to convert the ADCIN1 voltage in the next ADC conversion cycle. CH4 D4 0 Set to 1 to convert the GATE1 voltage in the next ADC conversion cycle. Also, the PD1-3 bit in the shutdown register must be set to 0. measurement in the next ADC conversion cycle.

Table 20. SHUT (Write) Table 21. LDAC (Write) to activate all internal blocks. bandgap voltage as required by the ADC. self-monitoring function of the watchdog timer. reset to 0 after receiving the next interface command. PD2-3 D7 1 Set to 1 to power down the channel 2 current-sense amplifier. PD2-2 D6 1 Set to 1 to power down the channel 2 gate-drive amplifier. PD2-0 D4 1 Set to 1 to power down the channel 2 DAC. PD1-3 D3 1 Set to 1 to power down the channel 1 current-sense amplifier. PD1-2 D2 1 Set to 1 to power down the channel 1 gate-drive amplifier. PD1-0 D0 1 Set to 1 to power down the channel 1 DAC. in the channel 2 DAC input register. in the channel 1 DAC input register.

74h to write to the software clear register. See Table 22.

• Write to the software clear register once with FULLRESET = 0 and ARMRESET = 1.
• Write a second word to the software clear register with FULLRESET = 1 and ARMRESET = 0. The full reset takes effect after completion of the second write to this register. Set the ALMSCLR bit, D4, to 1 to reset all ALARM thresh- old register bits and the ALARM flag register bits. Set the CACHECLR bit, D3, to 1 to force the ALU to clear the pointers and lookup value cache to their power-up val- ues. This forces a LUT operation and a V DAC(CODE) cal- culation for the next sample, regardless of whether the sample produces a table pointer that is different. Set the FIFOCLR bit, D2, to 1, reset the FIFO address pointers, and clear the FIFO’s contents. Set the DAC2CLR bit, D1, to 1 to reset the channel 2 DAC input and output register bits. Set the DAC1CLR bit, D0, to 1 to reset the channel 1 DAC input and output register bits.

Table 22. SCLR (Write) Table 23. LUTADD (Write) FULLRESET = 1 and ARMRESET = 0. state, but the internal oscillator remains running (unlike at power-up). RAM before setting BUSY low. produces a table pointer that is different. FIFOCLR D2 N/A Set to 1 to reset the FIFO address pointers and clear the FIFO’s contents. DAC2CLR D1 N/A Set to 1 to reset the channel 2 DAC input and output registers. DAC1CLR D0 N/A Set to 1 to reset the channel 1 DAC input and output registers.

pointer, and the LUT configuration word. See Table 23. for the read/write operation. Write or read LUT data through the LUT data register. data register write command. LUT data channel tag 110_. See Table 25. Table 24. LUTDAT (Read/Write) LUTDAT0 D15–D0 N/A The 16-bit data word written to the LUT data or configuration memory space. Table 25. FIFO 0000 MSB — LSB Internal temperature sensor. 0001 MSB — LSB Channel 1 external temperature sensor. 0010 MSB — LSB Channel 1 sense voltage. 0011 MSB — LSB Channel 1 DAC input register. 0100 MSB — LSB Channel 1 GATE voltage. 0101 MSB — LSB ADCIN1 voltage. 0110 MSB — LSB Channel 2 external temperature sensor. 0111 MSB — LSB Channel 2 sense voltage. 1000 MSB — LSB Channel 2 DAC input register. 1001 MSB — LSB Channel 2 GATE voltage. 1010 MSB — LSB ADCIN2 voltage.

1110 MSB — LSB

out in place of the FIFO data.

and bit D0 is the LSB. See Table 25.

1. The RESTART bit, D6, is set to 1 after either a

ALU is performing a PGA calibration. Table 26. FLAG (Read) software reset through the software clear register’s FULL RESET function. RESTART returns to 0 after a power-on reset or a flag register read command. internal memory initialization after power-up. the ADC completes all of the conversions in the current scan. VDAC(CODE) calculation for either channel. FIFOCLR set to 1 causes the FIFO to be cleared, which then sets FIFOEMP to 1. 1) Reading the ADC data: FIFOOVR is set to 1 if the FIFO has a data overflow. the LUT is full and set to 0 if the LUT is not full, for that instant in time only.

Table 27. ALMFLAG (Read) or a software clear command. flag register or a software clear command. flag register or a software clear command. ALARM flag register or a software clear command. ALARM flag register or a software clear command. either a read of the ALARM flag register or a software clear command. or a software clear command. flag register or a software clear command. flag register or a software clear command. ALARM flag register or a software clear command. ALARM flag register or a software clear command. either a read of the ALARM flag register or a software clear command.

Automatic RF MESFET Amplifier Drain-Current Controllers The ADCBUSY bit, D3, is set to 1 when the ADC is busy, an ALARM value is being checked, or the ADC results are being loaded into the FIFO. ADCBUSY returns to 0 after the ADC completes all of the conver- sions in the current scan. The VGBUSY bit, D2, is set to 1 when the ALU is performing a lookup and interpola- tion or V DAC(CODE) calculation for either channel. The FIFOEMP bit, D1, is set to 1 when the FIFO is empty and contains no data. FIFOEMP is reset to 0 if data is written into the FIFO. Writing to the software clear regis- ter with FIFOCLR set to 1 causes the FIFO to be cleared, which then sets FIFOEMP to 1. The functionality of the FIFOOVR bit, D0, depends on whether the FIFO is loaded with ADC data or LUT data. FIFOOVR functions in one of two modes: 1) Reading the ADC data: FIFOOVR is set to 1 if the FIFO has a data overflow. FIFOOVR is reset to 0 only by reading the flag register or by clearing the FIFO through the software clear register. Emptying the FIFO does not clear the FIFOOVR bit. 2) Reading the LUT data: When commanding a LUT read, the FIFO is no longer allowed to overflow. FIFOOVR is set to 1 if the LUT is full and set to 0 if the LUT is not full, for that instant in time only. See the FIFO Description section. ALMFLAG (Read) Read the ALARM flag register to determine the source of an alarm condition. Set the command byte to F8h to read the ALARM flag register. Bits D15–D12 are don’t care. See Table 27. Bits D11–D0 are all reset to 0 following a read of the ALARM flag register or a software clear com- mand. The HIGH-V2 bit, D11, is set to 1 when the GATE2 voltage exceeds the high threshold setting. The LOW-V2 bit, D10, is set to 1 when the GATE2 voltage decreases below the low threshold setting. The HIGH-I2 bit, D9, is set to 1 when the channel 2 sense voltage exceeds the high threshold setting. The LOW-I2 bit, D8, is set to 1 when the channel 2 sense voltage decreases below the low threshold setting. The HIGH-T2 bit, D7, is set to 1 when the channel 2 external temperature exceeds the high threshold setting. The LOW-T2 bit, D6, is set to a 1 when the channel 2 external temperature decreases below the low threshold setting. The HIGH-V1 bit, D5, is set to 1 when the GATE1 volt- age exceeds the high threshold setting. The LOW-V1 bit, D4, is set to 1 when the GATE1 voltage decreases below the low threshold setting. The HIGH-I1 bit, D3, is set to 1 when the channel 1 sense voltage exceeds the high threshold setting. The LOW-I1 bit, D2, is set to 1 when the channel 1 sense voltage decreases below the low threshold setting. The HIGH-T1 bit, D1, is set to 1 when the channel 1 external temperature exceeds the high threshold setting. The LOW-T1 bit, D0, is set to a 1 when the channel 1 external temperature decreases below the low threshold setting. FIFO Description The MAX11014/MAX11015’s FIFO stores 15 ADC sam- ples or 16 SRAM LUT data words. Read the FIFO to load the FIFO data onto DOUT in SPI mode and SDA in I 2C mode. See Table 25. The ADC sample data includes a 4-bit channel tag, followed by 12 bits of data. The ADC channel tags indicate the source for the temperature or voltage result. The LUT data includes a 3-bit channel tag for LUT configuration word data and a 4-bit tag for all other LUT data. The LUT tags indicate whether the LUT data is temperature (T) or numerical (K)-based. Do not mix ADC results with LUT results in the FIFO. The FIFO allows overflows of ADC data and it always contains the 15 most recent ADC conversion results. Read the FIFO quickly enough to prevent an overflow condition. Detect if the FIFO has overflowed (indicating a loss of data) by inspecting the FIFOOVR bit in the flag register. The FIFO does not overflow while outputting SRAM LUT data. Count how many words are output in order (through the numerical representation of the LUTWORD bits in the LUT address register) to tell which LUT data word is being supplied. ADC Monitoring Mode Each time the ADC converts a sample in ADC monitor- ing mode, the data word and its 4-bit channel tag are moved into the FIFO. Load the data from the FIFO to DOUT in SPI mode and SDA in I 2C mode by writing command byte 80h. The hardware configuration register’s ADCMON bit determines whether ADC samples are loaded into the FIFO. See Table 10. Set ADCMON to 1 to store ADC samples in the FIFO. Set to 0 to not load ADC results into the FIFO. The value of ADCMON does not affect whether the results from any particular ADC conversion are checked against the ALARM thresholds or exam- ined for changes to the V DAC(CODE) equations. After reading out all of the ADC FIFO data, the flag regis- ter sets the FIFOEMP bit to 1. If a FIFO read command is issued with the FIFO empty, the FIFO returns a channel tag of 1111 and the 12 flag register bits. See Table 25. The FIFO allows interface reads to be simultaneous with the arrival of new ADC sample or LUT data words. But when the FIFO is full and overflowing, if an ADC sample arrives at exactly the same time as an interface read, there is a possibility of data corruption. This condition is

valid and can be accessed with subsequent reads. to the FIFO faster than its read out, the FIFO fills up. transfer functions, respectively. halfway between successive-integer LSB values. MAX11014’s Class A control loop detailed in Figure 5. Figure 6. Calculate the PGAOUT_ voltage with the fol-

1 LSB = VREFADC / 4096

Figure 21. ADC Transfer Function Figure 22. Temperature Transfer Function

PGAOUT_ output and ADC input. The BUSY output goes high for a variety of reasons.

• The ADC is converting, but not in continuous con- version mode
• The internal ALU core is performing a power-up initialization
• The internal ALU core is performing a V DAC(CODE) calculation
• The internal ALU core is performing another function
• The self-calibration routine is taking place When the CONCONV bit is set in the ADC conversion register, the BUSY output does not trigger when the ADC is converting (for all clock modes). This prevents the continuous ADC activity from masking other BUSY events. The serial interface remains available regardless of the state of BUSY, although certain commands are not appropriate. For example, if BUSY is high for an ADC operation, reading the FIFO does not produce the result for the current conversion. Also, if BUSY triggers due to an ADC conversion, do not enter a second con- version command until BUSY returns low, indicating the previous conversion is complete. See Figure 23 for a pair of BUSY timing examples. In example 1, an externally timed ADC conversion trig- gers the ADCBUSY bit in the flag register and forces BUSY high. Next, a V DAC(CODE) calculation triggers the ALUBUSY bit in the flag register and holds BUSY high. In example 2, the V DAC(CODE) calculation is not requested. CNVST GATE1/2 OUTPUT BUSY (OUTPUT) BUSY TIMING: EXAMPLE 1 ADCBUSY (FLAG REGISTER BIT) ALUBUSY (FLAG REGISTER BIT) CNVST BUSY OUTPUT ADCBUSY (FLAG REGISTER BIT) ALUBUSY (FLAG REGISTER BIT) BUSY TIMING: EXAMPLE 2

Figure 23. BUSY Timing

register values. See Table 13 and Figure 24. dowing or hysteresis conditions are satisfied. Figure 26. ALARM Hysteresis Comparator Example

GATE_ voltage and then clamping that same voltage.

• ALM_CLMP1/ALM_CLMP0 = 11 This mode provides semi-automatic clamping. Prior to an alarm condition, the GATE_ voltage is controlled by the sense voltage (MAX11014) or the DAC setting (MAX11015). When an alarm condition is triggered, the GATE_ voltage clamps to ACLAMP_. The clamp holds the GATE_ output in this condition, even if sub- sequent ADC samples are taken and all ALARM channels are cleared. To release the clamp, rewrite the ALM_CLMP1/ALM_CLMP0 bits to 11 or 01. OPSAFE Inputs Set the OPSAFE1 and OPSAFE2 inputs high to clamp the GATE1 and GATE2 outputs to the externally applied voltage at ACLAMP1 and ACLAMP2, respectively. OPSAFE1/OPSAFE2 override any software commands. The ALM_CLMP1/ALM_CLMP0 bits in the hardware ALARM configuration register also provide clamping functionality. SRAM LUTs The MAX11014/MAX11015 implement four independent lookup tables (LUTs). The LUTs are temperature based (TLUT) and numeric based (KLUT). Channel 1 and channel 2 each have a separate T and K LUT. Each LUT can store up to 48 separate data words. See

Figure 28. In addition to storing data values, the LUT 28 details how the LUTs are configured in memory. are don’t care in LUT writes). 2) Write to the LUT data register to write data values. ber of locations based on the LUTWORD code. (channel 2) values are stored at addresses 30h to 5Fh. size, hysteresis threshold size, and size of the LUT. and size of the LUT. See Table 28b.

Figure 28. LUT Memory Space

Do not write to these locations. Table 28. LUT Addresses Configuration C0 1 1 0 See Table 28b for bit details. Configuration C1 1 1 0 See Table 28b for bit details. Configuration C2 1 1 0 See Table 28b for bit details. Configuration C3 1 1 0 See Table 28b for bit details.

Automatic RF MESFET Amplifier Drain-Current Controllers BIT NAME DATA BIT RESET FUNCTION SIZE5 D12 0 SIZE4 D11 0 SIZE3 D10 0 SIZE2 D9 0 SIZE1 D8 0 SIZE0 D7 0 The SIZE field is a straight binary representation of the size of the respective LUT. SIZE5 is the MSB of the 6 SIZE bits. SIZE0 is the LSB. Set the size of the LUT between eight entries (001000) and 48 entries (110000). HYS2 D6 0 HYS1 D5 0 HYS0 D4 0 The HYS2, HYS1, and HYS0 bits set the hysteresis bit threshold for each LUT. When the difference between the last index value and the next index value is less than the value set by HYS2, HYS1, and HYS0 bits, the LUT operation for that parameter is omitted and the last value calculated for the respective LUT is used. Set the HYS2 (MSB), HYS1, and HYS0 (LSB) bits to the following hysteresis bit values: 000: 0 bits (a new LUT operation is always performed) 001: 1 bit (if the value differs by 1 bit, a new LUT operation is performed) 010: 2 bits 011: 4 bits 100: 8 bits 101: 16 bits 110: 32 bits 111: 64 bits STEP3 D3 0 STEP2 D2 0 STEP1 D1 0 STEP0 D0 0 The STEP3–STEP0 bits determine the LUT 12-bit step size. The step size is a 2 N value. The N value is determined by the STEP bits, with STEP3 being the MSB and STEP0 the LSB. See Table 28c for the TLUT and KLUT step-size equivalents. Table 28b. LUT Configuration STEP3 STEP2 STEP1 STEP0 LUT STEP SIZE TLUT STEP-SIZE EQUIVALENT KLUT STEP-SIZE EQUIVALENT 0 0 0 0 1 +0.125°C 1 0 0 0 1 2 +0.25°C 2 0 0 1 0 4 +0.5°C 4 0 0 1 1 8 +1°C 8 0 1 0 0 16 +2°C 16 0 1 0 1 32 +4°C 32 0 1 1 0 64 +8°C 64 0 1 1 1 128 +16°C 128 1 0 0 0 256 +32°C 256 1 0 0 1 512 +64°C 512 1 0 1 0 Reserved. Do not use. 1 0 1 1 Reserved. Do not use. 1 1 0 0 Reserved. Do not use. 1 1 0 1 Reserved. Do not use. 1 1 1 0 Reserved. Do not use. 1 1 1 1 Reserved. Do not use. Table 28c. LUT Configuration Step Sizes

(+0.9995) in steps of approximately 0.0005. the step size is 128 (+16°C between each entry). Figure 29. TLUT Example

sion register to indicate which channels to convert. pulled low and the results are available in the FIFO. Clock mode 10 is reserved. Do not use this clock mode. voltage using the internal reference conversion. Electrical Characteristics table for more details. results are available after an additional 3.5µs (typ). the conversion results are available after 5.6µs. CLOCK MODE 11 EXAMPLE 1: COMMAND A SCAN OF CHANNELS 0, 5, AND 10 WITH AN INTERNAL REFERENCE. *ALL TIMING SPECIFICATIONS ARE TYPICAL. Figure 31. Clock Mode 11 Timing Example 1

• CKSEL1/CKSEL0 = 00 and is then changed to another value: The ADC completes the already triggered series of conversions and then goes idle. The BUSY output remains high until the conversions are completed. The MAX11014/MAX11015 then responds according to commands with the new clock mode.
• CKSEL1/CKSEL0 = 01 and is then changed to another value: If waiting for the initial external trigger, the MAX11014/MAX11015 immediately exit clock mode 01, power down the ADC, and go idle. If a conversion sequence is in progress, that conver- sion is completed and then the ADC goes idle. The BUSY output remains high until the conversions are completed. The MAX11014/MAX11015 then respond according to commands with the new clock mode.
• CKSEL1/CKSEL0 = 11 and is then changed to another value: If waiting for an external trigger, the MAX11014/ MAX11015 immediately exit clock mode 11, power down the ADC, and go idle. The BUSY output stays low and waits for the external trigger. If a conversion sequence is in progress, that con- version is completed and then the ADC goes idle. Applications Information Layout Considerations For the external temperature sensor to perform to spec- ifications, care must be taken to place the MAX11014/MAX11015 as close as is practical to the remote diode. Traces of DXP_ and DXN_ should not be routed across noisy lines and buses. DXP_ and DXN_ routes should be guarded by ground traces on either sides and should be routed over a quiet ground plane. Traces should be wide enough (> 10mm) to lower inductance, which tends to pick up radiated noise. BUSY CNVST WRITE TO THE ADC CONVERSION REGISTER TO SET UP THE SCAN CH6 (EXTERNAL TEMPERATURE) RESULT LOADED INTO THE FIFO CLOCK MODE TIMING EXAMPLE 2: COMMANDS A SCAN OF CHANNELS 5, 6, AND 10 WITH AN INTERNAL REFERENCE. INTERNALLY* INT REFERENCE POWERS UP IN 45μs 1.5 μs ACQUISITION OF CH5 TEMPERATURE CONVERSION IN 30μs IDLE, BUT REFERENCE STAYS POWERED UP 3.5 μs CONVERSION TIME FOR CH5 IDLE, BUT REFERENCE AND TEMPERATURE SENSOR STAY POWERED UP 1.5 μs ACQUISITION FOR CH10 3.5 μs CONVERSION TIME FOR CH10 END OF SCAN, REFERENCE AND TEMPERATURE SENSOR POWER DOWN AUTOMATICALLY CH5 LOADED INTO THE FIFO CH10 LOADED INTO THE FIFO tPUINT tACQ11tCNV11 TEMP SENSOR POWERS UP , ACQUIRES IN 5 μs *ALL TIMING SPECIFICATIONS ARE TYPICAL.

Figure 32. Clock Mode 11 Timing Example 2

Automatic RF MESFET Amplifier Drain-Current Controllers Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. INL for the MAX11014/MAX11015 is measured using the end- point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. ADC Offset Error For an ideal converter, the first transition occurs at 0.5 LSB, above zero. Offset error is the amount of deviation between the measured first transition point and the ideal first transition point. ADC Gain Error When a positive full-scale voltage is applied to the con- verter inputs, the digital output is all ones (FFFh). The transition from FFEh to FFFh occurs at 1.5 LSB below full scale. Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed. DAC Offset Error DAC offset error is determined by loading a code of all zeros into the DAC and measuring the analog output voltage. DAC Gain Error DAC gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all 1s into the DAC. Aperture Jitter Aperture jitter, t AJ, is the statistical distribution of the variation in the sampling instant. Aperture Delay Aperture delay (t AD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full- scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): In reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist fre- quency excluding the fundamental, the first five har- monics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist fre- quency excluding the fundamental and the DC offset: Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quanti- zation noise only. With an input range equal to the full- scale range of the ADC, calculate the effective number of bits as follows: Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: where V 1 is the fundamental amplitude, and V 2 through V6 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spectral component. THD x VVVVV V log = ++++20 2 ENOB SINAD ( . ) / .=− 17 6 60 2 SINAD dB x SIGNAL NOISE RMS RMS ( ) log ( / )= 20 SNR x N dB (. . )=+ 60 2 17 6

Automatic RF MESFET Amplifier Drain-Current Controllers ADC Channel-to-Channel Crosstalk Bias the ON channel to midscale. Apply a full-scale sine- wave test tone to all OFF channels. Perform an FFT on the ON channel. ADC channel-to-channel crosstalk is expressed in dB as the amplitude of the FFT spur at the frequency associated with the OFF channel test tone. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f2, are present at the inputs. The intermodulation prod- ucts are (f1 ±f 2), (2 x f1), (2 x f2), (2 x f1 ±f 2), (2 x f2 ± f1). The individual input tone levels are at -7dBFS. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in such a way that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the track/hold (T/H) performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as full- power input bandwidth frequency. DAC Digital Feedthrough DAC digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital con- trol lines are toggled. ADC Power-Supply Rejection Power-supply rejection is defined as the shift in offset error when the power supply is moved from the minimum operating voltage to the maximum operating voltage. DAC Power-Supply Rejection DAC PSR is the amount of change in the converter’s value at full scale as the power-supply voltage changes from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the power-supply voltage. Chip Information PROCESS: BiCMOS TOP VIEW MAX11014 MAX11015 TQFN 7mm x 7mm X 0.8mm ACLAMP2 GATE2 GATEV SS N.C. ACLAMP1 GATE1 FILT1 FILT2 FILT3 FILT4 PGAOUT1 PGAOUT2 1 2 3456789 1 0 11 12 SCLK/SCL N.C./A2 SPI/I2C CS/A0 ALARM CNVST DGND DV DD BUSY OPSAFE2 OPSAFE1 N.C. AGND AVDD REFADC REFDAC DXP2 DXN2 DXP1 DXN1 ADCIN2 ADCIN1 DOUT/A1 DIN/SDA 36 35 34 33 32 31 30 29 28 27 26 25 AGND AVDD AVSS N.C. N.C. RCS2+ RCS2- RCS1- RCS1+ N.C. N.C. N.C. Pin Configuration

Automatic RF MESFET Amplifier Drain-Current Controllers Typical Operating Circuit MAX11014 MAX11015 μC SCLK/SCL REFADC REFDAC AVDD DVDD DIN/SDA ALARM DXP1 DXN1 DXP2 DXN2 RCS1+ RCS1- RCS2+ RCS2- GATE1 GATE2 DRAIN SUPPLY DRAIN SUPPLY RF OUTPUT RF INTPUT RF OUTPUT RF INTPUT OPSAFE1 OPSAFE2 BUSY DGND CNVST +5V EXTERNAL REFERENCE +5V (AT MESFET) (AT MESFET) ADCIN1 ADCIN2 ACLAMP1 ACLAMP2 FILT1 FILT2 FILT3 FILT4 CS/A0 DOUT/A1 N.C./A2 +5V +5V -5V PGAOUT1 PGAOUT2 AGND AVSS GATEVSS SPI/I2C

Automatic RF MESFET Amplifier Drain-Current Controllers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 69 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Heslington

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.) 32, 44, 48L QFN.EPS e L e L A1 AA2 E/2 E D/2 D DETAIL A D2/2 b L k E2/2 (NE-1) X e (ND-1) X e e CLCL CL CL k DETAIL B e L PACKAGE OUTLINE 21-0144 2 32, 44, 48, 56L THIN QFN, 7x7x0.8mm PACKAGE OUTLINE 21-0144 2 32, 44, 48, 56L THIN QFN, 7x7x0.8mm