100370

100370 FAIRCHILD

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I 35% power reduction of the 100170 I 2000V ESD protection I Pin/function compatible with 100170 I Voltage compensated operating range = −4.2V to −5.7V Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP 28-Pin PLCC Order Number Package Number Package Description 100370PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100370QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100370QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range ( −40°C to +85°C)

www.fairchildsemi.com 2 100370 Logic Symbols Single 1-of 8 Application Dual 1-of-4 Application- Pin Descriptions Truth Tables Dual 1-of-4 Mode (M = A2a = Hc = LOW) Single 1-of-8 Mode (M = HIGH; A0b = A1b = Ha = Hb = LOW) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care E 1 = E1a and E1b wired; E2 = E22a and E2b wired Note 1: for Hc = LOW, output states are complemented Pin Names Description Ana, Anb Address Inputs Ena, Enb Enable Inputs M Mode Control Input H a Z0–Z3 (Z0a–Z3a) Polarity Select Input H b Z4–Z7 (Z0b–Z3b) Polarity Select Input H c Common Polarity Select Input Z0–Z7 Single 1-of-8 Data Outputs Zna, Znb Dual 1-of-4 Data Outputs Inputs Active HIGH Outputs Active LOW Outputs (Ha and Hb Inputs HIGH) (Ha and Hb Inputs LOW) E1a E2a A 1a A 0a Z0a Z1a Z2a Z3a Z0a Z1a Z2a Z3a E1b E2b A 1b A 0b Z0b Z1b Z2b Z3b Z0b Z1b Z2b Z3b H XXXLLLLH H H H XH XXLLLLH H H H LLLLHLLLLH H H LLLHLHLLHLHH LLHLLLHLH HLH L LHHL L LHHHHL Inputs Active HIGH Outputs (Note 1) c Input HIGH) E1 E2 A 2a A 1a A 0a Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7 HXXXXLLLLLLLL XHXXXLLLLLLLL L L L L LHLLLLLLL L L L LHLHLLLLLL L L LHLLLHLLLLL L L LHHLLLHLLLL L LHL LLLLLHLLL L LHLHLLLLLHLL L LHHLLLLLLLHL L LHHHLLLLLLLH

3 www.fairchildsemi.com 100370 Logic Diagram (Zn) for 1-of-4 applications.

www.fairchildsemi.com 4 100370 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015.Commercial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Storage Temperature (TSTG ) −65°C to +150°C Maximum Junction Temperature (TJ) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V Case Temperature (TC ) Commercial 0 °C to +85°C Industrial −40°C to +85°C Supply Voltage (VEE ) −5.7V to −4.2V Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage −1025 −955 −870 mV V IN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1035 mV V IN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 240 µAV IN = VIH (Max) IEE Power Supply Current −95 −50 mA Inputs OPEN Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max tPLH Propagation Delay Figures 1, 2 tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL H a, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20%

5 www.fairchildsemi.com 100370 Commercial Version (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Industrial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max tPLH Propagation Delay Figures 1, 2 tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL H a, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% Symbol Parameter TC = −40°CT C = 0°C to +85°C Units Conditions Min Typ Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV V IN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1095 −1035 mV V IN = VIH (Min) Loading with VOLC Output LOW Voltage −1565 −1610 mV or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 300 240 µAV IN = VIH (Max) IEE Power Supply Current −95 −50 −95 −50 mA Inputs OPEN Symbol Parameter TC = −40°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max tPLH Propagation Delay Figures 1, 2 tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL H a, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20%

7 www.fairchildsemi.com 100370 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E

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100370 Low Power Universal Demultiplexer/Decoder

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com