100351

100351 FAIRCHILD

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I 40% power reduction of the 100151 I 2000V ESD protection I Pin/function compatible with 100151 I Voltage compensated operating range: −4.2V to −5.7V I Available to industrial grade temperature range Ordering Code: Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Order Number Package Number Package Description 100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range ( −40°C to +85°C) Pin Names Description D 0–D 5 Data Inputs CP a, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q 0–Q 5 Data Outputs Q 0–Q 5 Complementary Data Outputs

www.fairchildsemi.com 2 100351Truth Tables (Each Flip-flop) Synchronous Operation H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition t+1 = Time after CP positive transition /c17 = LOW-to-HIGH transition Asynchronous Operation Logic Diagram Inputs Outputs D n CP a CP b MR Q n(t+1) L /c17 LL L H /c17 LL H LL /c17 LL HL /c17 LH XH /c17 LQ n(t) X /c17 HL Q n(t) XL LL Q n(t) Inputs Outputs D n CP a CP b MR Q n(t+1) XX XH L

3 www.fairchildsemi.com 100351 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Storage Temperature (TSTG ) −65°C to +150°C Maximum Junction Temperature (TJ) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V Case Temperature (TC ) Commercial 0 °C to +85°C Industrial −40°C to +85°C Supply Voltage (VEE ) −5.7V to −4.2V Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µAV IN = VIL (Min) IIH Input HIGH Current MR 350 D 0–D 5 240 µAV IN = VIH (Max) CP a, CPb 350 IEE Power Supply Current −129 −62 mA Inputs OPEN Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3 tPLH Propagation Delay tPHL CP a, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 0–D 5 0.40 0.40 0.40 ns Figure 5 MR (Release Time) 1.60 1.60 1.60 Figure 4 tH Hold Time 0.80 0.80 0.80 ns Figure 5 D 0–D 5 tPW (H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4 CP a, CPb, MR

www.fairchildsemi.com 4 100351 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack- aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ), or LOW-to-HIGH (tOSLH ), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design. Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3 tPLH Propagation Delay tPHL CP a, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 0–D 5 0.30 0.30 0.30 ns Figure 5 MR (Release Time) 1.50 1.50 1.50 Figure 4 tH Hold Time 0.80 0.80 0.80 ns Figure 5 D 0–D 5 tPW (H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4 CP a, CPb, MR tOSHL Maximum Skew Common Edge PLCC only Output-to-Output Variation 220 220 220 ps (Note 4) Clock to Output Path t OSLH Maximum Skew Common Edge PLCC only Output-to-Output Variation 210 210 210 ps (Note 4) Clock to Output Path t OST Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 240 240 240 ps (Note 4) Clock to Output Path t PS Maximum Skew PLCC only Pin (Signal) Transition Variation 230 230 230 ps (Note 4) Clock to Output Path

5 www.fairchildsemi.com 100351 Industrial Version VEE =−4.2V to −5.7V, VCC =VCCA = GND, TC = 0°C to +85°C (Note 5) Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = −40°CT C = 0° to +85°C Units Conditions Min Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1565 −1610 or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 0.50 µAV IN = VIL (Min) IIH Input HIGH Current MR 350 350 D 0–D 5 240 240 µAV IN = VIH (Max) CP a, CPb 350 350 IEE Power Supply Current −129 −62 −129 −62 mA Inputs OPEN Symbol Parameter TC = −40°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3 tPLH Propagation Delay tPHL CP a, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 0–D 5 0.60 0.30 0.30 ns Figure 5 MR (Release Time) 2.20 1.50 1.50 Figure 4 tH Hold Time 0.60 0.90 0.90 ns Figure 5 D 0–D 5 tPW (H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4 CP a, CPb, MR

www.fairchildsemi.com 8 100351 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E

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100351 Low Power Hex D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com