100341

100341 FAIRCHILD

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I 35% power reduction of the 100141 I 2000V ESD protection I Pin/function compatible with 100141 I Voltage compensated operating range = −4.2V to −5.7V I Available to industrial grade temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Order Number Package Number Package Description 10034SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100341PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100341QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100341QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range ( −40°C to +85°C) Pin Names Description CP Clock Input S 0, S1 Select Inputs D 0, D7 Serial Inputs P0–P7 Parallel Inputs Q 0–Q 7 Data Outputs

www.fairchildsemi.com 2 100341Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care /c17 = LOW-to-HIGH Transition Logic Diagram Function Inputs Outputs D 7 D 0 S1 S0 CP Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 Load Register X X L L /c17 P7 P6 P5 P4 P3 P2 P1 P0 Shift Left X L L H /c17 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 L Shift Left X H L H /c17 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 H Shift Right L X H L /c17 LQ 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Shift Right H X H L /c17 HQ 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Hold X X H H X H o l d XXXXH N o C h a n g e H o l d XXXXL

3 www.fairchildsemi.com 100341 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 4: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. Storage Temperature (TSTG ) −65°C to +150°C Maximum Junction Temperature (TJ) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V Case Temperature (TC ) Commercial 0 °C to +85°C Industrial −40°C to +85°C Supply Voltage (VEE ) −5.7V to −4.2V Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage −1025 −955 −870 mV V IN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1035 mV V IN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for all Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for all Inputs IIL Input LOW Current 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 240 µAV IN = VIH (Max) IEE Power Supply Current Inputs OPEN −157 −75 mA V EE = −4.2V to −4.8V −167 −75 mA V EE = −4.2V to −5.7V Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Max Clock Frequency 400 400 400 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 3 tPHL CP to Output (Note 4) tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D n, Pn 0.65 0.65 0.65 ns Figure 4 Sn 1.60 1.60 1.60 tH Hold D n, Pn 0.80 0.80 0.80 ns Sn 0.60 0.60 0.60 tPW (H) Pulse Width HIGH CP 2.00 2.00 2.00 ns Figure 3

www.fairchildsemi.com 4 100341 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 5: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack- aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ), or LOW-to-HIGH (tOSLH ), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Maximum Clock Frequency 425 425 425 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 3 tPHL CP to Output (Note 5) tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D n, Pn 0.55 0.55 0.55 ns Sn 1.50 1.50 1.50 Figure 4 tH Hold Time D n, Pn 0.70 0.70 0.70 ns Sn 0.50 0.50 0.50 tPW (H) Pulse Width HIGH CP 2.00 2.00 2.00 ns Figure 3 tOSHL Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 6) Clock to Output Path tOSLH Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 6) Clock to Output Path tOST Maximum Skew Opposite Edge PLCC Only Output-to-Output Variation 250 250 250 ps (Note 6) Clock to Output Path tps Maximum Skew PLCC Only Pin (Signal) Transition Variation 250 250 250 ps (Note 6) Clock to Output Path

5 www.fairchildsemi.com 100341 Industrial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 8: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. Symbol Parameter TC = −40°CT C = 0°C to +85°C Units Conditions Min Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV V IN = VIH(Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or V IL (Min) 50 Ω to −2.0V VOHC Output HIGH Voltage −1095 −1035 mV V IN = VIH (Min) Loading with VOLC Output LOW Voltage −1565 −1610 mV or V IL (Max) 50 Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for all Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for all Inputs IIL Input LOW Current 0.50 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 240 240 µAV IN = VIH (Max) IEE Power Supply Current Inputs OPEN −157 −75 −157 −75 mA V EE = −4.2V to −4.8V −167 −75 −167 −75 mA V EE = −4.2V to −5.7V Symbol Parameter TC = −40°CT C = +25°CT C = +85°C Units Conditions Min Max Min Max Min Max fMAX Max Clock Frequency 425 425 425 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 3 tPHL CP to Output (Note 8) tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D n, Pn 0.60 0.55 0.55 ns Sn 1.70 1.50 1.50 Figure 4 tH Hold Time D n, Pn 0.90 0.70 0.70 ns Sn 0.50 0.50 0.50 tPW (H) Pulse Width HIGH CP 2.00 2.00 2.00 ns Figure 3

www.fairchildsemi.com 8 100341 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E

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100341 Low Power 8-Bit Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com