100336

100336 NSC

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 16

Technical content

Features

n 40% power reduction of the 100136 n 2000V ESD protection n Pin/function compatible with 100136 n Voltage compensated operating range= −4.2V to −5.7V n Standard Microcircuit Drawing (SMD) 5962-9230601 Logic Symbol Pin Names

Description

CEP Count Enable Parallel Input (Active LOW) D 0/CET Serial Data Input/Count Enable Trickle Input (Active LOW) S 0–S 2 Select Inputs MR Master Reset Input P 0–P 3 Preset Inputs D 3 Serial Data Input TC Terminal Count Output Q 0–Q 3 Data Outputs Q 0–Q 3 Complementary Data Outputs DS100307-1 August 1998

100336 Low Power 4-Stage Counter/Shift Register

© 1998 National Semiconductor Corporation DS100307 www.national.com

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Q 0 = LSB Inputs Outputs MR S 2 S1 S0 CEP D 0/CET D 3 CP Q 3 Q 2 Q 1 Q 0 TC Mode LLLL X X X N P3 P2 P1 P0 L Preset (Parallel Load) LLLHX X X N Q 3 Q 2 Q 1 Q 0 L Invert LLHL X X X N D 3 Q 3 Q 2 Q 1 D 3 Shift to LSB LLH HX X X N Q 2 Q 1 Q 0 D 0 Q 3(Note 1) Shift to MSB LHLL L L X N (Q0–3) minus 1 1 Count Down LHLL H L XX Q 3 Q 2 Q 1 Q 0 1 Count Down with CEP not active LHLL X H XX Q 3 Q 2 Q 1 Q 0 H Count Down with CET not active LHLH X X X N LLLL H Clear LHHL L L X N (Q0–3) plus 1 2 Count Up LHHL H L XX Q 3 Q 2 Q 1 Q 0 2 Count Up with CEP not active LHHL X H XX Q 3 Q 2 Q 1 Q 0 H Count Up with CET not active LHHH X X XX Q 3 Q 2 Q 1 Q 0 H Hold HLLL X X XXLLLL L HLLHX X XXLLLL L HLHL X X XX LLLL L HLH HX X XXLLLL L Asynchronous H HLL X L XXLLLL L Master Reset H HLL X H XXLLLL H H HLHX X XXLLLL H H H HL X X XXLLLL H HHHH X X XX LLLL H 1 = Li fQ0–Q 3 = LLLL Hi fQ0–Q 3 ≠ LLLL 2 = Li fQ0–Q 3 = HHHH Hi fQ0–Q 3 ≠ HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care N = LOW-to-HIGH Transition Note 1:Before the clock, TC is Q3 After the clock, TC is Q2 www.national.com 4

Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (T STG ) −65˚C to +150˚C Maximum Junction Temperature (TJ) Ceramic +175˚C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V Recommended Operating Conditions Case Temperature (TC ) Military −55˚C to +125˚C Supply Voltage (VEE ) −5.7V to −4.2V Note 2:Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3:ESD testing conforms to MIL-STD-883, Method 3015. Military Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, T C = −55˚C to +125˚C Symbol Parameter Min Max Units T C Conditions Notes VOH Output HIGH Voltage −1025 −870 mV 0˚C to +125˚C V IN = VIH (Max) Loading with −1085 −870 mV −55˚C or V IL (Min) 50Ω to −2.0V (Notes 4, 5, 6) VOL Output LOW Voltage −1830 −1620 mV 0˚C to +125˚C −1830 −1555 mV −55˚C VOHC Output HIGH Voltage −1035 mV 0˚C to +125˚C V IN = VIH (Min) Loading with −1085 mV −55˚C or V IL (Max) 50Ω to −2.0V (Notes 4, 5, 6) VOLC Output LOW Voltage −1610 mV 0˚C to +125˚C −1555 mV −55˚C VIH Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 4, 5, 6, 7) +125˚C for All Inputs VIL Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 4, 5, 6, 7) +125˚C for All Inputs IIL Input LOW Current 0.50 µA −55˚C to V EE = −4.2V (Notes 4, 5, 6) +125˚C V IN = VIL (Min) IIH Input HIGH Current 240 µA 0˚C to V EE = −5.7V +125˚C V IN = VIH(Max) (Notes 4, 5, 6) 340 µA −55˚C IEE Power Supply Current −55˚C Inputs Open −185 −70 mA to V EE = −4.2V to −4.8V (Notes 4, 5, 6) −195 −70 +125˚C V EE = −4.2V to −5.7V Note 4:F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 5:Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6:Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7:Guaranteed by applying specified input conditon and testing VOH /VOL . 5 www.national.com

VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter T C = −55˚C T C = +25˚C T C = +125˚ Units Conditions Notes Min Max Min Max Min Max fshift Shift Frequency 325 325 325 MHz Figures 2, 3 (Note 11) tPHL CP to Qn,Q n (Notes 8, 9, 10, 12) tPHL CP to TC (Shift) tPHL CP to TC (Count) tPHL MR to Qn,Q n (Notes 8, 9, 10, 12) tPHL MR to TC (Count) MR to TC (Shift) tPHL D 0/CET to TC Figures 1, 5 (Notes 8, 9, 10, 12) tPHL Sn to TC tTHL 20% to 80% ,8 0% to 20% ts Setup Time D 3 1.40 1.40 1.40 Pn 1.70 1.70 1.70 D 0/CET 1.80 1.80 1.80 ns Figure 6 (Note 11) CEP 1.80 1.80 1.80 Sn 3.30 3.30 3.30 MR (Release Time) 2.60 2.60 2.60 th Hold Time D 3 0.90 0.90 0.90 Pn 1.00 1.00 1.00 ns Figure 6 (Note 11) D 0/CET 0.70 0.70 0.70 CEP 0.60 0.60 0.60 Sn 0.00 0.00 0.00 tpw (H) Pulse Width HIGH: CP 1.60 1.60 1.60 ns Figures 3, 4 (Note 11) MR 2.00 2.00 2.00 Note 8:F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold tempertures. Note 9:Screen tested 100% on each device at +25˚C temperature only, Subgroups A9. Note 10:Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroups A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 11:Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 12:The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. www.national.com 6

FIGURE 1. AC Test Circuit

Switching Waveforms (Continued)

Applications

Note: *Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H. DS100307-21 Note: *Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H. FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)

Applications(Continued) Slow Expansion Scheme DS100307-13 Fast Expansion Scheme DS100307-14 13 www.national.com

Physical Dimensionsinches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) 24-Lead Quad Cerpak (F) 15 www.national.com

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.