100336

100336 FAIRCHILD

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Features

I 40% power reduction of the 100136 I 2000V ESD protection I Pin/function compatible with 100136 I Voltage compensated operating range = −4.2V to −5.7V I Available to industrial grade temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Logic Symbol Order Number Package Number Package Description 100336SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100336PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100336QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100336QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range ( −40°C to +85°C)

www.fairchildsemi.com 2 100336 Function Select Table Pin Descriptions Truth Table Q 0 = LSB 1 = L if Q0–Q 3 = LLLL H if Q0–Q 3 ≠ LLLL 2 = L if Q0–Q 3 = HHHH H if Q0–Q 3 ≠ HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care /c17 = LOW-to-HIGH Transition Note 1: Before the clock, TC is Q3 After the clock, TC is Q2 S2 S1 S0 Function L L L Parallel Load L L H Complement L H L Shift Left L H H Shift Right H L L Count Down HLH C l e a r H H L Count Up HHH H o l d Pin Names Description CP Clock Pulse Input CEP Count Enable Parallel Input (Active LOW) D 0/CET Serial Data Input/Count Enable Trickle Input (Active LOW) S0–S2 Select Inputs MR Master Reset Input P0–P3 Preset Inputs D 3 Serial Data Input TC Terminal Count Output Q 0–Q 3 Data Outputs Q 0–Q 3 Complementary Data Outputs Inputs Outputs MR S 2 S1 S0 CEP D 0/CET D 3 CP Q 3 Q 2 Q 1 Q 0 TC Mode L LLL X X X /c17 P3 P2 P1 P0 L Preset (Parallel Load) LL L H X X X /c17 Q 3 Q 2 Q 1 Q 0 LI n v e r t LL H L X X X /c17 D 3 Q 3 Q 2 Q 1 D 3 Shift to LSB LL H H X X X /c17 Q 2 Q 1 Q 0 D 0 Q 3 (Note 1) Shift to MSB LH L L L L X /c17 (Q0–3) minus 1 1 Count Down LH L L H L XX Q 3 Q 2 Q 1 Q 0 1 Count Down with CEP not active LH L L X H XX Q 3 Q 2 Q 1 Q 0 H Count Down with CET not active LH L H X X X /c17 LLLL H C l e a r LH H L L L X /c17 (Q0–3) plus 1 2 Count Up LH H L H L XX Q 3 Q 2 Q 1 Q 0 2 Count Up with CEP not active LH H L X H XX Q 3 Q 2 Q 1 Q 0 H Count Up with CET not active L HHH X X X XQ 3 Q 2 Q 1 Q 0 HH o l d HLLL X X XX L L L L L HL L H X X XXLLLL L HL H L X X XXLLLL L H L H H X X X X L L L L L Asynchronous H H L L X L X X L L L L L Master Reset HH L L X H XXLLLL H HH L H X X XXLLLL H HH H L X X XXLLLL H H HHH X X X X L L L L H

3 www.fairchildsemi.com 100336 Logic Diagram

www.fairchildsemi.com 4 100336 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional opera- tion under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. Storage Temperature (TSTG ) −65°C to +150°C Maximum Junction Temperature (TJ) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥ 2000V Case Temperature (TC ) Commercial 0 °C to +85°C Industrial −40°C to +85°C Supply Voltage (VEE ) −5.7V to −4.2V Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage −1025 −955 −870 mV V IN =VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or V IL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV V IN = VIH(Min) Loading with VOLC Output LOW Voltage −1610 mV or V IL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 240 µAV IN = VIH (Max) IEE Power Supply Current −165 −80 Inputs Open

5 www.fairchildsemi.com 100336 Commercial Version (Continued) DIP AC Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions M i nM a xM i nM a xM i nM a x fSHIFT Shift Frequency 300 300 300 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 3 tPHL CP to Qn, Qn (Note 5) tPLH Propagation Delay Figures 1, 7, 8 tPHL CP to TC (Shift) (Note 5) tPLH Propagation Delay Figures 1, 9 tPHL CP to TC (Count) (Note 5) tPLH Propagation Delay Figures 1, 4 tPHL MR to Qn, Qn (Note 5) tPLH Propagation Delay Figures 1, 12 tPHL MR to TC (Count) (Note 5) tPHL Propagation Delay Figures 1, 10, 11 MR to TC (Shift) (Note 5) tPLH Propagation Delay tPHL D 0/CET to TC Figures 1, 5 tPLH Propagation Delay (Note 5) tPHL Sn to TC tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 3 1.00 1.00 1.00 Pn 1.50 1.50 1.50 D 0/CET 1.30 1.30 1.30 ns Figures 6, 4 CEP 1.40 1.40 1.40 Sn 3.40 3.40 3.40 MR (Release Time) 2.60 2.60 2.60 tH Hold Time D 3 0.40 0.40 0.40 Pn 0.30 0.30 0.30 ns Figure 6 D 0/CET 0.30 0.30 0.30 CEP 0.20 0.20 0.20 Sn 0.10 0.10 0.10 tPW (H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4 CP , MR

www.fairchildsemi.com 6 100336 SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 6: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack- aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ), or LOW-to-HIGH (tOSLH ), or in opposite directions both HL and LH (tOST ). Parameters tOST and tps guaranteed by design Symbol Parameter TC = 0°CT C = +25°CT C = +85°C Units Conditions M i nM a xM i nM a xM i nM a x fSHIFT Shift Frequency 350 350 350 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 2 tPHL CP to Qn, Qn (Note 6) tPLH Propagation Delay Figures 1, 7, 8 tPHL CP to TC (Shift) (Note 6) tPLH Propagation Delay Figures 1, 9 tPHL CP to TC (Count) (Note 6) tPLH Propagation Delay Figures 1, 4 tPHL MR to Qn, Qn (Note 6) tPLH Propagation Delay Figures 1, 12 tPHL MR to TC (Count) (Note 6) tPHL Propagation Delay Figures 1, 10, 11 MR to TC (Shift) (Note 6) tPLH Propagation Delay tPHL D 0/CET to TC Figures 1, 5 tPLH Propagation Delay (Note 6) tPHL Sn to TC tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 3 0.90 0.90 0.90 Pn 1.40 1.40 1.40 ns Figures 4, 6 D 0/CET 1.20 1.20 1.20 CEP 1.30 1.30 1.30 Sn 3.30 3.30 3.30 MR (Release Time) 2.50 2.50 2.50 tH Hold Time D 3 0.30 0.30 0.30 Pn 0.20 0.20 0.20 ns Figure 6 D 0/CET 0.20 0.20 0.20 CEP 0.10 0.10 0.10 Sn 0.00 0.00 0.00 tPW (H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4 CP, MR tOSHL Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 7) Clock to Output Path tOSLH Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 7) Clock to Output Path tOST Maximum Skew Opposite Edge PLCC Only Output-to-Output Variation 230 230 230 ps (Note 7) Clock to Output Path tPS Maximum Skew PLCC Only Pin (Signal) Transition Variation 245 245 245 ps (Note 7) Clock to Output Path

7 www.fairchildsemi.com 100336 Industrial Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under “worst case” conditions. VEE = −4.2V to −5.7V, VCC = VCCA = GND Note 9: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. Symbol Parameter TC = −40°CT C = 0°C to +85°C Units Conditions Min Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV V IN =VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or V IL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 −1035 mV V IN = VIH(Min) Loading with VOLC Output LOW Voltage −1565 −1610 mV or V IL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 0.50 µAV IN = VIL (Min) IIH Input HIGH Current 240 240 µAV IN = VIH (Max) IEE Power Supply Current −165 −75 −165 −80 mA Inputs Open Symbol Parameter TC = −40°CT C = +25°CT C = +85°C Units Conditions M i nM a xM i nM a xM i nM a x fSHIFT Shift Frequency 325 350 350 MHz Figures 2, 3 tPLH Propagation Delay Figures 1, 3 tPHL CP to Qn, Qn (Note 9) tPLH Propagation Delay Figures 1, 7, 8 tPHL CP to TC (Shift) (Note 9) tPLH Propagation Delay Figures 1, 9 tPHL CP to TC (Count) (Note 9) tPLH Propagation Delay Figures 1, 4 tPHL MR to Qn, Qn (Note 9) tPLH Propagation Delay Figures 1, 12 tPHL MR to TC (Count) (Note 9) tPHL Propagation Delay Figures 1, 10, 11 MR to TC (Shift) (Note 9) tPLH Propagation Delay tPHL D 0/CET to TC Figures 1, 5 tPLH Propagation Delay (Note 9) tPHL Sn to TC tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D 3 1.40 0.90 0.90 Pn 1.70 1.40 1.40 ns Figure 6 D 0/CET 1.80 1.20 1.20 CEP 1.80 1.30 1.30 Sn 3.30 3.30 3.30 MR (Release Time) 2.60 2.50 2.50 tH Hold Time D 3 0.90 0.30 0.30 Pn 1.00 0.20 0.20 ns Figure 6D 0/CET 0.70 0.20 0.20 CEP 0.60 0.10 0.10 Sn 0.00 0.00 0.00 tPW (H) Pulse Width HIGH CP, MR 2.20 2.00 2.00 ns Figures 3, 4

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Applications

3-Stage Divider, Preset Count Down Mode Note: If S0 = S1 = S2 = LOW, then TC = LOW Slow Expansion Scheme Fast Expansion Scheme

13 www.fairchildsemi.com 100336 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E

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100336 Low Power 4-Stage Counter/Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com